JPH0821021B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a data processing device for accessing a peripheral device having a slow response, and particularly to improving throughput during waiting for access.

(Prior Art) In a computer system including a large number of peripheral devices, a central processing unit (CPU) and individual peripheral devices cannot be directly connected by a bus, and an appropriate interface is used.

The bus control device is an interface on the CPU side and generally comprises a data buffer, an address buffer, and timing control logic.

In this type of system, the CPU temporarily stores the instruction fetched via the data buffer of the bus control device in the instruction register and then decodes it with the instruction decoder,
The instruction execution unit (arithmetic logic unit or the like) executes the instruction. If the execution of this instruction requires read access to an external peripheral device (memory, I / O device, etc.), the CPU sends an address to the address bus via the address buffer of the bus controller. At the same time as sending, a read control signal is output from the timing control logic on the control bus. When data is sent from the peripheral device in response to this, the data is taken into the data buffer of the bus control device and transferred from there to a predetermined register in the CPU.

(Problems to be Solved by the Invention) By the way, a wait cycle is inserted in the execution of the CPU from the read access to the reception of the data. Therefore, if the peripheral device responds slowly, the wait cycle continues (extends) for a while and CPU processing is interrupted during that time. If the data obtained by read access will be used in the next step, it is safe to wait, but if it is not, the CPU will be idle in vain, which is preferable in terms of throughput. Absent.

As described above, conventionally, since the wait cycle is inserted according to the response speed of the peripheral device, the processing speed of the CPU is reduced.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a data processing device that improves throughput during read access waiting for a peripheral device having a slow response.

(Means for Solving the Problems) In order to achieve the above-mentioned object, the present invention provides a slow response in a data processing device in which a central processing unit accesses an external peripheral device via a bus control device. Determining means for preliminarily registering the peripheral device and for generating a predetermined control signal and identification signal by determining when the read access from the central processing unit is for the registered peripheral device; Access control means for outputting an access request signal to the peripheral device in response to the control signal and for causing the bus control device to perform read access in response to the ready signal from the peripheral device; and in response to the identification signal. Identify the register in the central processing unit that is the destination of the data by read access and read by the bus control unit. The register access control means is provided for inserting a wait cycle into the execution cycle of the central processing unit only when an access to the register occurs until the execution of the access is completed.

(Operation) In the present invention, in a read access to a peripheral device having a slow response, while waiting for a response from the peripheral device, a wait cycle is unconditionally (only for waiting for a response) in the execution cycle of the central processing unit. Is never inserted. Standby / execution of read access is performed by access control means, bus control means, and register access control means. Therefore, the instruction execution unit of the central processing unit can proceed to another processing.

The register access control means identifies the destination register of the data obtained by the read access on the basis of the identification signal from the determination means, and, for example, a flag for that register until the read access is completed.
Set a bit. In the meantime, even if the instruction execution unit tries to access the register, the register contents are not fixed yet. Therefore, only when such a register access is made, the register access control means inserts a wait cycle to read the register. The instruction execution unit is put on standby until the access is completed.

As described above, since the wait cycle is inserted at that point only when the register access occurs and the execution cycle is not interrupted in principle, it is possible to prevent the deterioration of the throughput.

Embodiment An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 shows the main configuration of the data processing apparatus according to this embodiment.

The central processing unit (CPU) is composed of an instruction execution unit 10, an instruction decoder 12, an instruction register 14, a register array 16, a register access control circuit 18, and an address register 20.

The instruction execution unit 10 includes an arithmetic logic unit that performs arithmetic processing, a timing control circuit that generates control signals necessary for executing instructions, and the like. Instruction decoder 12
Is the instruction (OP) latched (fetched) in the instruction register.
Code). Register array 16 collects a number of general purpose registers, stack pointers, program counters, and the like. Address register 20 is a buffer that temporarily latches the address to be sent out from the register in register array 16.

The register access control circuit 18 is a register array.
Manages flag bits that indicate whether or not each general purpose register in 16 is accessible. This control circuit 18
When receiving the identification signal DE from the condition determination logic 22 described later, the flag is set for the general-purpose register designated by the identification signal DE (the flag bit is set to the logical value "1"), and the bus control unit 34 When the access completion signal EN is received from the timing circuit 36, the flag is defeated (the flag bit is set to the logical value "0"). When the instruction execution unit 10 tries to access the general-purpose register while this flag is set, the register access control circuit 18 gives a wait request signal WS of logical value "0" through the AND gate 30 to A wait cycle is inserted in the execution cycle of the execution unit 10.

The condition judgment logic 28 has a memory or a table in which peripheral devices having a slow response are registered in advance. The registration method may be, for example, a method of associating such a peripheral device with all addresses used for access thereto. Information required for registration is internal data bus
It is given from the instruction execution unit 10 via 22.

When the read access is performed, the condition judgment logic 28
An address is given from the address register 20 via the internal address bus 24, and a read access request signal RA is given from the instruction execution unit 10. Based on the input information and the registration information, the condition judgment logic 28 judges whether or not this read access is for the registered peripheral device (peripheral device with slow response), and if so, The access control circuit 32 is provided with a control signal MS for instructing an access request to the peripheral device, and the identification signal DE for specifying a general-purpose register as a destination of the data sent from the peripheral device is register-accessed. It is given to the control circuit 18. If it is determined that the read access is for a peripheral device that is not registered, the condition determination logic
28 supplies a control signal CE to the timing control circuit 36 to instruct a normal (same as the conventional) read access operation.

Upon receiving the control signal MS from the condition determination logic 28, the access control circuit 32 outputs an access request signal, for example, REQ A, to the peripheral device designated by the signal MS on the control bus 42, and the peripheral device outputs the access request signal. Ready signal RE
Wait for ADY. When the ready signal READY is sent, the access control circuit 32 gives the start signal ST to the timing control circuit 36 of the bus control unit 34.

The bus control unit 34 comprises a timing control circuit 36, an address buffer 38, and a data buffer 40 as in the conventional case, and when receiving a start signal ST from the access control circuit 32, it starts a read access operation, Is completed, the register access control circuit 18
Give access completion signal EN. Also, the condition judgment logic
When the control signal CE from 28 is received, the conventional read access is executed.

Although the wait control signal is supplied from the timing control circuit 18 to the AND gate 30, it is not related to read access to a peripheral device having a slow response, and is always considered as "1" in this embodiment. Good. That is, when the wait request signal WS of "0" is generated from the register access control circuit 18, the output signal of the AND gate 30 is "0".
Therefore, it may be considered that the wait request is input to the instruction execution unit 10.

 Next, the operation of the apparatus of this embodiment will be described with reference to FIG.

In this illustrated example, the instruction execution unit 10 executing CPU processing first executes instructions in register array 16 to transfer data from a slow-responding external memory to register A in register array 16. H register and L
The content (address) of the register is sent to the address register 20 and the read access request signal RA is given to the condition judgment logic 28 ().

The condition judgment logic 28 receives the address and the read access request signal RA and makes a judgment. In this case, since the read access is directed to the registered peripheral device (external memory), the condition judgment logic 28 outputs the control signal MS for instructing the access request to the external memory to the access circuit.
At the same time as 32, an identification signal DE designating the A register which is the destination in this read access is given to the register access control circuit 18 ().

Upon receiving the identification signal DE, the register access control circuit 18 receives the flag bit FA for the A register.
Is a logical value "1" ().

The access control circuit 32 sends an access request signal REQ A to the external memory in response to the control signal MS ().

The bus control unit 34 latches the address from the address register 20 ().

The instruction execution unit 10 is a register access control circuit.
Since the flag bit FA was set at 18, this external memory →
Knowing that the A register transfer instruction is incomplete, other processing is executed (). Then, the A register → B register transfer instruction must be executed at a certain step (), and the A register is to be accessed through the register access control circuit 18 (-1).

However, at this point in time, since the data from the external memory by the previous read access has not been taken into the A register, the flag of the A register is still set. Therefore, the register access control circuit 18 sets the wait request signal WS as a logical value "0" and responds to the instruction execution unit 10 (). As a result, the instruction execution unit 10 inserts a wait sille (wait state Tw and waits (-2).

Out of which, the external memory is ready and ready signal READ
Y is sent to the access control circuit 32 (). Then, the access control circuit 32 gives the start signal ST to the timing circuit 36, so that the bus control unit 34 executes the read access. That is, the read control signal READ is sent from the timing circuit 36 to the control bus 42 and the address buffer 38
Address is sent out on the address bus 44, and the data from the external memory is taken into the data buffer 40 via the data bus 46. And read access completion signal
Send EN to the register access control circuit 18 ().

Upon receiving the read access completion signal EN, the register access control circuit 18 stores the data from the data buffer 40 in the A register and sets the flag bit FA to "0".
And at the same time, the wait request signal WS for the instruction execution unit 10 is returned to "1" ().

As a result, the instruction execution unit 10 ends the wait cycle and resumes the execution of the interrupted A register → B register transfer instruction. That is, the A register is accessed and the data there is stored in the B register (-
3).

As described above, in this embodiment, when performing a read access to a peripheral device having a slow response, the instruction execution unit unit 10 does not need to wait according to the peripheral device,
You can proceed to perform other processing. The execution / management of the read access is performed by the access control circuit 32, the bus control unit 34, and the register access control circuit 18, and before it is completed, that is, before data is stored in the destination register. Only when an attempt is made to access the register, the instruction execution unit 10 inserts the wait cycle for the first time in the execution cycle. Therefore, it is possible to prevent the throughput of the instruction execution unit 10 from being lowered even while waiting for such a read access.

(Effect of the Invention) As described above, according to the present invention, when a read access is made to a peripheral device having a slow response, a wait cycle is not unconditionally inserted, and the destination access is completed before the read access is completed. Since the wait cycle is inserted at that time only when the access to the register occurs, the throughput of such a read access while waiting can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing the main configuration of a data processing apparatus according to an embodiment of the present invention, and FIG. 2 is a timing chart of the operation of each part for explaining the operation of the apparatus of FIG. . 10 ... Instruction execution unit, 16 ... Register array, 18
...... Register access control circuit, 20 ...... Address register, 28 ...... Condition judgment logic, 32 ...... Access control circuit, 36 ...... Bus control unit, 36 ...... Timing control circuit, 38 ...... Address ・Buffer, 40 ...
Data buffer.

Claims (1)

[Claims] 1. A data processing device in which a central processing unit accesses an external peripheral device via a bus control device, and a peripheral device having a slow response is registered in advance, and a read from the central processing unit. Determination means for determining when an access is to the registered peripheral device and generating a predetermined control signal and an identification signal; and an access request to the registered peripheral device in response to the control signal. A signal to the bus controller in response to a ready signal from the peripheral device.
The access control means for executing the access and the register in the central processing unit which becomes the data destination by the read access in response to the identification signal are identified, and the execution of the read access by the bus control device is completed. Register access control means for inserting a wait cycle into the execution cycle of the central processing unit only when an access to the register occurs before the data processing device.