JP2001092774A - Dma burst transfer controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To execute and process a preferential external access instruction in real time even during DMA burst transfer. SOLUTION: An address space range of external access which is desired to be preferentially processed to the DMA burst transfer is set in internal registers 6, 7 of a RISC. An address space comparing part 8 detects whether an operand in instruction data in an instruction cache 2 exists in the address space range. An area bit to be set as ON when the operand hits is provided in the tag part of the instruction cache. The area bit is searched by an area bit searching part 3 when the instruction to be executed by a computer hits the instruction cache. When detection of ON setting is reported from the area bit searching part when a burst transfer enabling signal is asserted by a DMA control part 4, control to interrupt the cycle of the external access is performed by an external bus arbitration part by interrupting the DMA transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to burst transfer control for DMA data transfer.

[0002]

2. Description of the Related Art One of the prior arts of this kind is disclosed in
This is described as a “data transfer control device” in JP-A-91354. This device automatically switches the operation mode of the DMA data transfer from a burst transfer mode in which DMA cycles are continuously performed by an interrupt signal to a cycle stealing transfer mode in which a CPU cycle and a DMA cycle can be alternately operated as necessary. Things. for that reason,
A DMA controller for switching the operation mode of the DMA data transfer between a burst operation mode and a cycle stealing operation mode, and intercepting an interrupt request signal generated from an input / output device and storing a position of a stack point of the CPU in the interrupt processing. A switching control unit that outputs a switching control signal for switching the mode of the DMA processing from the burst operation mode to the cycle stealing operation mode to the DMA controller. The switching control unit monitors access to the stack area provided in the external storage device, and
When U reads the location of the stack point,
When it is determined that the interrupt has been completed, the mode is switched to the burst operation mode again and the DMA processing is continued.

Another example of this kind of prior art is described as a "DMA controller" in Japanese Patent Application Laid-Open No. 4-306754. The controller sets (or resets) the flag means to a predetermined state when starting the execution of DMA. When an interrupt occurs during DMA execution, the DMA processing is temporarily interrupted, and the bus control is passed to the CPU. The CPU immediately starts the interrupt processing. During the interrupt processing, the state of the flag means remains in the predetermined state,
Various parameters are held as they were immediately before the DMA interruption. When the DMA execution command signal is given from the CPU after the interrupt processing is completed, first, the state of the flag means is referred to. DMA is started from the state at the time of DMA interruption based on the various parameters that have been set.

[0004]

However, according to the technique described in Japanese Patent Application Laid-Open No. 1-291354, the DMA
Since the data transfer can be switched from the burst mode to the cycle stealing mode only in the interrupt processing routine, the first problem is that it cannot respond to an urgent event in a normal program other than the interrupt processing. There is a point. Therefore, for example, when it becomes necessary to stop the rotating motor urgently,
For events that are determined by the instruction group in the normal program,
Real-time processing is not possible.

Further, in the cycle steal mode in which the DMA cycle and the CPU cycle are alternately and continuously operated one cycle at a time, there is a second problem that the use efficiency of the system bus deteriorates. For example, when a loop is executed by a loop instruction or the like in an interrupt process, an idle cycle in which no system bus is executed during a CPU cycle, and a wasteful time is added, resulting in a decrease in system performance.

In the technique described in Japanese Patent Application Laid-Open No. 4-306754, the DMA is completely stopped during the execution of the interrupt cycle. There is a problem that the system may fail.

An object of the present invention is to provide a DMA burst transfer control device capable of interrupting a priority external access cycle even during a DMA burst transfer.

Another object of the present invention is to provide a DMA burst transfer control device capable of improving traffic on a transmission line controlled by a microcomputer.

[0009]

According to a first aspect of the present invention, there is provided a DMA burst transfer control device, comprising: a tag portion for storing an execution address in an instruction cache in a reduced instruction set computer (RISC); An area bit indicating that an instruction is present is provided, and when the area bit is ON, a valid external access cycle is interrupted even during DMA burst transfer.

A DMA burst transfer control device according to a second aspect of the present invention is a DMA burst transfer control device in a reduced instruction set computer for setting an internal address space range of an external access which is to be preferentially processed for a DMA burst transfer. A register and an address space comparing unit for detecting whether an operand in the instruction data stored in the instruction cache is in the address space range, and
An area bit provided in a tag portion of an instruction cache, which is set to ON when a hit is made based on the result of the comparison, and a search for the area bit when an instruction executed by the computer hits the instruction cache; An area bit search unit for detecting the ON setting; and a DM for asserting a burst transfer enable signal during DMA transfer.
A control unit, and when the detection of the ON setting is notified from the area bit search unit while the burst transfer enable signal is asserted, the DMA transfer is interrupted.
An external bus arbitration unit that performs control for interrupting the external access cycle.

Further, in the DMA burst transfer control device according to the present invention, the area bit search unit has a function of searching for a required continuous external access, and the continuous external access competes with the DMA burst transfer. The external bus arbitration unit communicates with the external access and the DM.
A burst transfer is controlled to operate alternately.

Further, the DMA burst transfer control device of the present invention is characterized in that the ON control of the area bit is determined at the time of booting the microcomputer or at the time of fetching an instruction from an external storage device when a cache miss occurs. I do.

More specifically, the DMA burst transfer control device of the present invention provides an external access instruction (load instruction, store instruction, input instruction, output instruction, etc.) at the position of instruction data in the instruction cache (2 in FIG. 1). Means for turning on the area bit of the tag portion (1 in FIG. 2) and an area bit search unit (3 in FIG. 1) for searching for the continuous presence of the area bit. It has means for notifying the bus arbitration unit (5 in FIG. 1).

In the external bus arbitration unit, when the DMA control unit (4 in FIG. 1) is performing a burst transfer in which a large amount of data is transferred at a time, the burst transfer is temporarily suspended, and the priority instruction cache (FIG. 1) is used. The cycle of the external access instruction in 2) is executed, and the area bits are continuously
In the case of N, there is a means for alternately transferring a DMA cycle and a valid external bus access.

A general reduced instruction set computer (R)
ISC) has a configuration in which a DMA operation and a normal program operation can be processed in parallel when an instruction in the instruction cache is hit even during DMA data transfer. According to the present invention, by providing a means for recognizing the presence of a preferential external access instruction in a hit normal instruction, it becomes possible to interrupt an external bus access cycle even during a DMA burst transfer. As a result, an external bus can be efficiently used in external access to an external input / output device that requires urgency during a normal program, so that a device with significantly improved system performance can be realized.

Also, if the area bits are continuous and the DMA
During a burst transfer, by alternately executing a DMA cycle and a valid external bus cycle, the number of idle cycles in which nothing is performed is reduced, and a RISC with high data transfer efficiency can be provided.

[0017]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the present embodiment, a central processing unit 1 having two internal registers (6 and 7 in FIG. 2) for setting an address space range, and an external access to an address space set in the internal registers 6 and 7 An instruction cache 2 having an area bit for storing a result of searching for an instruction in a tag portion, and an area bit search section 3 for searching whether there is continuity of ON of the area bit.
When the DMA control unit 4 and the area bit search unit 3 notify the ON of the area bits and the DMA control unit 4 notifies that the DMA burst transfer is being performed,
This is a microcomputer including an external bus arbitration unit 5 for performing control to interrupt a valid external bus access cycle even during A transfer.

FIG. 2 shows the instruction cache 2 and its peripheral circuits in the microcomputer. In FIG. 2, the instruction cache 2 includes a plurality of entries including a tag section having area bits and an instruction data section. The instruction address includes a tag section and an index section. The tag comparing section 10 compares the tag section with the tag section of the instruction cache 2 specified by the index section, and if a hit occurs, the instruction data of the instruction cache 2 is executed by the central processing section 1. The address space comparing section 8 compares the address space determined by the internal register 6 as a system register with the address in the instruction data of the instruction cache 2, and turns on the area bit of the tag section if they match. I do.

Next, the operation of this embodiment will be described.

When the program is executed, the instruction cache 2 is initially empty, so that the instruction is fetched from the external storage device, and the central processing unit 1 executes processing based on the instruction. At this time, in order to utilize the temporal or spatial locality of the program at the time of subsequent processing execution, the upper address of the program counter value of the processing execution result is copied to a tag portion in the instruction cache 2 and
In addition, a process of storing corresponding instruction data in the same entry is generally performed.

The tag portion in the instruction address 9 to be executed currently contains the upper address of the program counter value. The tag comparing section 10 compares the upper address of the tag section with the upper address of the past program counter value stored in the tag section of the instruction cache 2.
When there is a loop process in the instruction group, a match of the upper address may be detected as a result of the comparison. In that case, it is determined that a valid instruction group exists in the instruction cache 2, and a corresponding entry in the instruction cache 2 is selected from the index in the instruction address section 5 and stored in the instruction data portion. Read instruction data. As a result, the instruction can be read directly from the instruction cache 2 without fetching the instruction from the external storage device, so that high-speed access is possible.

The internal register 6 of the central processing unit 1
Can set a start address r1 of an arbitrary address space, and an internal register 7 can set an end address r2.
An address space defined by the start address r1 and the end address r2 is used for setting an external memory address space or an I / O address space to be processed with priority even in DMA, and the internal registers 6 and 7 are used. By rewriting, it can be easily changed even during operation.

The address comparing section 8 includes a start address r1 held by the internal register 6, an end address r2 held by the internal register 7, a load instruction, a store instruction, and a load instruction stored in the instruction data section of the instruction cache 2. An address to be externally accessed is extracted from the operands (addresses) of the input and output instructions, and it is determined whether or not this address is an external access address in an address space defined by a start address r1 and an end address r2. Then, as a result of the determination, if the address is an external address in the address space, the corresponding area bit provided in the tag portion in the instruction cache 2 is turned ON. Such ON control of the area bit is performed by making a determination when fetching an instruction from an external storage device at the time of boot or cache miss.

In general DMA transfer, as shown in FIG. 3, a DM which is a transfer request from an external peripheral device is used.
The ARQ signal is turned ON (high level), and the DMA control unit 4
Turns on the DMACK signal indicating a response if
(High level) to start data transfer.

At this time, the DMA controller 4 asserts the burst transfer ENB signal during the burst transfer and notifies the external bus arbitration unit 5. On the other hand, area bit search section 3
Detects that the area bit is ON when hitting the instruction cache 2 and notifies the external bus arbitration unit 5.

The area bit of the external bus arbitration unit 5 is ON.
If the burst transfer ENB signal from the DMA controller 4 is asserted, it is determined that there is a valid external access command. Then, even during the DMA burst transfer, the DMA
The CK signal is temporarily negated to execute a preferential external access cycle, and after execution, the negated DM is again executed.
Assert the ACK signal to execute DMA burst transfer. In FIG. 3, since the existence of a valid external access instruction EXT1 is recognized at the time of the DMA burst cycle of the address DMA3, the external access cycle is preferentially executed, and thereafter, the DMA burst cycle of the address DMA3 is executed. It has been shown.

Next, when the ON of the area bit is continuous, the continuity of the area bit in the instruction cache 2 is checked in advance, and the area bit is continuously turned ON for two or more area bits.
Then, a time-division process is performed in which a DMA burst transfer is performed for one DMA cycle and one valid external access cycle. FIG. 4 is a timing chart showing such a competitive operation. In FIG. 4, since the external access commands EXT1 and EXT2 whose area bits are ON are continuous, as shown in the external bus state, DMA1 → EXT
1 → DMA2 → EXT2 → DMA3
The figure shows that the A instruction and the external access instruction are executed alternately.

When there is an external access to an address space outside the address space specified by the internal registers 6 and 7, the DMA burst transfer cycle is terminated, and in the example of FIG. Outside external access is performed.

[0030]

According to the present invention, in the normal DMA burst transfer control, since a large amount of data is sent collectively, the instructions in the normal program can be executed only after the end of the burst transfer. Above all, a cycle of external access to the address space designated with priority can be executed, and the first effect that real-time processing can be performed on an urgent event in a normal program can be obtained.

According to the present invention, the second effect that the traffic on the transmission line controlled by the microcomputer can be improved can be obtained. The reason is that the continuity of ON of the area bit in the instruction cache can be determined, and the DMA cycle and the valid external access cycle can be transferred continuously.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a configuration diagram of an instruction cache in the embodiment shown in FIG. 1;

FIG. 3 is a timing chart showing a basic operation of the embodiment shown in FIG. 1;

FIG. 4 is a timing chart showing a competing operation of the embodiment shown in FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Central processing unit 2 Instruction cache 3 Area bit search unit 4 DMA control unit 5 External bus arbitration unit 6 Internal register 7 Internal register 8 Address space comparison unit 9 Instruction address unit 10 Tag comparison unit

Claims (4)

[Claims] 1. A reduced instruction set computer (RIS)
In the tag portion for storing the execution address in the instruction cache in C), an area bit indicating that an external access instruction corresponding to the specified range exists is provided. When the area bit is ON, the DMA burst transfer is performed. A DMA burst transfer control device characterized in that a valid external access cycle is interrupted even if it is present. 2. D in a reduced instruction set computer
In the MA burst transfer control device, an internal register for setting an address space range of an external access to be given priority processing for a DMA burst transfer and an operand in instruction data stored in an instruction cache are in the address space range. An address space comparison unit for detecting whether an instruction is executed by the computer, an area bit provided in a tag unit of an instruction cache, which is set to ON when a hit occurs according to the result of the comparison, An area bit search unit that searches for the area bit and detects the ON setting; a DMA control unit that asserts a burst transfer enable signal during DMA transfer; and a burst transfer enable signal that is asserted. The area bit search section When the constant of the detection is notified, interrupted DMA transfer, DMA burst transfer control device characterized by having an external bus arbitration unit that performs control for interrupting the cycle of the external access. 3. The area bit search unit has a function of searching for required external accesses to be continued. When continuous external accesses conflict with DMA burst transfer, the external bus arbitration unit is controlled by the external bit arbitration unit. 3. The DMA burst transfer control device according to claim 2, wherein the external access and the DMA burst transfer are controlled to operate alternately. 4. The method according to claim 2, wherein the ON control of the area bit is determined at the time of booting the microcomputer or at the time of fetching an instruction from an external storage device when a cache miss occurs. DMA burst transfer controller.