JP2001084149A - Interruption processing system for information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interruption processing system for preventing the generation of any problem in a simple method at the time of accepting interruption just after delay in a pipe line system CPU for processing an instruction having a delay slot. SOLUTION: This interruption processing system, is provided with an instruction decoder 1 for decoding an instruction in a CPU for pipe line-processing a delay instruction having a delay slot and a flag register 2 which can be set according to the instruction. Thus, interruption just after the delay instruction is switched to validity or invalidity according to the state of the flag register 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interrupt processing method in a pipeline type information processing apparatus for processing an instruction having a delay slot.

[0002]

2. Description of the Related Art Information processing devices such as computers (hereinafter referred to as CPs)
U), single-step execution of instructions is performed for debugging.

In order to realize single-step execution, C
It is common for the PU to support single-step interrupts in hardware. This is realized by preparing an operation mode in which the CPU performs single step execution, and in this mode, an interrupt is generated each time one instruction is executed.

However, there are cases where interrupts cannot be made for each instruction, such as when a pipeline is provided with a delay slot such as a delayed branch instruction. In this case, two solutions are considered.

The first method is a means for providing hardware support so that even if an interrupt is inserted between a delay instruction and a delay slot, no inconsistency occurs and a complete return can be made. That is, it is possible to execute from the instruction in the delay slot when returning. This method has no restrictions on the instructions to be programmed, and for single-step debugging,
Although ideal, an increase in hardware cost for realizing this function is inevitable, and in some cases, a decrease in operating frequency, an increase in power consumption during operation, and the like may be considered.

[0006] The second method is a method in which an interrupt is not accepted immediately after a delay instruction. With this method, the hardware cost is small, and only the delayed instruction is not single-stepped. However, if the frequency of the delayed instruction is not high, it hardly hinders debugging.

[0007]

However, in the above-mentioned first method, hardware cost becomes a problem as described above. It is difficult to adopt such a system in which cost is of the utmost importance, and there may be disadvantages such as a decrease in operating frequency and an increase in power consumption.

In the second method, when the frequency of occurrence of the delayed instruction is high, there is a problem in the debugging operation. For example,
If several delayed instructions continue, interrupts are prohibited while processing the instruction group, and single-step execution cannot be performed. Therefore, the ease of debugging during that time is significantly reduced.

Although the above-mentioned second method is promising in terms of hardware cost, the problem is that
When delay instructions appear successively, in a single-step execution mode that should be one instruction at a time, information during the execution of several instructions is interrupted and debugging is hindered.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and has been made in consideration of the above-described conventional problem. In a pipeline type CPU that processes an instruction having a delay slot, when an interrupt is received immediately after a delay, a simple method is used. Provide an interrupt handling method that eliminates problems.

[0011]

According to the present invention, there is provided an information processing apparatus for pipeline processing a delay instruction having a delay slot, comprising at least one flag register which can be set by the instruction. The interrupt immediately after the delay instruction is switched between enabled and disabled depending on the state.

[0012] According to the above-described configuration, the right of interruption can be enabled or disabled immediately after the delay instruction by the instruction, thereby giving the programmer the right of selection. Since the programmer can select either method at his convenience, it is always possible to prepare favorable conditions for the programmer.

Further, according to the present invention, a first delay instruction for disabling a subsequent interrupt regardless of the state of the flag register, and enabling / disabling of a subsequent interrupt can be switched by a flag stored in the flag register. And a second delay instruction.

According to the above arrangement, the delay instruction capable of switching the validity / invalidity of the immediately following interrupt by the flag,
Regardless of the state of the above-mentioned flag, it is classified into two types of delay instructions, that is, delay instructions that invalidate the immediately following interrupt. That is,
A delayed instruction that places a significant burden on the hardware to realize an interrupt immediately after a delay, such as an instruction that requires special processing, such as providing a special register because the branch destination address and return address are different, such as a delayed branch instruction Is a category in which the acceptance of an interrupt immediately after is prohibited regardless of the flag state, and a delay instruction that does not require hardware cost can be switched between valid / invalid of the immediately following interrupt depending on the state of the flag. As a result, single-step execution can be performed even for a part of the instruction that could not be single-step-executed in the past without increasing the hardware, and the ease of debugging can be improved.

Further, in the information processing apparatus for pipeline processing a delay instruction having a delay slot, the interrupt processing method according to the present invention includes a first delay instruction for unconditionally invalidating an immediately following interrupt, a delay instruction, And a second delay instruction capable of switching the validity or invalidity of the interrupt immediately after by a combination of instructions arranged in the delay slot.

According to the above configuration, it is possible to automatically determine whether or not the interrupt can be permitted, so that knowledge and effort are not required for the programmer. Further, even in a program in which a hazard may occur and a program in which a hazard does not exist, interrupts do not need to be uniformly disabled, thereby improving the accuracy of debugging.

Further, the present invention has a comparator for checking the coincidence of operands of two consecutive instructions in a pipeline stage, and is arranged in the delay instruction and the delay slot reflecting the result of the comparator. It is preferable to enable or disable the immediately following interrupt by a combination of instructions.

According to the above configuration, the possibility of occurrence of a hazard is checked at the operand level. Therefore, even in the case of a combination of a delayed instruction and a subsequent instruction that may cause a hazard, a hazard is generated due to mismatch of operands. In some cases, it is not necessary to prohibit interrupts, so that the accuracy of debugging is further improved.

[0019]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 5 is an operation timing chart of pipeline processing of a delayed instruction according to an embodiment of the present invention. Here, for simplicity of explanation, a simple pipeline structure is used.

In this CPU, "fetch" and "execution"
It has a three-stage pipeline structure of “memory access”.
“Fetch” is a step of sequentially reading instructions from a memory storing the instructions. "Execution" is a step of performing a process such as an operation in accordance with an instruction and storing the result in a desired register. The “memory access” is a process that exists only in an instruction for accessing a memory such as load or store. In the case of a load, data is read from a desired address and stored in a desired register.

FIG. 5 shows the operation of each step when the following program is executed. Here, "instruction A"
Is a load instruction of “LD (mem), R1”,
The data at the address (mem) on the memory is read and stored in the register R1. "Instruction B" is "ADD R
1, R2 ", which adds the contents of the registers R1 and R2 and stores the result in the register R2.
“Instruction C” is an addition instruction of “ADDR1, R3”, adds the contents of the registers R1 and R3, and stores the result in the register R3.

Here, the register R1 handling the "instruction B"
And the contents of the register R1 handled by the “instruction C” are different. This is because, as shown in FIG. 5, the update of the register R1 by the "instruction A" is not reflected in the "instruction B", but is reflected in the "instruction C". That is, "instruction B"
Uses the contents of the register R1 before the execution of the "instruction A", whereas the "instruction C" uses the contents read out by the "instruction A", that is, the contents stored at the address (mem) in the memory. Will be.

This is an architectural feature of the CPU, and the programmer understands the fact before programming.

FIG. 6 shows a case where this is debugged by single step execution. In single step execution,
Since each instruction is executed independently, several extraneous cycles exist between "instruction A" and "instruction B" as shown in FIG. Then, when the "instruction B" is executed, the contents of the register R1 are updated by the "instruction A". Therefore, the operation is performed on the contents different from the original execution time, and there is no meaning in debugging.

Therefore, when such a problem (generally called a hazard) may occur, single-step execution cannot be performed. In the case of this example, since “instruction A” corresponds to a delayed instruction, an interrupt such as a single step must not be accepted between “instruction A” and “instruction B”.

If it can be accepted, it is necessary to take measures such as holding and restoring the contents of the register during instruction processing by processing using special hardware so that the above problem does not occur. These have already been established as conventional techniques.

However, if an interrupt is accepted immediately after a delay instruction, a problem (hazard) does not necessarily occur. In the example of FIG. 5, if “instruction B” is an instruction that does not use the register R1, “instruction A” and “instruction B” are not related, and “instruction A” and “instruction B” are not related. Hazard does not occur even if an interrupt occurs. Interrupted,
Whether or not a hazard occurs is determined by the operand (generally a register in many cases) specified by the instruction, and can be grasped at the stage of programming by the programmer.

The present invention has been made in consideration of the above points. In the present invention, when an interrupt is accepted immediately after a delay instruction, two types of development are prepared according to a problem that can occur.

The first of the above two cases is a case where an interruption is accepted immediately after the delay instruction, which causes an obstacle in the control of the CPU. This is a case where the delay instruction is an instruction such as a branch instruction, and it is impossible to interrupt immediately before the delay slot (immediately after the delay instruction) without special hardware. Control is performed so as not to accept an interrupt immediately after the delay instruction corresponding to this case.

The second of the above two cases is a case where the control of the CPU is not affected. That is, this means an instruction that may cause a data hazard. If this type of delayed instruction causes a data hazard,
This is a hazard that is caused not by the instruction itself but by designating the operand in which the data is stored by the preceding and following instructions. Therefore, in the present invention, it is noted that, in the second case, it is not necessary to uniformly inhibit the acceptance of the immediately succeeding interrupt as a delayed instruction. If it is secured, a mode is set to enable interrupts to be accepted. With this, if even the operands of the delayed instruction are carefully arranged, the debugging operation can be performed without causing a problematic hazard even when the single step is performed.

Next, specific processing of the present invention will be described with reference to the drawings. FIG. 1 is a schematic diagram of a block to which the interrupt processing method of the present invention is applied. In the figure,
1 is an instruction decoder (DEC) for decoding an instruction,
2 is a flag register (FLA) operable by an instruction.
G). When the delay instruction is issued from the instruction decoder 1, a signal (LOC) indicating that the delay instruction is detected is output to the signal line 10. The flag register 2 outputs the content of the B flag of the flag register 2 to the signal line 20. This B flag sets the B flag in the flag register 2 when a hazard occurs when an interrupt occurs, that is, when the interrupt is invalidated.

Signal lines 10 and 20 are AND gate 5
And the LOC signal and the B flag signal are supplied to the AND gate 5. This AND gate 5 responds to both signals,
An output signal is output to the output signal line 30. When the LOC signal and the B flag signal are given to the AND gate 5, an interrupt disable signal (NSS) is generated and output.

As described above, in the first processing method of the present invention, the instruction decoder 1 detects the delayed instruction and
When the OC signal is output and the B flag of the flag register 2 is in the set state, an interrupt disable signal (NSS) is generated from the AND gate 5, and the immediately following interrupt is invalidated.

When the instruction decoder 1 detects a delay instruction and outputs a LOC signal and the B flag of the flag register 2 is in a reset state, the AND gate 5 generates an interrupt disable signal (NSS). And immediately enable the interrupt immediately after.

Further, even when no delay instruction is detected by the instruction decoder 1 and the B flag of the flag register is set, no interrupt disable signal (NSS) is generated from the AND gate 5, and Enable interrupts.

When no delayed instruction is detected by the instruction decoder 1 and the B flag of the flag register 2 is in a reset state, the AND gate 5 does not generate an interrupt disable signal (30NSS), and Is valid.

As described above, in the first processing method of the present invention, the programmer can select the validity / invalidity of the interrupt immediately after the delay instruction by operating the contents of the B flag of the flag register 2.

FIG. 2 is a schematic diagram of a block to which the second interrupt processing method of the present invention is applied. The same components as those in FIG. 1 are denoted by the same reference numerals.

When the instruction decoder 1 detects a delay instruction of the first type, a signal (LOCA) indicating that the delay instruction of the first type is detected is output to the signal line 11. When the instruction decoder 1 detects the second type of delayed instruction, a signal (LOCB) indicating that the second type of delayed instruction is detected is output to the signal line 12.

The flag register (FLAG) 2 outputs the contents of the B flag of the flag register 2 to the signal line 20. The B flag is set in the flag register 2 when a hazard occurs when an interrupt occurs.

The signal lines 12 and 20 are connected to the logic gate 6, and the LOCB signal and the B flag signal are given to the AND gate 6. From the AND gate 6, an intermediate signal corresponding to both signals is generated.

When the LOCB signal and the B flag are given, the AND gate 6 outputs an intermediate signal for invalidating the interrupt immediately thereafter. This signal is supplied from the signal line 13 to the OR gate 7.

The OR gate 7 generates an interrupt disable signal (NSS) based on the intermediate signal from the AND gate 6 or the LOCA signal that has detected the first type of delay instruction given from the instruction decoder 1, and outputs it. Output to the signal line 30.

Here, the first type of delayed instruction detected by the instruction decoder 1 is irrespective of the state of the B flag.
This instruction disables the immediately following interrupt. The second type of delay instruction detected by the instruction decoder 1 is an instruction for selecting whether the next interrupt is valid or invalid according to the state of the B flag.

In the second processing method according to the present invention, the instruction decoder 1 detects the first type of delayed instruction,
When the CA signal is output, the OR gate 7 generates an interrupt disable signal (NSS) regardless of the state of the B flag in the flag register 2, and invalidates the immediately following interrupt.

In the case where the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is detected by the instruction decoder 1, LOCB is given to the signal line 12, and the flag register When the B flag of No. 2 is in the set state, an interrupt prohibition signal (NSS) is generated from the OR gate 7, and the immediately following interrupt is invalidated.

Further, when the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is detected by the instruction decoder 1, LOCB is supplied to the signal line 12, and the flag register 2 B
When the flag is in the reset state, the interrupt disabling signal (NSS) is not generated from the OR gate 7, and the immediately following interrupt is made valid.

In the case where the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is not detected by the instruction decoder 1 and the B flag of the flag register 2 is set to the set state. In some cases, the interrupt prohibition signal (NSS) is not generated from the OR gate 7, and the immediately following interrupt is valid.

When the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is not detected by the instruction decoder 1, and the B flag of the flag register 2 is reset. In some cases, the interrupt prohibition signal (NSS) is not generated from the OR gate 7, and the immediately following interrupt is valid.

In the above-described first processing method, it is necessary to provide both means for enabling the interrupt immediately after the delayed instruction and for disabling the interrupt immediately after the delay instruction. It is difficult to adopt the system in which cost is of the utmost importance, and there may be negative aspects such as a decrease in operating frequency and an increase in power consumption. However, in the second processing method, the first type of delay instruction that disables the immediately following interrupt regardless of the state of the B flag and the second type that can switch the enable / disable of the immediately following interrupt by the B flag are used. Are prepared. Then, special processing such as providing a special register such as a delayed instruction which imposes a significant burden on hardware for realizing an interrupt immediately after the delay, for example, providing a special register because a branch destination address and a return address are different like a delayed branch instruction. Such instructions are classified as prohibiting the acceptance of the immediately following interrupt regardless of the flag state, and the delayed instructions that do not require hardware cost are classified as being capable of switching between valid and invalid interrupts depending on the state of the flag. With this configuration, without increasing the hardware,
Even a part of the instruction which cannot be executed in the single step can be executed in the single step, and the ease of debugging can be improved.

FIG. 3 is a schematic diagram of a block to which the third interrupt processing method of the present invention is applied. In the figure, 1
Is an instruction decoder (DEC) for decoding instructions, and 3
Is a predecoder (PDEC). The predecoder (PDEC) 3 handles an instruction immediately after being handled by the instruction decoder 1. That is, the instruction sent to the instruction decoder 1 is handled in the next stage.

The instruction decoder 1 outputs the LOCA signal to the signal line 11 when detecting the first type of delay instruction, and outputs the LOCB signal to the signal line 12 when detecting the second type of delay instruction.

The predecoder 3 outputs an INST signal to the signal line 21 on the result of detecting an instruction which may cause a hazard if executed immediately after the second type of delayed instruction.

The signal lines 12 and 21 are connected to the AND gate 6.
1 and the AND gate 61 outputs the LOCB signal, IN
An ST signal is applied, and an AND signal is generated by an AND gate 61. This intermediate signal is supplied from the signal line 14 to the OR gate 7. The OR gate 7 is supplied with the LOCA signal from the instruction decoder 1.

The above-mentioned intermediate signal generates an interrupt prohibition signal (NSS) by the OR gate 7 and the OR gate 7 and outputs it to the output signal line 30. LOCB signal, I
The combination of the NST signal and the AND gate 61 is required only for the type of the second instruction, so that the number may be plural. In the example of FIG. 3, two examples are shown.

Here, the first type of delayed instruction detected by the instruction decoder 1 is an instruction for invalidating the immediately following interrupt regardless of the succeeding instruction, and the second type of delayed instruction detected by the instruction decoder 1 is The delay instruction is an instruction for switching the next interrupt between valid and invalid according to the type of the subsequent instruction.

In the third processing method, the instruction decoder 1
When the first type of delayed instruction is detected, the OR gate 7 generates an interrupt disable signal (NSS) regardless of the type of the subsequent instruction, and invalidates the immediately following interrupt.

In the case where the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is detected by the instruction decoder 1 and immediately after the instruction detected by the instruction decoder 1. When there is an interrupt, when a pre-decoder 3 detects a subsequent instruction that may become a hazard, the OR gate 7 generates an interrupt disable signal (NSS), and invalidates the immediately following interrupt.

Further, when the first type of delayed instruction is not detected by the instruction decoder 1 and the second type of delayed instruction is not detected by the instruction decoder 1, the OR gate 7 generates an interrupt disable signal (NSS). It is not generated and the immediately following interrupt is valid.

In the case where the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is detected by the instruction decoder 1 and immediately after the instruction detected by the instruction decoder 1. When there is an interrupt, if a pre-decoder 3 does not detect a subsequent instruction that may cause a hazard, the OR gate 7 does not generate an interrupt disable signal (NSS), and the immediately following interrupt is valid.

With the above-described configuration, it is possible to automatically determine whether or not to permit an interrupt, so that the programmer does not require knowledge and trouble. Further, even in a program in which a hazard may occur and a program in which a hazard does not exist, interrupts do not need to be uniformly disabled, thereby improving the accuracy of debugging.

FIG. 4 is a schematic diagram of a block to which the fourth interrupt processing method of the present invention is applied. In the figure, 1
Is an instruction decoder (DEC) for decoding instructions, and 3
Is a predecoder (PDEC). The predecoder (PDEC) 3 handles an instruction immediately after being handled by the instruction decoder 1. That is, the instruction sent to the instruction decoder 1 is handled in the next stage.

The instruction decoder 1 outputs the LOCA signal to the signal line 11 when detecting the first type of delay instruction, and outputs the LOCB signal to the signal line 12 when detecting the second type of delay instruction.

Further, when the instruction decoder 1 detects operand information which may cause a hazard specified in the delayed instruction of the second type, it outputs an O signal to the signal line 22.
Outputs a PA signal. The predecoder 3 outputs an OPB signal to the signal line 23 upon detecting operand information which may cause a hazard specified in the detected subsequent instruction. The OPA signal and the OPB signal are provided to the comparator 8. If the OPA signal and the OPB signal match, it is known that a hazard is generated by an interrupt immediately after the delay instruction, as in the example shown in FIG. Therefore, the comparator 8 checks whether the OPA signal and the OPB signal match, and outputs the result as an intermediate signal to the signal line 14 to give the AND gate 62. The AND gate 62 is supplied with the LOCB signal from the instruction decoder 1.

An AND signal is generated by the AND gate 62 by ANDing the LOCB signal and the intermediate signal, and supplied to the OR gate 7 from the signal line 15. This intermediate signal is ORed by the LOCA from the instruction decoder 1 and the OR gate 7 to generate an interrupt disable signal (NSS) and output it to the signal line 30.

According to the fourth processing method of the present invention, when the instruction decoder 1 detects the first type of delayed instruction, an interrupt disable signal (NSS) is generated irrespective of the operand of the subsequent instruction, and the immediately following interrupt is generated. Is invalidated.

When the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is detected by the instruction decoder 1, and the operand of the delayed instruction detected by the instruction decoder 1 is detected. (OPA)
When the operand (OPB) of the subsequent instruction detected by the predecoder 3 matches, an interrupt disable signal (NSS) is generated, and the immediately following interrupt is invalidated.

Further, when the first type of delayed instruction is not detected by the instruction decoder 1, and when the second type of delayed instruction is not detected by the instruction decoder 1, the interrupt disable signal (NSS) is not generated, and Enable interrupts.

In the case where the first type of delayed instruction is not detected by the instruction decoder 1, the second type of delayed instruction is detected by the instruction decoder 1, and the operand of the delayed instruction detected by the instruction decoder 1 is detected. (OPA)
When the operand (OPB) of the subsequent instruction detected by the predecoder 3 does not match, the interrupt disable signal (NSS) is not generated, and the immediately following interrupt is made valid.

According to the above-described method, the possibility of occurrence of a hazard is checked at the operand level. Therefore, even in the case of a combination of a delayed instruction and a subsequent instruction that may cause a hazard, the occurrence of the hazard due to mismatch of operands is possible. In some cases, it may not be necessary to disable interrupts, which improves debugging accuracy.

[0071]

As described above, according to the first aspect of the present invention, it is possible for the programmer to select whether to enable or disable the interrupt immediately after the delay instruction by the instruction. Rights can be given. Since the programmer can select either method at his convenience, it is always possible to prepare favorable conditions for the programmer.

According to the second aspect of the present invention, a delayed instruction that imposes a significant burden on hardware for realizing an interrupt immediately after a delay is classified into a category in which acceptance of an interrupt immediately after is prohibited regardless of a flag state. Delayed instructions that do not require hardware cost are classified according to the state of the flag so that the next interrupt can be enabled or disabled immediately. In some cases, single-step execution can be performed, and the ease of debugging can be improved.

According to the third aspect of the present invention, it is possible to automatically determine whether or not to permit an interrupt, so that the programmer does not require knowledge and trouble. Further, even in a program in which a hazard may occur and a program in which a hazard does not exist, interrupts do not need to be uniformly disabled, thereby improving the accuracy of debugging.

According to the fourth aspect of the present invention, in addition to the effect of the third aspect, the possibility of occurrence of a hazard is checked at the operand level. Even in the case of a combination, a hazard does not occur due to mismatch of operands, and there is a case where it is not necessary to prohibit an interrupt, so that debugging accuracy is further improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of a block to which a first interrupt processing method according to the present invention is applied;

FIG. 2 is a schematic diagram of a block to which a second interrupt processing method according to the present invention is applied;

FIG. 3 is a schematic diagram of a block to which a third interrupt processing method according to the present invention is applied;

FIG. 4 is a schematic diagram of a block to which a fourth interrupt processing method according to the present invention is applied;

FIG. 5 is an operation timing chart of pipeline processing of a delayed instruction according to the embodiment of the present invention;

FIG. 6 is an operation timing diagram when debugging is performed by single-step execution.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Instruction decoder 2 Flag register 3 Predecoder 5 AND gate 7 OR gate 8 Comparator 61 AND gate 62 AND gate

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Takao Katayama 1-3-6 Nakamagome, Ota-ku, Tokyo Inside Ricoh Company (72) Inventor Kazuhiko Iwanaga 1-3-6 Nakamagome, Ota-ku, Tokyo Stock In Ricoh Company (72) Inventor Hiroshi Takato 1-3-6 Nakamagome, Ota-ku, Tokyo F-term in Ricoh Company (reference) 5B013 AA11 5B098 AA02 BB08

Claims (4)

[Claims] An information processing apparatus for performing pipeline processing of a delay instruction having a delay slot has at least one flag register that can be set by the instruction, and enables an interrupt immediately after the delay instruction depending on a state of the flag register. Alternatively, an interrupt processing method in an information processing apparatus characterized by being switched to invalid. 2. A first delay instruction for invalidating an immediately following interrupt irrespective of the state of the flag register, and a second delay instruction for enabling or disabling the immediately following interrupt by a flag stored in the flag register. 2. The interrupt processing method according to claim 1, further comprising: a delay instruction. 3. An information processing apparatus for pipeline processing a delay instruction having a delay slot, wherein a first delay instruction that unconditionally invalidates an immediately following interrupt, a delay instruction and an instruction arranged in the delay slot And a second delay instruction capable of switching the validity or invalidity of the interrupt immediately after the combination. 4. A pipeline stage comprising a comparator for checking the coincidence of operands of two consecutive instructions in a pipeline stage, and reflecting a result of the comparator, by combining the above-mentioned delay instruction and an instruction arranged in a delay slot. 4. An interrupt processing method in an information processing apparatus according to claim 3, wherein an interrupt immediately after the interrupt is enabled or disabled.