JPH05108542A - Data processor - Google Patents

Abstract

PURPOSE:To recognize a bit state easily in comparison with a conventional system due to plural instructions by providing an instruction exclusive for inspecting the state of a bit not depending on a data processed result in a control register. CONSTITUTION:This device is equipped with means to interrupt a processing under executing according to a prescribed signal, means to save the contents of a prescribed register to an external storage device in the case of this interruption and means to recover the saved contents into the source register according to a prescribed instruction. Namely, at a microcomputer equipped with the control register to be saved in the case of executing the interruption processing and to be recovered by a return instruction, the exclusive instruction is provided to inspect the state of the bit not depending on the data processed result in the control register. Thus, the state of the bit not depending on the data processed result in the control register, which is saved in the case of executing the interruption processing and recovered by the return instruction, can be inspected with one instruction, and the state of the bit can be easily recognized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing technique, and more particularly to a technique which is particularly effective when applied to an instruction format of a microcomputer, for example, a technique which is effectively used for a bit check instruction of a control register in a microcomputer. It is a thing.

[0002]

2. Description of the Related Art A central processing unit (CPU) of a microcomputer is provided with a data register or address register generally called a general purpose register, an accumulator or an index register, and a control register such as a program counter or a condition code register. The condition code register among the above-mentioned various registers is composed of a flag that reflects the result of the data processing of the CPU, such as a zero flag, a negative flag,
Includes carry flag, overflow flag, etc. Of these, for example, the carry flag is set to "1" if a carry occurs when the CPU performs addition, and is cleared to "0" if a carry does not occur.

When an external factor independent of the processing of the CPU or an operation of a built-in functional block occurs, the microcomputer temporarily suspends the processing of the CPU to cope with the operation of the external factor or the functional block. It has a so-called interrupt function to perform processing. When the CPU executes such interrupt processing, the contents of the program counter and the condition code register are saved outside the CPU, that is, in a so-called stack area. Further, when the execution of the interrupt processing is completed and a so-called return instruction is executed and the processing of the CPU returns to the state before the interrupt processing, the contents of the saved program counter and condition code register are restored.

FIG. 5 shows an example of a register configuration of a CPU in a conventional microcomputer. This CPU includes 16 general-purpose registers having 8 bits, a program counter having 16 bits, and a condition code register having 8 bits. In the condition code register, in addition to the zero flag (Z), negative flag (N), carry flag (C) and overflow flag (V), an interrupt mask bit (I) and 3 user bits (U
0, U1, U2) are included. The interrupt mask bit is set to "1" to disable the interrupt, and cleared to "0" to enable the interrupt. When the interrupt process is executed, the interrupt mask bit is set to "1". As described above, the condition code register changes due to the reflection of the result of data processing by the CPU, execution of interrupt processing, and also due to the logical operation on the condition code register itself. Further, data can be transferred between the condition code register and the general-purpose register, and can be operated by a software program.

On the other hand, 3 user bits (U0, U
1, U2) does not change depending on the reflection of the result of the data processing or the execution of the interrupt processing, but only by the software program. Further, the user bit has a characteristic that it is automatically saved when the interrupt processing is executed, and can be used for displaying the execution state of the program. For example, when configuring an operating system (OS), a user bit can be used to indicate whether an OS program is running or a user program is running. Although not particularly limited, if the OS program is running, the bit U0 of the user bits is set to "1".
And the user bit U0 is cleared to "0" if the user program is being executed. As a result, even if the execution of the OS program is interrupted by the interrupt and the user program is executed, even if the user program is executed during the interrupt process to rewrite the user bit U0 and clear it to "0", the return instruction The original state "1" of the user bit is restored by the execution, and can be used for determining whether or not the execution of the OS program can be resumed. Such CPU is “H8 / 330 HD647” issued by Hitachi, Ltd. in June 1989.
3308 HD64333308 Hardware Manual ”.

[0006]

However, the above-mentioned CP
In U, whether the user bit is "1" or "0" is determined by temporarily transferring the entire condition code register to a general-purpose register and determining the transferred user bit by a so-called bit test instruction. However, if the program to be processed is changed based on the determination result, the branch instruction must be further used. A program example for such processing is shown below. STC CCR, R0L BTST # 4, R0L BEQ L1 (OS program) L1: (User program)

The above program uses three instructions and is complicated as compared with the processing contents to be executed, and its execution efficiency is very poor. In addition, there is a problem that the content is difficult to understand. It is an object of the present invention to provide a data processing technique capable of easily inspecting the state of a bit that is saved during execution of interrupt processing and that is restored by a return instruction and that does not depend on the data processing result. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0008]

The typical ones of the inventions disclosed in the present application will be outlined below. That is, it is saved when interrupt processing is executed,
In a microcomputer provided with a control register which is restored by a return instruction, a dedicated instruction for inspecting the state of a bit that does not depend on the data processing result in the control register is provided.

[0009]

According to the above-mentioned means, the state of the bit saved in the execution of the interrupt processing and recovered by the return instruction and not depending on the data processing result in the control register can be inspected by one instruction. The bit state can be known more easily than the conventional method of checking the state.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows a block diagram of a CPU of a microcomputer suitable for application of the present invention. That is, the CPU includes a data register or address register called a general-purpose register, an accumulator or an index register, a register group REG including control registers such as a program counter and a condition code register, and an arithmetic logic unit ALU for performing addition / subtraction and logical operation. An instruction register IR for fetching an instruction read from an external program memory via the data bus DB; a control unit CONT for decoding the fetched instruction to form a control signal for the arithmetic logic unit ALU or the like; It is composed of external data bus DB and address bus AB and data input / output buffers DIBF and DOBF and address buffer ABF provided between internal buses IDB1 and IDB2.

The register structure in the register group REG and the bit structure of the condition code register therein are the same as those shown in FIG. Further, the CPU of this embodiment has a function of decoding and executing a dedicated instruction (hereinafter referred to as a user bit check instruction) for checking the states of the user bits U0, U1, U2 in the condition code register. .. Although not particularly limited, the data bus is composed of 16 bits,
16-bit data can be read / written in two states and so-called instruction prefetch control is performed.

FIG. 1 shows an example of a flow chart of the user bit check instruction. Although not particularly limited, this instruction is expressed as TSTUn n = 0, 1, 2. For example, the TSTU0 instruction is user bit U
When 0 is checked and the U0 bit is 0, the zero flag is set to 1, and when the U0 bit is 1, the zero flag is cleared to 0. This instruction does not affect the contents other than the zero flag of the condition code register, and
It does not affect the contents of general registers. The instruction length is 2 bytes.

When this TSTUn instruction is executed, the first
In step S11, the data (next instruction) on the data bus DB is loaded into the CPU. At the same time, the contents of the program counter PC are transferred to the address buffer ABF and the arithmetic logic unit ALU via the first internal bus IDB1. Program counter PC for arithmetic logic unit ALU
"2" is added to the contents of, and the addition result is stored in the program counter PC via the second internal bus IDB2.
In the second step S12, the reading of the instruction is started based on the contents of the program counter PC stored in the address buffer ABF. At the same time, the decoding of the next instruction stored in the first step S11 is started. Further, the contents of the condition code register are transferred via the first internal bus IDB1 to the address buffer ABF and the arithmetic logic unit ALU.
Transfer to.

Although not particularly limited, the TSTU0 instruction inspects the value 4 (user bit U0) of the condition code register and the TSTU1 instruction inspects bit 5 (user bit U) of the condition code register.
1) Check the value, and in TSTU2, the instruction checks the bit 6 (user bit U2) value of the condition code register. Specifically, in the TSTU0 instruction, the data H'10 (= B'0001000) is stored inside the arithmetic logic unit.
0; H'represents a hexadecimal number and B'represents a binary number), and is ANDed with the data input from the first internal bus to determine whether the result is H'00. Just make a decision. The value of the zero flag in the condition code register is changed according to the result of this judgment.
The zero flag may be checked to determine whether to branch. Note that the TSTU1 instruction generates data H'20 inside the arithmetic logic unit, and the TSTU2 instruction generates data H'40 inside the arithmetic logic unit.

FIG. 2 shows an example of a flowchart of another instruction for checking the state of the user bit of the condition code register. Although not particularly limited, this instruction is expressed as LDUn n = 0, 1, 2. For example, the LDU0 instruction is user bit U0
The content of is reflected in the carry flag. It does not affect the contents other than the carry flag of the condition code register, nor does it affect the contents of the general-purpose register.

When this LDUn instruction is executed, the data (next instruction) on the data bus is transferred to C in the first step S21.
Take in the PU. At the same time, the contents of the program counter PC are transferred to the address buffer ABF and the arithmetic logic unit ALU via the first internal bus IDB1. The arithmetic logic unit ALU adds "2" to the second internal bus I
The addition result is stored in the program counter PC via DB2. In the second step S22, reading of an instruction is started based on the contents of the program counter PC stored in the address buffer ABF. At the same time, the contents of the condition code register are transferred to the address buffer ABF and the arithmetic and logic unit ALU via the first internal bus IDB1. In the arithmetic logic unit ALU, L
The DU0 instruction, LDU1 instruction, and LDU2 instruction respectively cause bits 4, 5 of the condition code register,
Check the value of 6. The value of the carry flag is changed according to this determination result. However, data inverted from the zero flag is stored in the carry flag.

FIG. 3 shows a flowchart of an instruction for checking the state of the user bit of the condition code and branching according to the result. Although not particularly limited, this instruction is expressed as BUCn relative value BUSn relative value n = 0, 1, 2. For example, if the result of checking the state of the U0 bit is "0", the BUC0 100 instruction branches to the address where the relative address 100 is added to the address where the next address instruction of this instruction exists, and the U0 bit is "1". If it is ", the instruction at the next address is executed. If the U0 bit is "1", the BUS0-10 instruction branches to an address obtained by subtracting the relative value 10 from the address where this instruction exists, and if the U0 bit is "0", the instruction at the next address is executed. Is what you do.
Neither affects the other bits in the condition code register, nor does it affect the contents of the general purpose register.

The BUCn instruction has a relative value of 16 bits in the instruction code and has a length of 4 bytes. When this instruction is executed, first, in the first step S31, the data bus DB
The above data (relative value 16 bits) is loaded into the CPU. At the same time, set the contents of the condition code register to the first
Address buffer ABF via internal bus IDB1 of
To the arithmetic logic unit ALU. Arithmetic logic operation unit A
The LU inspects the value of bit 4 (U0) of the condition code register in BUC0, the bit 5 (U1) in BUC1, and the value of bit 6 (U2) in BUC2 in the same manner as described above. In the second step S32, if the output of the zero detection circuit which is the check result is "1", the contents of the program counter PC are transferred to the arithmetic logic unit ALU via the first internal bus IDB1. Then, the relative value stored in the first step is used as the second internal bus IDB2.
Is transferred to the arithmetic and logic unit ALU and added. The addition result is stored in the program counter PC via the third internal bus IDB3. On the other hand, if the output of the zero detection circuit, which is the inspection result, is "0", the contents of the program counter PC are transferred to the arithmetic logic unit ALU via the first internal bus IDB1 and the relative value is added. The result is not stored.

In the third step S33, the contents of the program counter PC are transferred to the address buffer ABF and the arithmetic logic unit ALU via the first internal bus IDB1. If the U0 bit is "1", the next address is transferred, and if the U0 bit is "0", the branch destination address is transferred. The arithmetic logic unit ALU adds "2" and stores the addition result in the program counter PC via the second internal bus IDB2. In the fourth step S34, the program counter P stored in the address buffer ABF is stored.
The instruction read is started based on the contents of C. In the fifth step S35, the data on the data bus DB is fetched into the CPU, and the contents of the program counter PC are transferred to the address buffer A via the first internal bus IDB1.
Transfer to BF and arithmetic logic unit ALU. The arithmetic logic unit ALU adds "2" and outputs the result to the second internal bus I.
Stored in the program counter PC via DB2.
In the sixth step S36, the address buffer ABF is
The instruction reading is started based on the contents of the program counter PC stored in. At the same time, the decoding of the instruction stored in the fifth step S35 is started.

FIG. 6 shows the user bit check instruction TS.
A specific configuration example of a part of the arithmetic and logic unit ALU and the condition code register suitable for executing TUn and LDUn is shown. The arithmetic logic operation unit ALU includes a bit data generation circuit BDG, an operation circuit LOC, and a zero detection circuit ZDC. The arithmetic circuit LOC has a first
The data on the second internal buses IDB1 and IDB2 and the output of the bit data generation circuit BDG are input and can be output to the third internal bus IDB3. The bit data generation circuit BDG uses H'01 (= B'00000001) to H'8 based on the three signals input from the control unit.
Data of 0 (= B'10000000) is generated. F
z is a zero flag and Fc is a carry flag.

Either the second internal bus IDB2 or the output of the bit data generating circuit BDG is input to the arithmetic circuit LOC. For example, the add instruction inputs data on the second internal bus IDB2, and the TSTUn instruction inputs the output of the bit data generation circuit BDG. The zero detection circuit ZDC receives the output of the arithmetic circuit LOC, determines whether the input value is all bits 0 by an AND logic gate, and outputs "1" if all bits are 0. Although not particularly limited, in this embodiment, the internal bus is negative logic. First and second internal buses IDB1 and IDB
2 is precharged to a high level (“0” level) by a precharge transistor composed of a P-channel MOSFET while the system clock φ is at a high level.

Next, in the circuit of FIG.
When the 0 instruction is executed, in the second step, the control signal CR1 is set to "1" level, and the content of the condition code register is output to the first internal bus IDB1. The control signal A1 is set to "1" level, and the output of the bit data generation circuit DBG is input to the arithmetic circuit LOC. Bit data generation circuit BD according to control signals B0 to 2
Instruct G to generate H'10. The logical product calculation is instructed by the control signals C0 to C2. The control signal CZ0 is set to "1" level, and the output of the zero detection circuit ZDC is input to the zero flag Fz. By the above operation, the contents of bit 4 of the condition code register can be reflected in the zero flag Fz.

Similarly, when the LDU0 instruction is executed,
In the second step, the control signal CR1 is set to "1" level, and the content of the condition code register is output to the first internal bus IDB1. The control signal A1 is set to "1" level, and the output of the bit data generation circuit BDG is input to the arithmetic circuit LOC. Bit data generation circuit BD according to control signals B0 to 2
Instruct G to generate H'10. The logical product calculation is instructed by the control signals C0 to C2. The control signal CC1 is set to "1" level, and the inverted signal of the output of the zero detection circuit ZDC is input to the carry flag Fc. By the above operation, the contents of bit 4 of the condition code register can be reflected in the carry flag Fc.

FIG. 7 shows the BUCn instruction and BUSn.
A concrete configuration example of a program counter PC and an arithmetic logic unit ALU suitable for executing instructions is shown. The program counter PC can be input from the third internal bus IDB3. When data is input from the third internal bus IDB3 other than the second step of the BUCn and BUSn instructions, the control signal PW0 is set to "1" level. At the second step of the BUCn and BUSn instructions, the control signal PW1 is set to "1" level, and the data of the third internal bus IDB3 is transferred based on the contents of the output of the zero detection circuit delayed by one step by a so-called shift register. Select whether to input or not. BUSn at the same time
In the command, the control signal ZN is set to "1" level, and the result of zero detection is inverted.

FIG. 8 shows the user bit check instruction TST.
Arithmetic and logic unit A suitable for executing Un and LDUn
Another specific configuration example of the LU and the condition code register is shown. The output of the bit data generation circuit BDG and the contents of bits 4 to 6 of the condition code register are input to the inspection circuit DTC composed of an AND logic gate Ga and a NOR logic gate Gn. If the contents of bits 4 to 6 of the condition code register corresponding to the bit for which the output of the bit data generation circuit BDG has become "1" are "1", the output of the AND logic gate Ga for that bit becomes "1". , The output of the NOR logic gate Gn becomes "0" level. Others are the same as the circuit of FIG. 6, and the inspection result is reflected in the zero flag Fz.

In the circuit of FIG. 8, when the TSTU0 instruction is executed, in the second step, the bit data generating circuit BD is generated by the control signals B0-2.
Instruct G to generate H'10. The control signal CZ0 is set to "1" level, and the output of the inspection circuit DTC is input to the zero flag Fz. By the above operation, the contents of bit 4 of the condition code register can be reflected in the zero flag Fz.

Similarly, in the circuit of FIG. 8, the output of the NOR logic gate Gn may be inverted and put in the carry flag instead of the zero flag Fz. In such a circuit, when the LDU0 instruction is executed, in the second step, the bit data generating circuit BD is generated by the control signals B0 to B2.
Instruct G to generate H'10. The control signal CC1 is set to "1" level and the inspection circuit DT
The inversion of the output of C is input to the carry flag Fc. By the above operation, the contents of bit 4 of the condition code register can be reflected in the carry flag Fc.

According to the above-described embodiment, the state of the bit saved during the execution of the interrupt process, restored by the return instruction, and independent of the data processing result can be easily inspected by one instruction. Compared with the conventional method of checking the state, there is an effect that the software program can be simplified to improve the execution efficiency and the contents can be directly expressed. The invention made by the present inventor is not limited to the embodiments, and various modifications can be made without departing from the spirit of the invention. For example, the number of registers and the number of bits of the CPU, the internal configuration of the CPU, and the like are not limited at all. The method of checking the condition code register is not limited to the embodiment. The number of user bits can be changed. Also, the condition code register may include a half carry flag or the like. It is also possible to combine the embodiments with each other. Further, the user bit may be configured so as not to be affected by the reset signal. In the above description, the case where the invention mainly made by the present inventors is applied to a microcomputer, which is a field of application which is the background of the invention, has been described.
The present invention is not limited to this, and can be applied to other data processing devices. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a data processing device including a register that is saved / restored at the time of executing / returning an interrupt process.

[0029]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, it becomes possible to easily know the state of the bit that does not depend on the data processing result in the control register in the microcomputer provided with the control register that is saved when the interrupt processing is executed and restored by the return instruction.

[Brief description of drawings]

FIG. 1 is a flowchart showing an example of an instruction for checking the state of a user bit of a condition code according to the present invention.

FIG. 2 is a flowchart showing another example of an instruction for checking the state of user bits of a condition code.

FIG. 3 is a flowchart showing an example of an instruction for checking the state of a user bit of a condition code and branching according to the result.

FIG. 4 is a block diagram showing an example of a CPU of a microcomputer to which the present invention is preferably applied.

FIG. 5 is an explanatory diagram showing a register configuration example of a CPU.

FIG. 6 is a circuit configuration diagram showing a specific example of a part of an arithmetic logic unit and a condition code register.

FIG. 7 is a circuit configuration diagram showing a specific example of a part of a program counter.

FIG. 8 is a circuit configuration diagram showing another specific example of a part of the arithmetic logic unit and the condition code register.

[Explanation of symbols]

 CCR condition code register PC program counter LOC operation circuit BDG bit data generation circuit ZDC zero detection circuit Fz zero flag Fc carry flag

Claims (3)

[Claims] 1. A means for interrupting a process being executed by a predetermined signal from the outside of the apparatus, a means for saving the contents of a predetermined register to an external storage device at the time of the interruption, and the above-mentioned save by a predetermined instruction. Means for restoring the contents to the original register, the register includes a bit readable and writable by an instruction, and the state of the bit can be inspected by a predetermined instruction. Processing equipment. 2. The state of the bit readable and writable by an instruction is inspected by a predetermined instruction, and the instruction to be executed next is changed based on the result. The described data processing device. 3. The method according to claim 1, wherein a result of checking a state of the bit that can be read and written by an instruction is reflected in a predetermined bit in the register. The described data processing device.