JPH06202907A - Debug support device - Google Patents

Abstract

PURPOSE:To provide a debug support method which can perform a debugging job in real time without giving any special limitation to the program to be debugged. CONSTITUTION:A debug support device 1 consists of a microprocessor 3, an address comparator 7, a comparison data latch 6, an address pass detecting circuit 5, a debug device control circuit 9, an external address pass detecting circuit 8, a display device 15, and a state deciding circuit 16. A device 2 to be debugged includes a memory 4 which stores the program to be debugged, etc. This memory 4 is connected to a microprocessor 3 via a data bus 10 and an address bus 11 and receives an access. The microprocessor 3 consists of a holding control circuit which stops the operation when the instructions of an instruction word latch, an execution pipeline, and an object address are fetched by the execution pipeline.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug support technique, and more particularly to a technique effectively applied to debug of an application device using a microprocessor having an instruction pipeline type architecture.

[0002]

2. Description of the Related Art In recent years, devices to which microprocessors are applied have become widespread. When developing these applied devices, a debugging support device such as an in-circuit emulator is used to debug the program. An address break and address passage detection function are effective as one of the debug functions. That is, when the execution program reaches a specific address, it is a function of stopping the microprocessor or making it possible to recognize from outside that the specific address has been executed.

In order to realize such a function, conventionally, in the debug support device, a comparison circuit for comparing with a target address is connected to the address bus of the microprocessor and the output result and the instruction word of the microprocessor are connected. A method of stopping the microprocessor or detecting an address passage depending on the fetch operation state has been widely adopted.

Regarding the debugging technique in the system development of a microcomputer, for example, Ohmsha Co., Ltd., published on Dec. 20, 1988, Kenzo Kani, "Microcomputer Basic Course, Volume 3," Software and Programming "" P202-P203. , And the like.

[0005]

When debugging a program, it is often difficult to detect a defective portion of the program and find the cause thereof. At this time, it can be efficiently performed by using a development support device such as an in-circuit emulator. One of the debug functions of this development support device is the address break and address passage detection functions described above. When this function is implemented by a pipelined microprocessor, conventional non-pipelined microprocessors could be easily implemented only by monitoring the address bus, but pipelined microprocessors generated branch instructions. In this case, the determination as to whether the actually fetched instruction has been executed cannot be recognized only by externally monitoring the address bus.

Therefore, for example, a break-dedicated instruction is added to a part of the original instruction sequence for debugging.
This is achieved by adding constraints to the program,
There is a problem in that not only debugging work becomes complicated due to re-creating the program, but it also becomes difficult to check the program in its original state in real time.

An object of the present invention is to provide a debug support technique capable of realizing real-time debugging without adding special restrictions to a program to be debugged.

Another object of the present invention is to provide a microprocessor capable of realizing debugging in real time without adding special restrictions to a program to be debugged.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

That is, the debug support apparatus of the present invention is
A first means for monitoring the address bus of the microprocessor to determine whether the address value is a target address value; a second means for determining whether the execution cycle in the microprocessor is an instruction word fetch cycle; Third means for issuing a first logic signal for instructing a debug operation to the microprocessor based on the determination result by the second means, and debug provided by the first logic signal provided inside the microprocessor. When an operation is designated, a fourth means for issuing a second logic signal indicating that the instruction word of the address value has entered the execution cycle to the outside and an address break operation provided inside the microprocessor are provided. And a fifth means for stopping the execution operation of the microprocessor based on the second logic signal when set. .

[0012]

According to the debug support apparatus of the present invention described above,
The third means recognizes that the address output to the address bus in the first means is the target address to be debugged, and in the second means, the execution cycle in the microprocessor is the instruction word fetch cycle. Then, the first logic signal input to the microprocessor is set to be true.

A fourth means provided in the microprocessor issues a second control signal to the outside when the address to be debugged enters an execution cycle while the first logic signal is in the true state. With this second control signal, it is possible to surely know that the instruction at the target address has been executed from the outside of the microprocessor, for example, without adding an instruction dedicated to debugging to the program to be debugged.

Further, if necessary, the fifth means provided in the microprocessor stops the execution operation of the microprocessor at the target address (address break) upon detection of the second control signal. Can be done.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A debug support apparatus according to an embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an example of the configuration of the debug support apparatus of this embodiment. The debug support device 1 includes a microprocessor 3, an address comparison circuit 7, a comparison data latch 6, an address passage detection circuit 5, a debug device control circuit 9, an external address passage detection circuit 8, a display device 15, and a state determination circuit 16. There is.

The device to be debugged 2 is composed of, for example, a memory 4 in which a program to be debugged is stored, and the memory 4 is connected to the microprocessor 3 via a data bus 10 and an address bus 11. Be accessed.

FIG. 2 is a block diagram showing an example of the internal configuration of the microprocessor 3 in this embodiment. The microprocessor 3 includes an instruction word latch 12, an execution pipeline 13, a hold control circuit 14 and the like.

A cycle identification signal 16a indicating whether or not the microprocessor 3 is in an instruction word fetch cycle is output from the microprocessor 3 to the state determination circuit 16.

An example of the operation of the debug support device of this embodiment will be described below.

First, when performing an address break, a target address value is set in the comparison data latch 6, and the address bus 11 of the microprocessor 3 is connected to the address comparison circuit 7.
Are monitored to determine whether they match the contents of the comparison data latch 6.

Next, when the address comparison circuit 7 determines that the addresses match, the microprocessor 3 determines by the state determination circuit 16 whether or not it is currently in the instruction word fetch cycle, and the determination result is the read cycle. If so, the address pass detection input 17 to the microprocessor 3 is set to true. After that, the microprocessor 3 inputs the address passage detection input 17 to the execution pipeline 13, and when the instruction word of the target address enters the execution cycle in the execution pipeline 13,
A hold request is output to the hold control circuit 14, and the hold control circuit 14 stops the execution operation of the microprocessor 3.

Further, in the case of detecting the address passage, the hold control circuit 14 outputs the address bus output signal 18 indicating that the execution cycle has been entered without operating the microprocessor 3, and the inside of the debug support apparatus 1 The address passage detection circuit 5 detects passage. Then, the debug device control circuit 9 displays on the display device 15 that the microprocessor 3 has stopped at the target address or that the instruction word at the target address has been executed (passed) in the microprocessor 3.

As described above, according to the debug support apparatus 1 of the present embodiment, for example, the program to be debugged stored in the memory 4 is modified by adding a special instruction word dedicated to debugging. Without this, it is possible to easily and surely perform the debug operation such as the address break and the address passage detection in the microprocessor 3 having the execution pipeline 13 in real time.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.

[0026]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

According to the debug support apparatus of the present invention, the program to be debugged is not subjected to any special restriction,
The effect is that real-time debugging can be realized.

Further, according to the microprocessor in the debug support apparatus of the present invention, when the instruction pipeline is provided, real-time debugging can be realized without adding special restrictions to the program to be debugged. The effect is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating an example of a configuration of a debug support device that is an embodiment of the present invention.

FIG. 2 is a block diagram showing an example of an internal configuration of a microprocessor in the debug support device according to the embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 debug support device 2 device to be debugged 3 microprocessor 4 memory 5 address passage detection circuit 6 comparison data latch 7 address comparison circuit (first means) 8 external address passage detection circuit (third means) 9 debug device control circuit 10 Data bus 11 Address bus 12 Instruction word latch 13 Execution pipeline (fourth means) 14 Hold control circuit (fifth means) 15 Display device 16 State determination circuit (second means) 16a Cycle identification signal 17 Address passage detection Input (first logic signal) 18 Address bus output signal (second logic signal)

Claims (1)

[Claims] 1. A first means for monitoring an address bus of a microprocessor to determine whether the address value is a target address value, and a second means for determining whether an execution cycle in the microprocessor is an instruction word fetch cycle. Means and the determination results of the first and second means,
Third means for issuing a first logic signal for instructing a debug operation to the microprocessor; and a third means provided inside the microprocessor for designating the debug operation by the first logic signal. Fourth means for issuing a second logic signal indicating that the instruction word of the address value has entered an execution cycle to the outside, and, provided inside the microprocessor, when an address break operation is set, And a fifth means for stopping the execution operation of the microprocessor based on the second logic signal.