JP2002163126A - Event detecting circuit embedded in debugging cpu, event detecting method, and external peripheral circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a development support device generating no difference between a command subject to event detection and a command indicated by a present program counter PC. SOLUTION: This event detecting circuit is provided with an event command decoding means 104 comprising a command decoding means 121 decoding a command read in a command fetch stage, a command code analyzing means 131 extracting a load command and a store command from the read command and stopping the decoding of the succeeding command for a predetermined period and an address generating means 132 generating the access address of the read command and an event processing means 105 generating the address coincidence signal for interrupting a command executing means 151 to invalidate the command process stage subsequent to the execution stage of the succeeding command when the access address coincides with the predetermined event address.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an event detection circuit, an event detection method, and an external peripheral circuit incorporated in a debugging CPU of a development support apparatus. In particular, the present invention newly provides an event at the timing when the CPU decodes an instruction. Debug improved by performing event instruction decode processing so that when event detection of data access is used, there is no difference between the instruction targeted for event detection and the instruction indicated by the current PC CPU
The present invention relates to a built-in event detection circuit, an event detection method, and an external peripheral circuit.

[0002]

2. Description of the Related Art In recent years, with the progress of miniaturization of semiconductor elements, the functions of microcomputers composed of semiconductor elements have become complicated and large-scale, and have been widely used in home appliances, personal computers, OA-related equipment, industrial equipment, and the like. It's being used.

Since the target program capacity of microcomputers applied to these devices is increasing year by year, the development of microcomputer application products is becoming more complicated and the development time is increasing due to the increase in program capacity. I have.

However, in order to respond to market demands, it is necessary to deal with complicated program development in a short time, and an efficient microcomputer development support device is required.

[0005] The debug CPU mounted on the microcomputer development support device described above includes an event detection circuit. In this conventional event detection circuit, memory access detection is performed by comparing data on a data bus output to an address targeted for memory access.

[0006] One example is described in JP-A-11-167500. Referring to FIG. 13 showing the configuration of an event circuit described in the publication, the debug system includes a debugger 901, an emulator device 902, and an MCU 90.
3, an event circuit 904;
04 detects a memory access event by comparing the values of the address bus and the data bus with variables.

[0007] That is, the event circuit 904 includes the MCU
The address value (F) on the address bus output from the address bus 903 and the data value (M) on the data bus are compared by the address comparison circuit 907 and the variable value coincidence detection & holding circuit 906, and the comparison result (H) is ANDed. Circuit 908 and A
After the calculation by the ND circuit 910, the result is output to the outside of the event circuit 904 as a variable access result (J) and a variable value condition match result (N), respectively. Event detection can be performed by these signals.

On the other hand, an example in which an instruction address of an executed instruction can be easily taken into a debugging tool is described in JP-A-8-171505.

According to the semiconductor device described in the publication, the CPU
And a debugging unit, and the debugging unit is a CP
A pipeline (IF stage latch, ID stage latch, MA stage latch) for performing pipeline control on an instruction address output from U and outputting the output as an instruction address to a debug tool, and a pipe for a read signal output from the CPU. There are two sets of pipelines (IF stage latch, ID stage latch, MA stage latch) that perform line control and output the output to a debug tool as a read strobe signal.

In this device, when the CPU fetches instructions 1 to 5 in the order of instruction 1 (branch instruction) → instruction 2 → instruction 3 → instruction 4 (branch destination instruction) → instruction 5, instruction 2
Instruction 2 is executed up to two stages of ID2, the subsequent stages are not executed, instruction 3 is executed only in IF3 stage, and the subsequent stages are not executed.

As a result, the instruction address output to the debug tool is such that IF1 of instruction 1 is output at the timing of the MA1 (memory access) stage of instruction 1,
The IF4 of the instruction 4 is output at the timing of the memory access stage of the instruction 4, and the IF5 of the instruction 5 is output at the timing of the memory access stage of the instruction 5. That is, the addresses of the canceled instructions 2 and 3 are not output and are blank, and “IF1” → “−” →
The order is “−” → “IF4” → “IF5”.

The instruction address at which the instruction was executed in this manner, that is, only the instruction address used for IF1, IF4, IF5 is output to the debugging tool, and the instruction address used for these IF1, IF4, IF5 is used. Is given to the debug tool.

Therefore, there is no need to provide a debug unit having a conventional configuration for outputting all instruction addresses output from the CPU to the debugging tool.

[0014]

Here, referring to FIG. 14 showing an example of a timing chart of the pipeline processing, a CPU using the pipeline processing generally has an instruction fetch stage (IF) and an instruction decode stage (I).
D), instruction execution stage (EX), MEM stage (M
EM) and WB stage (WB). In this procedure, MEM indicates memory access, and WB indicates write-back to a register.

Considering the execution of such pipeline processing, the above-described example disclosed in Japanese Patent Laid-Open No. 11-167500 has the following problems. That is, the allocation address (G) and the comparison condition & variable value (L) to be compared are compared with the address value (F) on the address bus and the data value (M) on the data bus, respectively.

In this case, one instruction or two instructions are executed by the time until the MEM stage is completed in the instruction execution procedure of the CPU and the time difference until the data on the data bus is detected. P
C indicates an instruction prior to the instruction that actually accessed the memory.

Therefore, when the event detection of data access is used, a difference occurs between the instruction targeted for the event detection and the instruction indicated by the current program counter PC.

As a result, the program counter PC of the instruction to be accessed must be searched backward from the current program counter PC.

On the other hand, in the case of the conventional example described in Japanese Patent Application Laid-Open No. 8-171505,
(Fetch address), an address (access address) targeted by the instruction itself in the embodiment of the present invention described later.
It is. That is, when processing the instruction code, the target part is different.

Further, a debug unit having two sets of pipelines is required, so that a chip area is increased.
The problem in the memory access described above is not solved.

An object of the present invention has been made in view of the above-mentioned drawbacks of the related art. By performing an instruction decoding process newly provided for an event at a timing at which the CPU performs instruction decoding, it is possible to reduce memory access factors. An object of the present invention is to provide a means for solving the above-described problem by detecting a memory access event immediately after executing an execution stage of an instruction that has become invalid and interrupting a subsequent instruction.

[0022]

According to the present invention, there is provided an event detection circuit for decoding an instruction read in an instruction fetch stage in an event detection circuit built in a debug CPU of a development support device used for debugging a development target program. In addition to the decoding means, an instruction code analyzing means for extracting a load instruction and a store instruction from the read instruction and stopping the decoding of a subsequent instruction for a predetermined period, and an access address generating means for generating an access address of the read instruction And an address for invalidating an instruction processing stage after the execution stage of the succeeding next instruction by interrupting the instruction execution unit when the access address and the preset event address match. Generate a match signal Characterized in that it constituted by a venting processor.

When the load instruction or the store instruction is decoded, the instruction code analyzing means stops the processing of the instruction decoder and waits until a register value necessary for calculating the address is determined. A processing control signal can be generated.

Further, the event instruction decoding means may execute the instruction processing after the instruction execution stage at the timing when the data read operation from the memory and the data storage operation to the internal register of the debug CPU in the load instruction are completed. The operation of the stage may be stopped to disable execution of the subsequent instruction.

Further, the event instruction decoding means stops the operation of the instruction processing stages after the instruction execution stage at the timing when the write operation to the memory in the store instruction is completed, and invalidates the execution of the subsequent instruction. You can also.

The event instruction decoding means may include an idle period which the load instruction and the store instruction have in advance in order to wait for the operation of the instruction processing stage after the decode stage until the memory access stage of the immediately preceding instruction is completed. In response to the above, even for the subsequent instruction having no idle period, decoding is stopped for waiting the operation of the instruction processing stage after the decode stage until the memory access stage of the load instruction and the store instruction is completed. A control signal for setting a period can be generated.

Further, even if the control signal for setting the decoding stop period is generated, the event instruction decoding means immediately after the decoding stop period unless the detection of the event becomes valid, immediately after the instruction execution stage of the subsequent instruction. The instruction processing stages can be executed continuously.

Further, the instruction code analyzing means includes:
A decoder, an address register selection circuit, and a transfer register selection circuit, wherein the decoder converts an instruction code input through an instruction queue into binary data,
If the bit indicating the type of the instruction in the binary data is a load or store instruction, the decoding process control signal is output to the instruction decoder, and the address register selection circuit and the transfer register selection circuit As the signal indicating which register is specified by the instruction code from the data, one corresponding to each of the address register selection signal and the transfer register selection signal can be output.

Further, the access address generator includes a data length extension shifter and an address adder, and the data length extension shifter has a bit width of address displacement data for converting into data necessary for address generation. The address adder may perform sign extension and add the extended displacement data, which is the converted displacement data, and the register data for register indirect addressing to calculate an access address to be actually accessed. .

Further, the event processing means includes an event address register and an address comparator. The event address register is a storage area for setting information on an address among conditions to be detected, and stores event data from an external event management area. When information is sent via the bus, an event enable signal and an event address are output, and the address comparator receives a load instruction select signal and the store instruction select signal generated by the instruction code analyzing means in addition to the comparator. An exclusive-OR circuit that outputs a comparator enable signal when one of them is valid, the result of the comparison between the event address and the access address output from the access address generator matches, and Can output an address coincidence detection signal upon activation of the signal.

Further, as a signal delay reducing means after outputting the instruction fetch means, the event detection means decodes an instruction accompanied by a memory access represented by a load instruction and a store instruction at the decode timing of the instruction decode. The layout means may have a layout structure in which the means is arranged adjacent to the instruction decoder of the debug CPU.

According to the event detection method of the present invention, in the event detection method of the event detection circuit built in the debug CPU of the development support device used for program development, the timing at which the debug CPU decodes the instruction of the debug program being executed is provided. At the same timing as above, when only the load instruction or the store instruction from the debug program is decoded by the instruction code analyzing means and the decoding of the subsequent instruction is stopped for a predetermined period, and the access address and the preset event address match. The instruction execution means is interrupted by an address match signal generated by the event processing means, and the instruction processing stages subsequent to the execution stage of the succeeding next instruction are invalidated.

Another feature of the method for detecting an event by the event circuit built in the debug CPU of the present invention is that in the event detection method by the event detect circuit built in the debug CPU in the development support device, the event is read in the instruction fetch stage. Instruction decoding for an event including instruction decoding means for decoding an instruction, instruction code analysis means for extracting a load instruction and a store instruction from the read instruction, and access address generation means for generating an access address of the read instruction The instruction decoding means using event register means for setting an event address in advance and an address comparator for comparing the event address and the access address and outputting an address match signal when they match. At the same timing, decode processing of an instruction to be decoded is performed in parallel, and if the instruction is a load instruction or a store instruction, a decode processing control signal is output to latch and stop the processing being executed by the instruction decode means. After the address to be accessed by the memory is determined by the access address generation means, an address match detection signal is output when the determined address matches the event address. In this case, the operation of the instruction execution means is stopped by generating an interrupt in the interrupt processing unit.

The feature of the external peripheral circuit of the debugging CPU of the present invention is that an instruction code analyzing means for extracting a load instruction and a store instruction from instructions read in the instruction fetch stage and stopping the decoding of a subsequent instruction for a predetermined period, and An event instruction decoding means comprising an access address generating means for generating an access address of the read instruction; and interrupting the instruction execution means when the access address and a preset event address match, to interrupt the subsequent next instruction. A trace unit is provided outside a debug CPU provided with an event detection circuit including an event processing unit for generating an address match signal for invalidating an instruction processing stage after the execution stage. The trace unit includes an instruction fetch bus. , External address bus and external A trace memory connected to the data bus to write the progress of program execution, and event data from the event data bus in response to the address match detection signal issued immediately after the instruction of the event is executed. And a trace event control unit for controlling the timing of starting and ending the trace so that a signal is generated and the write enable signal does not cause erroneous writing to the trace memory.

The trace section includes a trace event control section for inputting the address match detection signal and controlling start and end of a trace, and a trace memory in which the progress of program execution is written. The unit includes a trace event comparison unit that receives event data from an event data bus, and an AND circuit that outputs an output signal of the trace event comparison unit and the address match detection signal and outputs a write enable signal.

Another feature of the external peripheral circuit of the debug CPU of the present invention is that an instruction code analyzing means for extracting a load instruction and a store instruction from instructions read in the instruction fetch stage and stopping the decoding of a subsequent instruction for a predetermined period, and An instruction decoding means for an event comprising access address generation means for generating an access address of the read instruction; and an execution stage for executing the subsequent instruction by interrupting the instruction execution means when the access address matches a preset event address. A timer unit is provided outside a debugging CPU having an event detection circuit including an event processing unit for generating an address match signal for invalidating a subsequent instruction processing stage. The timer unit includes a timer counter, The instruction targeted by was executed In response to the address match detection signal issued later, event data is taken from the bus to generate a count start signal and a count stop signal, and the two signals are used to start counting so that an error does not occur in the count number of the timer counter. And a timer event control unit for controlling the end timing.

The timer unit includes a timer event control unit that controls the start and end of the timer counter by using an event, and a timer counter that can control a counting operation by the event. A timer event comparator for receiving and comparing the event data, a first AND circuit for receiving the output signal of the timer event comparator and the address match detection signal and outputting a counter start signal, And a second AND circuit that receives the address match detection signal and outputs the counter stop signal.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An outline of an event detection circuit according to the present invention will be described with reference to FIG. 1 showing a configuration of a first embodiment of the present invention. By referring to the execution result of the provided instruction decoding means, the timing for detecting a memory access event is set immediately after the execution of the instruction that caused the memory access.

An outline of an event detection method according to this embodiment will be described. First, the event instruction decoding unit 104 is arranged in parallel with the instruction decoding unit 103 which processes one of the procedures in which the debug CPU 101 executes an instruction. Perform decoding processing. That is, the decoding process is started at the same timing as that of the instruction decoding unit 103.

Subsequently, the event instruction decoding unit 104
Determines from the instruction code that the instruction to be decoded is a load or store instruction, and sends a decode processing control signal to the instruction decode unit 103 on the signal line 13.
9 to latch and stop the processing being executed by the instruction decoder 121.

By stopping the latch, the contents of the addressing register, which is information necessary for executing the decoded instruction, are determined. This means that there is no undetermined item when executing the instruction.

At this point, since the address to be accessed by the memory is determined, the event address register 1
It can be compared with the address set in 41.

When the addresses match as a result of the address comparison, the address comparator 142 outputs an address match detection signal via the signal line 144.

The address match detection signal is sent to the instruction execution unit 1
By inputting to the interrupt processing unit 152 at 06, an interrupt can be generated in the interrupt processing unit 152 and the execution unit 151 can be stopped.

By this processing operation, the execution unit 151
Can be processed under the condition that it is stopped immediately after its execution operation, and the execution stage of an instruction involving a memory access to be executed can be stopped immediately after the execution of the subsequent instruction, thereby improving the debugging efficiency. .

Next, the first embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

Referring to FIG. 1, a debug CPU 101 equipped with an event detection circuit according to the present invention includes an instruction fetch unit (IF) 102 and an instruction decode unit (ID) 103.
, An instruction execution unit (EX) 106, an event instruction decoding unit 104, an event processing unit 105, and an internal register unit 107.

The instruction fetch unit (IF) 102 is connected to an external fetch bus 172, the instruction decode unit (ID) 103 is connected to an internal data bus 173, and the event processing unit 105 is connected to an internal event data bus 171.
Are connected, and the internal register unit 107 is also connected to the internal data bus 1.
73 is connected.

The instruction fetch unit 102 includes a bus interface 111 and an instruction queue 112. The bus interface 111 reads an instruction code from the fetch bus 172. The instruction queue 112 sequentially stores the instruction codes read by the bus interface 111 via the bus interface output bus 113, and outputs the instruction codes to the next step.

The instruction decoding unit 103 includes the instruction decoder 1
21. The instruction decoder 121 decodes an instruction code received from the instruction queue 112 via the instruction queue output bus 114. From the decoding result, 1
By specifying the operation of the instruction using information of a bit or a plurality of bits, an address necessary for executing the instruction is generated and a target internal register is selected. Then, as the next step, the information of the specified instruction is output to the instruction execution unit 106 via the decode output bus 122.

The instruction execution unit 106 includes an execution unit 151
And an execution unit 151 including
Receives an interrupt signal generated by the interrupt processing unit 152 via an interrupt signal line 153.

Execution unit 151 is the instruction identified in the immediately preceding step,
Execute the instruction input through the.

When receiving an address match detection signal described later via the address match detection signal line 144, the interrupt processing unit 152 outputs an interrupt signal to the interrupt signal line 153 to stop the execution unit 151.

The event instruction decoding unit 104 includes a load / store instruction code analysis unit 131 and an access address generation unit 132.

Load / store instruction code analyzer 131
Referring to FIG. 2 showing the configuration, the decoder 20
1, an AND circuit group (AND gate) group 202, an address register selection circuit 203, and a transfer register selection circuit 20
4 and an exclusive OR circuit (XOR gate) 205.

The decoder 201 has an instruction queue output bus 1
Hex (HE), which is the instruction code input through
X) Convert the data to binary (BIN) data so that it can be processed bit by bit. Referring to FIG. 3 showing the format of the decoded instruction code, the instruction code format includes an instruction code, an operation of the instruction, and a description of abbreviations.

That is, the symbol instruction “LD disp
The instruction code for [r], R "is" dddddddd
RRR01rrr ", and the instruction operation is transfer from the access address area to the transfer register (load instruction).

The symbol instruction "STR, disp"
The instruction code for “[r]” is “ddddddddRR
R10rrr ", and the instruction operation is a transfer from the transfer register to the access address area (store instruction).

If the bit (the fourth and fifth bits of the LSD) representing the type of instruction in the converted binary data is a load or store instruction, the decode control signal is sent to the decode control signal line 139. Instruction decoder 1 through
21.

The address register selection circuit 203
From the information converted to binary data, the instruction code (rrr)
A register selection signal for address, which is information indicating which register is designated by (1), is output via an address register selection signal line 137.

The transfer register selection circuit 204 transfers a transfer register selection signal, which is information indicating which register is specified by the instruction code (RRR), from the information converted into binary data. Output via the register selection signal line 138.

When the fourth bit of the instruction code is “1”, the AND gate 202 of the fourth bit is set to the load instruction selection signal line 1
Activate 35.

When the fifth bit of the instruction code is “1”, the fifth-bit AND gate 202 is connected to the store instruction selection signal line 1
Activate 36.

The XOR gate 205 stores the fourth bit (load instruction) and the fifth bit (store instruction) of the instruction code.
When one of them is "1", the decode processing control signal line 13
Activate 9

The ninth to sixteenth bits of the instruction code are used as address displacement data on the signal line 13.
3 is output.

The group of AND gates 202 controls whether or not to output a binary instruction code 206, which is a result of decoding an instruction, according to an event enable signal provided via a signal line 145.

Referring to FIG. 4 showing the configuration, access address generating section 132 includes data length extension shifter 3.
01 and an address adder 302.

Referring to FIG. 5 showing the configuration, data length extension shifter 301 converts the ninth to sixteenth bit address displacement data of the instruction code on bus 137 into data necessary for address generation. In order to perform the conversion, the sign displacement of the bit width of the address displacement data is extended, here, the signal line 401 for 8 bits is further extended, and output to the bus 303 as 16-bit extended address displacement data.

The address adder 302 responds to the address register selection signal on the signal line 137, and outputs the expanded displacement data, which is the converted displacement data on the bus 303, and the register indirect addressing on the bus 161. Then, a process of calculating an access address to be actually accessed and outputting the calculated address to the bus 134 is performed.

The event processing unit 105 includes an event address register 141 and an address comparator 142.

The event address register 141 is a storage area for setting information on an address among conditions to be detected for an event, and is connected to an external event management area via an event data bus 171.

The event address register 141
When information is sent from an external event management area, an event enable signal is sent to the event enable signal line 145.
Output to Since the external event management area is not directly related to the present invention, the description is omitted here.

Referring to FIG. 6 showing the structure of the address comparator 142, the event address output from the event address register 141 to the bus 143 by the two-input comparator and the output from the access address generator 132 to the bus 143 are shown. The comparator 501 compares the obtained access address 134 with the access address 134, and outputs an address match detection signal to the signal line 144 if they match.

The comparator 501 has a signal line 1
35, a load instruction selection signal input from the
A store instruction selection signal input from the XOR gate 502
Has been entered. The XOR gate 502 outputs a comparator enable signal to the comparator 501 via the signal line 503 when one of the input signals is valid. The valid state in this case indicates that the logical value input to the XOR gate 502 is “1”.

The internal register section 107 is a storage area allocated to a register which is a resource of the CPU.
61 are connected.

Next, the operation of the first embodiment will be described with reference to FIGS. 1 to 7 and FIGS. 8 and 9 showing timing charts for explaining the operation.

First, referring to FIG. 1, a debugging CPU
In order to execute an instruction, first, a bus interface 111 in the instruction fetch unit 102 sequentially stores an instruction code in an instruction queue 112 via a fetch bus 172.
Store.

Subsequently, the instruction decoder 121 and the event instruction decoder 104 in the instruction decoder 103 are provided.
The instruction code output from the instruction queue 112 is stored in a load 114
And the instruction code is analyzed in each case.

Here, the instruction decoder 121 and the load / store instruction code analyzer 13 of the present invention will be described with reference to FIG.
The operation of the load / store instruction code analysis unit 131 will be described in comparison with 1.

The instruction decoder 121 and the load / store instruction code analyzer 131 to which the instruction code has been input from the bus 114 first convert the instruction code from hexadecimal data to binary data.

This is because the instruction code can be handled as data for each bit, and such processing is performed from the format of the instruction code. The instruction decoder 121 targets all instructions supported by the debug CPU 101, but the load / store instruction code analyzer 1
At 31, since only the load or store instruction is targeted using binary data indicating the mnemonic of the instruction,
The time for determining the target load or store instruction can be reduced due to the circuit size.

After it is determined that the instruction is a load or store instruction, the load / store instruction code analyzing unit 131
Outputs a decode control signal to the instruction decoder 121 via a signal line 139,
Stop the processing of.

The reason why the processing of the instruction decoder 121 is stopped is that the target instruction is a load or store instruction. These instructions are
Since the instruction involves a memory access, the target memory address must be determined.

At this time, the value of the register is required. When the addressing of the load or store instruction is the register indirect addressing, the address to be accessed is determined by the displacement and the register value included in the instruction code.

The value of the register required for determining the address may not be determined until the instruction executed immediately before the instruction currently being processed ends. Therefore, it is necessary to stop the processing of the instruction decoder 121 and wait until the immediately preceding instruction is executed.

Referring again to FIG. 1, the load / store instruction code analysis unit 131 can determine the address to be accessed when the register value is determined from the instruction code. And a register selection signal, that is, a register selection signal for address and a register selection signal for transfer,
37 and 138, and the address displacement data via bus 133.

The load instruction select signal and the store instruction select signal are output to the address comparator 142 in the event processing section 105 via signal lines 135 and 136, respectively. These signals are used to determine whether the event detection processing can be performed.

On the other hand, load / store instruction code analyzer 1
The access address generation unit 132, to which the address register selection signal, the transfer register selection signal, and the address displacement data from 31 have been input, calculates the access address and outputs it to the address comparator 142 via the signal line 134. I do.

Here, the operation of the access address generator 132 will be described with reference to FIGS. First, the address displacement data required for register indirect addressing is sign-extended (8-bit signal line 401 in FIG. 4) by the data length extension shifter 301. This uses a sign bit to match the register bit width, for example, a 16-bit width, for addition with a register.

Next, the extended address displacement data, which is sign-extended and output to the signal line 303, is input to the address adder 302, and when the address register selection signal on the signal line 137 is active, the signal line 1
It is added to the register data of 61.

Further, the operation of the address comparator 142 will be described with reference to FIGS. First, in response to a comparator enable signal, which is an output signal of the XOR gate 502, which becomes "1" level when one of the load instruction selection signal of the signal line 135 and the store instruction selection signal of the signal line 136 is active, the address comparator The comparator 601 compares the output of the event address register of the signal line 143 with the access address of the signal line 134 for each bit.

All data for each bit compared are "1".
If they match, the AND gate 602 outputs an address match detection signal to the signal line 144 to notify the block necessary for event detection that an event has been detected.

Since the present embodiment is applied to the case where an event is used for a break, an address match detection signal is input to the interrupt processing unit 152 in the instruction execution unit 106 via the signal line 144, and the execution unit Prepare to stop 151. The break used here indicates an operation of interrupting the program being executed by using a dedicated interrupt of the debugging CPU 101.

Here, a procedure from decoding of the fetched instruction to detection of an address match of the event will be described with reference to a timing chart shown in FIG. The timing chart of FIG. 8 shows the processing of the debugging CPU 101 using the pipeline for each clock 801A, and a first instruction 802A is an execution timing of an arithmetic operation instruction for a register.

While the first instruction 802A processes up to the instruction decode stage (ID), the load instruction as the second instruction 803A is processed up to the instruction fetch stage (IF).

At this time, since the first instruction 802A and the load instruction as the second instruction 803A are assumed to use the same register, the load instruction as the second instruction 803A is equivalent to two clocks. It becomes idle state. This is the section 805A waiting for the result of the first instruction. During this time, the first instruction 802A is in the instruction execution stage (EX)
And processing up to the memory access stage (MEM).

When the idle state ends, the first instruction 802A executes a write-back stage (WB), and the load instruction, which is the second instruction 803A, is an instruction decode stage ( The load / store instruction code analysis unit 131 outputs a decode processing control signal to the instruction decoder 121 via the signal line 139.

At this point, since the value of the register used by the load instruction as the second instruction 803A has been determined,
The calculation of the access address of the signal line 134 and the coincidence detection by the address comparator 142 are performed.

At this timing, the arithmetic operation instruction, which is the third instruction 804A, is stopped when the instruction fetch stage (IF) has been completed, and the pipeline enters an idle state for two clocks. This is the section 806A waiting for the result of the second instruction. This idle state is the second instruction 80
This is to secure time until the load instruction of 3A is completed. At this time, the second instruction 803A is executing processing up to the instruction execution stage (EX) and the memory access stage (MEM).

During this time, an address match detection signal is output from the address comparator 142 to the interrupt processing unit 152 in the instruction execution unit 106 via the signal line 144, and an interrupt signal is output from the interrupt processing unit 152 to the execution unit 151. Therefore, the third unit in the execution unit 151
Of the arithmetic operation instruction of the instruction 804A of FIG.
Instruction 804A stops when the instruction decode stage (ID) ends, and the subsequent stages become invalid.

By the operation described above, immediately after executing the load instruction which is the second instruction 803A targeted in the present embodiment, the subsequent third instruction 804A is stopped.

Next, a procedure from decoding of a fetched instruction to detection of an address match will be described with reference to a timing chart of FIG. FIG. 9 shows the case where the second instruction is a store instruction, and shows the processing of the debug CPU 101 using the pipeline for each clock 801B as in FIG. 8, and the first instruction 802B is an arithmetic operation instruction for a register. Is the execution timing. First instruction 8
While 02B processes up to the instruction decode stage (ID), the store instruction that is the second instruction 803B is processed up to the instruction fetch stage (IF).

At this time, the first instruction 802B and the second instruction 803B are assumed to use the same register for the store instruction.
The 3B store instruction is in an idle state for two clocks. This is the section 805B waiting for the result of the first instruction.

When this idle state ends, the store instruction of the second instruction 803B is changed to the instruction decode unit 1 for the event.
04 is decoded in the instruction decode stage (ID2) which is processed. In response to this decoding result, load /
The store instruction code analysis unit 131 outputs a decode processing control signal to the instruction decoder 121 via the signal line 139.

At this point, the value of the register used by the store instruction of the second instruction 803B has been determined.
2 is performed.

At this timing, that is, the arithmetic operation instruction of the third instruction 804B is stopped by the decode processing control signal of the load / store instruction code analysis unit 131 at the stage when the instruction fetch stage (IF) is completed, and the pipeline is stopped. It becomes idle state for two clocks. This is the section 806B that waits for the result of the second instruction, and secures the time until the store instruction of the second instruction 803B ends.

During this time, the address match detection signal 144 is output to the interrupt processing unit 152 in the instruction execution unit 106, and the third instruction 804B is set to the instruction decode stage (I
When D) ends, the operation stops, and the subsequent stages become invalid.

By the above-described operation, immediately after the execution of the store instruction of the second instruction 803B targeted in the present embodiment,
The subsequent third instruction has stopped.

On the other hand, the operation when no address match is detected in FIG. 9 will be described with reference to the timing chart shown in FIG. FIG. 10 shows the processing of the debug CPU 101 using the pipeline as the clock 801.
The first instruction 802C is also an execution timing of an arithmetic operation instruction for a register.

While the first instruction 802C processes up to the instruction decode stage (ID), the store instruction as the second instruction 803C is processed up to the instruction fetch stage (IF). At this time, since the store instruction of the first instruction 802C and the store instruction of the second instruction 803C are assumed to use the same register, the store instruction of the second instruction 803C is in an idle state for two clocks, that is, , Section 805C waiting for the result of the first instruction.

When this idle state ends, the store instruction of the second instruction 803C is changed to the instruction decode unit 1 for the event.
The instruction is decoded in the instruction decode stage (ID2) processed by the 04, and the load / store instruction code analyzer 131 outputs a decode processing control signal to the instruction decoder 121 via the signal line 139.

At this point, the value of the register used by the store instruction of the second instruction 803C has been determined.
2 is performed.

At this timing, in response to the decode processing control signal, the arithmetic operation instruction of the third instruction 804C is stopped when the instruction fetch stage (IF) is completed, and the pipeline enters an idle state for two clocks. .

This is the interval 80 for waiting for the result of the second instruction.
6C, which secures a time until the store instruction of the second instruction 803C ends.

Here, since the access address of the signal line 134 does not match the output of the event address register of the signal line 143, the address match detection signal is inactive and the level of the signal line 144 remains "0". , The interrupt processing unit does not output the interrupt signal 153.

Therefore, the arithmetic operation instruction of the third instruction 804C is also executed in the stages after the instruction decode stage (ID).

As a chip layout, it is desirable to arrange the event instruction decoding unit 104 adjacent to the instruction decoding unit 103. That is, the output of the instruction queue 112 is transmitted via the wiring 114 to the instruction decoding unit 10.
This is for minimizing the wiring delay when wiring to the instruction decoding unit 104 for event No. 3 and the event.

According to the first embodiment described above, an instruction for accessing a memory, for example, a load instruction,
Even in the case of a store instruction, by calculating the address of the target memory access at the same timing as the instruction decode stage (ID1) of the instruction decode unit 103, immediately after the execution of the instruction for accessing the memory is completed,
Thus, it is possible to stop the execution stage of the instruction (the third instruction in the above-described example) that is the target of the memory access event and thereafter.

The reason is that the idle state of the pipeline is used. That is, by setting the operation of the pipeline to the idle state, the instruction execution stage can be delayed and the next instruction execution can be invalidated.

For example, considering the single-chip microcomputer V850 family manufactured by NEC Corporation, CP
If the U clock is 66 MHz, the delay time is as follows.

1/66 [uS / clock] × 1-2 [clock] = 1.51-3.02 [uS] ‥‥‥‥‥‥‥‥‥‥‥‥‥‥ (1) That is, the expression ( Although the real-time property of the instruction execution at the time indicated by 1) is impaired, the present embodiment in which the instruction targeted for the memory access event stops after the execution of the decode stage, as compared with the related art in which the time difference of the memory access event detection occurs. , 1-2 instructions can be prevented from being executed.

When this is applied to the operator using the debugging device, assuming that the debugger operator sets an event, repeats the execution of the program, and confirms the stop position of the program, the operator confirms the operation. The time required is as follows: Event setting using the debugger {State 1 Instruction confirmation from instruction position from program stop position} State 2 , State 1 = 300 times, state 2 = 12
In the case of [S], 300 times × 12 [S] = 3600 [S] ‥‥‥‥‥‥‥‥‥‥‥‥‥ (2).

The effect can be said to be great even when considering the work of the time of Expression (2).

Next, a second embodiment of the present invention will be described.

Referring to FIG. 11 showing the configuration of the second embodiment, the trace unit 108, which is one of the units using an event, is provided outside the debug CPU 101 with an event data bus 171 and an external address bus 174.
, External data bus 175 and address match detection signal 1
44 and is provided.

The trace section 108 receives an address match detection signal via a signal line 144, and includes a trace event control section 701 for controlling the start and end of a trace, and a trace memory 702 for writing the progress of program execution. In.

The trace event control section 701 has a trace event comparison section 703 whose input terminal is connected to the event data bus 171, an output line of the trace event comparison section 703 and an address match detection signal line 141 connected to the input terminal, Its output terminal is a write enable signal line 703.
Connected to an AND gate 704.

The operation of this circuit is determined by the event processing unit 105
Trace event control unit 701 receiving an address match detection signal output from the address comparator 142
Outputs a write enable signal to the trace memory 702 via a signal line 903,
2 is controlled.

That is, when the trace event comparison unit 703 receives data indicating that “an event is associated with a trace event” from the event data bus 141, the trace event comparison unit 703
04 is output to enable a write enable signal to be output to the trace memory 702 by an address match signal. This enables tracing when the address match signal becomes valid.

Here, the timing of writing to the trace memory 702 becomes a problem. That is, if the address match detection signal is not output immediately after the execution of the instruction targeted for the event, the write control to the trace memory 702 is delayed, so that necessary data is not written or unnecessary data is not written. Is written.

In the second embodiment, the timing of writing to the trace memory 702 can be adjusted by applying the present invention to the trace function, so that the operation of the first embodiment can be further extended.

Next, a third embodiment of the present invention will be described.

Referring to FIG. 12 showing the configuration of the third embodiment, a timer unit 109, which is one of the units using an event, connects an event data bus 171 and an address match detection signal line 144 to each other. Is provided.

This timer section is a timer counter provided separately from the timer built in the debug CPU, is used for debugging, and is mainly for measuring the execution time of the program to be debugged.

The timer unit 109 includes a timer event control unit 801 that controls the start and end of the timer counter 802 using an event, and a timer counter 802 that can control the count and operation by the event.

The timer event control section 801 has a timer event comparison section 803 whose input terminal is connected to the event data bus 171, an output line of the timer event comparison section 803 and an address match detection signal line 141 connected to the input terminal, An AND gate 804 whose output terminal is connected to the counter start signal line 806;
And an AND gate 805 whose output end is connected to the counter stop signal line 807.

The operation of this circuit is determined by the event processing unit 105
The timer event control unit 801 having received the address match detection signal output from the address comparator 142 through the signal line 144 outputs a count start signal 806 or a count stop signal 807 to the timer counter 802. , A timer counter 802.

That is, when the timer event comparison unit 803 receives data indicating “the event is associated with the timer event” from the event data bus 141, the timer event comparison unit 803 sets the AND gate 804
"1" to output a timer start signal to the timer counter 802 in response to the address match signal.

On the other hand, from the event data bus 141, "the association of the event with the timer event has been completed."
When the timer event comparing unit 803 receives the data indicating that the
05 is output to enable a timer stop signal to be output to the timer counter 802 by the address match signal. This enables tracing when the address match signal becomes valid.

Here, the timing of the start and stop of the timer becomes a problem. That is, if the address match detection signal is not output to the signal line 144 immediately after the execution of the instruction targeted for the event, the timer counter 8
02 is delayed, and an error occurs in the number of times of counting.

In this embodiment, since the start and end timings of the timer counter 802 can be adjusted by applying the present invention to the timer function, the operation of the first embodiment can be further extended.

[0142]

As described above, the debugging C of the present invention is used.
An event detection circuit built in the PU extracts, in addition to the instruction decoding means for decoding the instruction read in the instruction fetch stage, a load instruction and a store instruction from the read instruction, and stops the decoding of the succeeding next instruction for a predetermined period. An instruction decoding means for an event comprising an instruction code analysis means and an address generation means for generating an access address of the read instruction; and a next instruction which interrupts the instruction execution means when the access address and the preset event address match, and then follows the next instruction And an event processing means for generating an address match signal for invalidating an instruction processing stage after the execution stage of
Even in the case of an instruction that accesses the memory, the address of the target memory access is calculated at the same timing as the instruction decode stage (ID1),
The instruction targeted for the memory access event can be stopped immediately after execution.

That is, since the idle state of the pipeline is used, the instruction execution stage can be delayed by setting the pipeline operation to the idle state, and the next instruction execution can be invalidated.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a load / store instruction code analysis unit 131.

FIG. 3 is a diagram showing an instruction code format applied in the present embodiment.

FIG. 4 is a block diagram of an access address generation unit 132;

FIG. 5 is a configuration diagram of a data length extension shifter 301;

FIG. 6 is a block diagram of an address comparator 142.

FIG. 7 is a block diagram of a comparator 501.

FIG. 8 is a timing chart for explaining operation when an address match is detected during execution of a load instruction according to the first embodiment;

FIG. 9 is a timing chart for explaining the operation when an address match is detected during execution of a store instruction according to the first embodiment;

FIG. 10 is a timing chart for explaining operation when an address match is not detected during execution of a store instruction according to the first embodiment;

FIG. 11 is a configuration diagram of a second embodiment of the present invention.

FIG. 12 is a configuration diagram of a third embodiment of the present invention.

FIG. 13 is a configuration diagram illustrating an example of a conventional event detection unit.

FIG. 14 is a timing chart for explaining the operation when an address match is detected during execution of a load instruction by a conventional event detection means.

[Explanation of symbols]

Reference Signs List 101 debug CPU 102 instruction fetch unit 103 instruction decode unit 104 event instruction decode unit 105 event processing unit 106 instruction execution unit 107 internal register unit 108 trace unit 109 timer unit 111 bus interface 112 instruction queue 121 instruction decoder 131 load / store instruction Code analysis unit 132 Access address generation unit 141 Event address register 142 Address comparator 151 Execution unit 152 Interrupt processing unit 201 Decoder 202, 602, 704, 804, 805 AND gate 203 Address register selection circuit 204 Transfer register selection circuit 205, 502 XOR gate 301 Data length extension shifter 302 Address adder 501 Comparator 601 Comparator 701 Training Source event control unit 702 trace memory 703 trace event comparison unit 801 timer event control unit 802 timer counter 803 timer event comparison unit

Claims (16)

[Claims] An event detection circuit built in a debugging CPU of a development support device used for debugging a development target program, in addition to an instruction decoding means for decoding an instruction read in an instruction fetch stage, a load from the read instruction. Instruction code analyzing means for extracting an instruction and a store instruction and stopping the decoding of the next following instruction for a predetermined period; and an instruction decoding means for an event comprising access address generating means for generating an access address of the read instruction; And event processing means for generating an address match signal for interrupting the instruction execution means when a preset event address matches and invalidating an instruction processing stage after the execution stage of the subsequent instruction. Characterized by Event detection circuit built into the CPU for debugging. 2. The decoding device according to claim 1, wherein, when the load instruction or the store instruction is decoded, the instruction code analysis unit stops processing of the instruction decoder and waits until a register value necessary for calculating the address is determined. 2. The debug CP according to claim 1, wherein the process control signal is generated.
Event detection circuit built in U. 3. The event instruction decoding means according to claim 1, wherein at a timing when the data read operation from the memory in the load instruction and the data storage operation to the internal register of the debug CPU are completed, the instruction processing after the instruction execution stage. 2. The event detection circuit built in a debugging CPU according to claim 1, wherein the operation of the stage is stopped to disable execution of a subsequent instruction. 4. The event instruction decoding means stops the operation of an instruction processing stage after the instruction execution stage at the timing when the write operation to the memory in the store instruction is completed, and invalidates the execution of the subsequent instruction. An event detection circuit built in the debug CPU according to claim 1. 5. The idle instruction period included in the load instruction and the store instruction in order for the event instruction decoding means to wait for the operation of an instruction processing stage after the decode stage until the memory access stage of the immediately preceding instruction is completed. In response to the above, even for the subsequent instruction having no idle period, decoding is stopped for waiting the operation of the instruction processing stage after the decode stage until the memory access stage of the load instruction and the store instruction is completed. 2. The event detection circuit according to claim 1, wherein the event detection circuit generates a control signal for setting a period. 6. The event instruction decoding means, even if a control signal for setting a decoding stop period is generated, immediately after the decoding stop period unless the detection of the event becomes valid, after the instruction execution stage of the subsequent instruction. 2. The event detection circuit built in a debugging CPU according to claim 1, wherein the instruction processing stage is executed continuously. 7. The instruction code analysis means includes a decoder, an address register selection circuit, and a transfer register selection circuit, wherein the decoder converts an instruction code input via an instruction queue into binary data. If the bit indicating the type of the instruction in the binary data is a load or store instruction, the decode processing control signal is output to an instruction decoder, and the address register selection circuit and the transfer register selection circuit 3. The debug according to claim 2, wherein a corresponding one of the address register selection signal and the transfer register selection signal is output as a signal indicating which register is specified by the instruction code from the binary data. Event detection circuit built into the CPU. 8. The access address generation section includes a data length extension shifter and an address adder, wherein the data length extension shifter has a bit width of address displacement data for converting into data required for address generation. The address adder performs sign extension, and the address adder adds an extended displacement data, which is converted displacement data, and register data for register indirect addressing to calculate an access address to be actually accessed. An event detection circuit built in the debug CPU described above. 9. The event processing means includes an event address register and an address comparator, wherein the event address register is a storage area for setting information on an address among conditions to be detected, and stores event data from an external event management area. When information is sent via the bus, an event enable signal and an event address are output, and the address comparator
In addition to the comparator, an exclusive OR circuit that receives a load instruction selection signal generated by the instruction code analysis unit and the store instruction selection signal and outputs a comparator enable signal when one of them is valid, 2. The event detection circuit built in the debug CPU according to claim 1, wherein a comparison result between the event address and the access address output from the access address generation unit matches, and an address match detection signal is output when the comparator enable signal is activated. . 10. An event detecting means as a signal delay reducing means after outputting an instruction fetch means for decoding an instruction for an event involving a memory access represented by a load instruction and a store instruction at the decode timing of the instruction decode. 2. The event detection circuit built in the debug CPU according to claim 1, wherein the event detection circuit has a layout structure in which is disposed adjacent to an instruction decoder of the debug CPU. 11. An event detection method of an event detection circuit built in a debug CPU of a development support device used for program development, wherein the debug CPU decodes an instruction of a debug program being executed at the same timing. Only the load instruction or the store instruction from the debug program is decoded by the instruction code analyzing means, the decoding of the subsequent instruction is stopped for a predetermined period, and the event processing means generates when the access address matches the preset event address. An event detecting method for an event detecting circuit built in a debugging CPU, wherein an interrupt is interrupted to an instruction executing means by an address match signal to invalidate an instruction processing stage after an execution stage of the succeeding next instruction. 12. An event detection method using an event detection circuit built in a debugging CPU in a development support apparatus, wherein in addition to an instruction decoding means for decoding an instruction read in an instruction fetch stage, a load instruction and a load instruction are read from the read instruction. An instruction decoding means for an event including an instruction code analyzing means for extracting a store instruction and an access address generating means for generating an access address of the read instruction; an event register means for setting an event address in advance; Using an event processing means including an address comparator which outputs an address match signal when the access addresses are compared and matched, decodes the instruction to be decoded in parallel at the same timing as the instruction decoding means, and If the instruction is a store instruction or a store instruction, a decode processing control signal is output to latch and stop the processing being executed for the instruction decode means, and the address to be accessed by the memory is determined by the access address generation means. Thereafter, when the determined address and the event address match, an address match detection signal is output, and an interrupt is generated in an interrupt processing unit in the instruction execution means by the address match detection signal to stop the operation of the instruction execution means. An event detection method using an event circuit built in a debugging CPU. 13. An instruction code analyzing means for extracting a load instruction and a store instruction from an instruction read in an instruction fetch stage and stopping the decoding of a subsequent instruction for a predetermined period, and an access address for generating an access address of the read instruction. An instruction decoding means for an event comprising a generation means for interrupting an instruction execution means when the access address matches a preset event address to invalidate an instruction processing stage subsequent to an execution stage of the following next instruction; A trace unit external to a debug CPU provided with an event detection circuit comprising an event processing means for generating an address match signal of the type described above. The trace unit is connected to an instruction fetch bus, an external address bus, and an external data bus, and The progress of execution is written Event data from the event data bus in response to the address match detection signal issued immediately after the instruction of the event to be executed is executed, and a write enable signal is generated. And a trace event control unit for controlling timing of starting and ending the trace so that erroneous writing to the trace memory does not occur.
External peripheral circuit. 14. The trace event control unit, comprising: a trace event control unit that inputs the address match detection signal and controls start and end of a trace; and a trace memory in which the progress of program execution is written. The unit includes: a trace event comparison unit that receives event data from an event data bus; and an AND circuit that receives an output signal of the trace event comparison unit and the address match detection signal and outputs a write enable signal. Item 14. An external peripheral circuit of the debugging CPU according to item 13. 15. An instruction code analyzing means for extracting a load instruction and a store instruction from an instruction read in an instruction fetch stage and stopping decoding of a subsequent instruction for a predetermined period, and an access address generating means for generating an access address of the read instruction. An instruction decoding means for an event comprising: an address match signal for interrupting the instruction execution means when the access address and the preset event address match to disable an instruction processing stage after the execution stage of the subsequent instruction. A timer unit is provided outside the debugging CPU provided with an event detection circuit comprising an event processing means for generating a timer counter, and the timer unit is issued immediately after execution of the instruction targeted by the event. In response to the address match detection signal A timer event control unit that captures event data from the bus, generates a count start signal and a count stop signal, and controls the timing of starting and ending counting by using these two signals so that an error does not occur in the count number of the timer counter. An external peripheral circuit of a debugging CPU, comprising: 16. The timer unit includes: a timer event control unit that controls start and end of a timer counter using an event; and a timer counter that can control a count operation by an event, wherein the timer event control unit includes: A timer event comparator for receiving and comparing the event data, a first AND circuit for receiving the output signal of the timer event comparator and the address match detection signal and outputting a counter start signal, 16. The debug CP according to claim 15, further comprising: a second AND circuit that receives the output signal of No. 2 and the address match detection signal and outputs a counter stop signal.
External peripheral circuit of U.