KR960003052B1 - Microprocessor having cashe memory unit - Google Patents

Abstract

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Description

Microprocessor with Internal Cache Memory Unit

1 is a block diagram showing the structure of a memory cache unit embedded in a microprocessor of the present invention.

2 is a block diagram showing the overall structure of a microprocessor of the present invention.

3 is a block diagram showing the structure of a program debugging system using the microprocessor of the present invention.

4 is a block diagram showing a second structural example of a memory cache unit built in the microprocessor of the present invention.

5 is a flowchart for explaining the operation of the memory cache unit of the microprocessor of the present invention.

* Explanation of symbols for main parts of the drawings

150: interrupt control circuit 200: microprocessor

210: prefetch unit 220: decoding unit

230: processing execution unit 240: valid address calculation unit

250: bus cycle control unit 260: instruction cache memory unit

270: data cache memory unit 310: memory device

320: debugging device

The present invention relates to a microprocessor incorporating a cache memory unit for caching data representing instruction code or memory operands, and in particular to enabling trap interruption of data stored in the cache memory unit while debugging a program. It relates to a microprocessor.

[Private Technology]

The following describes a separate debugging method used during program development with a microprocessor or when some problem is found in the system.

The first method is tracing. With this tracing technique, it is possible to find out the sequence (order) of instruction execution or operand / access by gathering data representing program execution locations or data related to access to memory / operland and assembling such data. The data described above generally consists of bus / cycle addresses, data, and statuses that can be observed at external microprocessor terminals.

This process does not require any special microprocessor functionality due to the fact that data is collected only externally and is not related to the operation of the microprocessor. In addition, with respect to the execution of the program to be debugged, there is no need to cause interruptions / exceptions or wait for the bus / cycle, so that the timing is not different between the debugging state and the non-debugging state. exist. This is a passive way of simply examining the state of a program as there is no interruption caused by a particular situation detection, simply with respect to the program being debugged.

The second method is Trapping. In the trapping scheme, control is passed to the debugging program (hereinafter referred to as “debugging”), and very precise debugging is performed, all from the fact that there is access to a special address instruction code or memory / operland determined previously. Do.

The difference with the tracing technique is that it has the advantage of enabling debugging by transferring control to debugging when it is needed. However, in order to correctly generate an interruption exception with respect to the determined address (e.g. immediately after or immediately after execution of the instruction code with the set address) a hardware type of mechanism (usually trapping interruption) that transfers debugging to control. In addition, the method has the following drawbacks. In other words, it is necessary to know the exact program execution sequence and cannot interrupt program execution when the trapping process cannot be set as scheduled.

The third method is a single step. In this single step, control is transferred to the debugger at the execution of each instruction so that the microprocessor's internal state (general purpose registers, processor / status / word (PSW), program / counter (PC), etc.) Is often displayed so that the execution of the program is done while some of the content is changed at the same time.

The fact that the internal state of the microprocessor can be understood at the time of instruction execution allows us to capture execution progress in great detail. On the other hand, a hardware type mechanism (generally called single-step interruption) is required to generate interruptions / exceptions and transfer control to the debugger when a single instruction is executed within the microprocessor itself. It can't be run at all. In addition, this method reduces execution efficiency due to the fact that control is shifted into the debugger for each instruction, the fact that timing critical processing (eg; timers / routines, etc.) cannot be executed by debugging, and internal operation timing. It has the drawbacks of being completely different between this debugging and non-debugging time.

Since each debugging method has the advantages and disadvantages as mentioned above, the methods are usually combined as follows. 1) A way of determining the actual sequence in which the instruction is executed by using the tracking mode. 2) Transfer of control to the debugger in the area where the problem occurs due to the trap function. 3) carefully tracking the instruction execution status one instruction at a time through the single step function.

Therefore, the trap function is an essential function for effective program debugging.

As mentioned above, special hardware is required in the microprocessor to realize the trap function, but subrogation is achieved through a single step and software processing in the debugger.

When the trap function is specified, single-level interruption is set, and the debugger returns to control when a single command of the program to be debugged is executed. At the same time, at the same time as evacuation of the microprocessor, a check is made as to whether a preset trap state is implemented. For example, when a trap is set in connection with a special address command code, a comparison is made through the contents of the evolved program counter. In addition, when a trap is established in connection with memory access of a particular address, the instruction code revealed by the evolved program counter is analyzed and, if the instruction entails memory access, the evolved general purpose register. The comparison is performed by calculating the target memory address using a value or the like.

If the preset trap condition is not met, control transfers to the original program and at the same time returns the evolved interior. The program to be debugged at this time is recognized to be unaffected in any way because the debugger does not output (eg, message) any of the debugging status to the user. On the other hand, when the preset trap condition is satisfied, the debugger outputs the fact that the trap is generated to the user, and subsequent generation of single-step interruption is canceled.

As described above, a similar trap function can be realized even when there is no trap interruption function in the microprocessor itself. However, since a single step interruption is used for each instruction, one by one, the efficiency is very poor until the trap condition is realized.

The following is a detailed description of the trap function in a programming debugging system. On the other hand, it is assumed that a system in which an external memory device and a microprocessor and a debugging device on the other side are connected via a bus.

The debugging device compares the contents of the trap address register setting the address causing the trap interruption, the trap cycle register setting the bus / cycle type causing the trap interruption, the address value and the trap address register and determines whether they are equivalent. A state comparator that compares the contents of the address comparator, the state data and the trap cycle register and determines whether they are equivalent, and a trap signal generation circuit for generating a trap interruption request signal via outputs from the address comparator and the state comparator. All are installed.

The trap interruption request signal from the debugging device is connected to the microprocessor trap interruption request terminal. When the microprocessor generates a signal, the address and status signal values are compared with the address and status preset by the debugging device. When the comparisons are equivalent, a trap interruption request signal is sent to the trap interruption terminal and the request signal is stored in the microprocessor at the end of the bus cycle. When the bus cycle is used within a microprocessor, a trap interruption occurs and the microprocessor transfers control to a debugger.

As mentioned above, to enable trapping, the debugging device must continuously compare the address and state output in synchronization with the bus cycle from the microprocessor.

To improve processing performance, it is contemplated that microprocessors include an instruction cache memory that caches instruction code and a data cache memory that caches memory operands. In the built-in cache memory, when memory data (both instruction code and memory operands) requested by the microprocessor is written to the cache memory (when data is written), it may generate a bus cycle to access the low speed external memory. Due to the fact that it is not necessary, high speed processing can be obtained.

In the microprocessor having the structure, the bus cycle for accessing the external memory is limited as follows.

Alternate bus cycles that occur when an instruction code that is not written in the instruction cache memory is accessed (i.e., miss-hit), or when an operand data that is not written during data cache memory read is accessed. Alternate bus cycles, which are the light cycles required to maintain consistency with external memory during reading of the data cache memory. Thus, even if processing inside the microprocessor proceeds, the debugging device that enables the trap function cannot be realized due to the fact that the bus cycle does not appear externally. For example, if all instruction codes corresponding to a local program region are cached by the instruction cache memory, the bus cycle corresponding to instruction code fetch does not occur due to the fact that the region corresponds to that region during processing of the region. Trap interruption cannot be done for addresses.

In order to avoid the above-mentioned problem, a countermeasure is proposed to switch the instruction cache memory operation to an unallowed state during debugging. However, in the above case, since the operation of the microprocessor is different from each other at the time of debugging and the actual processing in which the caching function is allowed, there is a problem that accurate debugging cannot be performed.

[Overview of invention]

An object of the present invention is to enable accurate trap interruption even for memory data that collides with cache memory, so that trap interruption for all instruction codes and memory operands can be applied, despite locality or other characteristics of the program. It is therefore to provide a microprocessor with a built-in cache memory unit for simple and efficient program debugging.

Another object is to provide a microprocessor with an integrated cache memory unit that delivers interruption data to the cache memory to perform trap interruption control and enable a trap function at the same processing time as the original program execution.

According to a preferred embodiment of the present invention for achieving the above object, a microprocessor having a built-in cache memory unit includes a processing execution device for data processing, a bus cycle control device for driving a bus cycle to access an external memory, the processing execution A cache memory unit for caching data processed by the device, the cache memory unit including a cache memory having a plurality of entries for storing addresses and data, and an interruption control device for controlling interruption, The cache memory has an interruption data area for each entry indicating whether an appropriate entry is the object of interruption, and the interruption control device synchronizes the interrupt request signal with the bus cycle upon replacement of the cache memory entry. If input by A function of registering interruption allocation data in the interruption data area of a memory entry, and determining whether there is interruption allocation data in the interruption data area when a data request relating to the cache memory entry is made; It has a function to output.

According to another preferred embodiment of the present invention, a microprocessor having an embedded cache memory unit includes a first cache memory unit for caching instruction code, and a second cache memory unit for caching data.

According to another preferred embodiment of the present invention, the cache memory of the cache memory unit includes an address storage memory and a data storage memory, wherein the address storage memory has an interruption data area for each entry.

According to another preferred embodiment of the present invention, the cache memory of the cache memory unit includes an address storage memory and a data storage memory, wherein the data storage memory has an interruption data area for each entry.

According to another preferred embodiment of the present invention, the cache memory unit has a selection device for selecting an entry required for replacement based on the hysteretic data of each entry during the cache memory entry replacement time.

According to another preferred embodiment of the present invention, the cache memory has a data storage area indicating whether an entry is valid for each entry.

The following detailed description will clarify other objects, features and effects of the present invention.

The following describes an ideal example of the present invention using FIGS. 1 to 5.

First, the overall microprocessor structure of the present invention is shown through the use of FIG. As shown in FIG. 2, the microprocessor 200 includes a prefetch unit 210, a decoding unit 220, a processing execution unit 230, a valid address calculation unit 240, a bus cycle control unit 250, an instruction cache memory. A unit 260 and a data cache memory unit 270. The instruction cache memory unit 260 performs instruction code caching, and the data cache memory unit 270 performs data (memory operand) caching.

The instruction code prefetched to the prefetch unit 210 via the data terminal DBT is once cached by the instruction cache memory unit 260 and then stored. The instruction code stored in the instruction cache memory unit 260 is transferred to the decoding unit 220 in response to a request from the decoding unit, and subsequently generates a control signal of the instruction unit. The processing execution unit 230 has a general purpose register, a processing device, a control circuit, and the like, which performs execution processing for each instruction in relation to the control signal generated by the decoding unit 220. In addition to the instruction function corresponding to the instruction code, execution processing includes handling exceptions and interruptions. When the instruction code for the request of the decoding unit 220 is not stored in the instruction cache memory unit 260, the prefetch unit 210 notifies the bus cycle control unit 250 of that fact.

The data cache memory unit 270 is disposed in parallel with the bus cycle control unit 250, and transfer between the integrated processing execution unit 230 and the cached memory operand is performed. If the memory / operand required by the processing execution unit 230 is not in the data cache memory unit 270, the memory address is calculated by the valid address calculation unit 240 and notified to the bus cycle control unit 250. do.

The bus cycle control unit 250 drives a bus cycle in accordance with the notification address and the type of request, and access to an external memory device is obtained. If there is a request coming from the prefetch unit 210, the result is an instruction fetch bus cycle according to the instruction code. In the case of a request from the processing execution unit 230, the result is a read and write bus cycle according to the memory data.

The bus cycle includes an address output signal from the address terminal ABT, an output or input data signal from the data terminal DBT, a status signal indicating the type of bus cycle (this signal comes from the status terminal STT), and a bus It consists of a timing signal indicative of cycle timing.

The processing execution unit 230, the valid address calculation unit 240 and the bus cycle control unit 250 are interconnected via an internal data bus ID and an internal address bus IA. The trap interruption request terminal ETRAP is a terminal for sampling the trap interruption request at the end of the bus cycle generated by the bus cycle control unit 250.

3 shows an example of the program debugging system of the present invention utilizing a microprocessor. In FIG. 3, the external memory device 310 is a memory accessed by the microprocessor 200, which is connected via a data bus DB, an address bus AB, and a status bus ST.

The debugging device 320 is connected to the microprocessor 200 via an address bus AB and a state bus ST.

The structure of the debugging device 320 is described below. The trap address register 321 is a register for setting an address for generating a trap interruption, the trap cycle register 322 is a register for setting a bus cycle type for generating a trap interruption, and the address comparator 323 is an address. A comparator that compares the address value from the bus AB with the contents of the trap address register 321 to determine whether they match, and the state comparator 324 is a state data from the state bus ST and a trap cycle register 322. Is a comparator that compares the contents of the signals and determines whether they match, and the trap signal generation circuit 325 generates a trap interruption request signal ETRAPREQ according to the outputs from the address comparator 323 and the state comparator 324. .

The trap interruption request signal ETRAPREQ coming from the debugging device 320 is connected to the trap interruption request terminal ETRAP of the microprocessor 200. When the microprocessor 200 generates a bus / cycle, a comparison is made between the values of the address and status signals from the address bus AB and the status bus ST, and the preset addresses and states. As a result of the comparison, if a match is detected, the interruption request signal ETRAPREQ is notified to the trap interruption request terminal and written into the microprocessor 200 at the end of the bus / cycle. Trap interruption occurs when the bus / cycle is used inside microprocessor 200, which transfers control to the debugger.

Hereinafter, a detailed configuration of the instruction data cache memory unit 270 of the microprocessor 200 illustrated in FIG. 2 will be described with reference to FIG. 1. In FIG. 1, as an example, the cache memory unit is capable of caching 1K bytes of memory data. This memory data includes both instruction code and memory operands. That is, the command code caching type, the data caching type, and the command code and data caching type are all acceptable. In case of performing data caching, a store through system can be used as the recording control system.

These cache memory units 260 and 270 include a tag memory unit 110, a data memory unit 120, a replacement entry selection circuit 140, and an interruption control circuit unit 150.

The tag memory section 110 is composed of 256 sets of entries W0-W255. Each entry W0-W255 has a valid bit section 111 indicating whether or not each corresponding entry is validly used, a trap bit section 112 indicating whether or not the entry address section is a target of trap interruption, and address data. The address section 113 stores 28-bit wide address data. The data memory 120 is composed of a data unit 121 (32 bits = 1 word) in units of 4 bytes corresponding to 256 sets of entries in the tag memory unit 110. The selected data section 121 outputs the output to either the internal data bus ID (in the case of data caching) or the decode unit 220 (in the case of instruction caching).

When the upper 28 bits (32 " memory addresses ") of 32-bit wide address data from the internal address bus IA (data caching) or prefetch unit 210 (command caching) are transferred to the cache memory unit, that memory An entry corresponding to the address portion 113 holding the same contents as the address is selected.

If no corresponding entry exists, an error signal MISS is generated. The microprocessor 200 selects a new entry, thereby causing the bus cycle control unit 250 to store word data obtained by driving a bus cycle in a specific data portion 121 of the data memory 120 of the selected entry. use. This series of operations is called replacement.

The replacement entry selection circuit 140 is a circuit for selecting an entry requiring replacement. The replacement entry selection circuit 140 retains hysteretic data for each entry and, upon selecting a new entry through replacement, selects entries that can be safely removed based on the hysteretic data. In general, control is performed by a Least Recently Used (LRU) method. The unit LRU method is a method of selecting the most recently used entry after referring to hysteretic data.

The interruption control circuit 150 generates a designated (assigned) indicated signal TIN, a control signal TSET, and a control signal TCLR for the purpose of controlling the trap bit 112. In addition, the above generates a detection signal TRAPET indicating detection of a trap interruption request based on the state of the trap bit 112. The trap interruption request signal is input to the interruption control circuit 150 via the trap interruption request terminal ETRAP, and the bus cycle signal BCYC is also input.

The assignment (designation) signal TIN executes trap interruption assignment via the control signal TSET, and trap bits of the tag memory section 110 for entries selected by the memory address or alternative entry selection circuit 140. Optionally set at 112, the allocation signal TIN is cleared by the control signal TCLR whenever necessary.

The operation of the above-described cache memory unit will be described below based on the flowchart of FIG. The flow of the trap interruption request is indicated by a dashed line in FIG.

First, it is determined whether there is a request for memory data or not (step 500). If there is a request for memory data, the address portion 113 matching the memory address from the internal address bus IA or the prefetch unit 210 is determined. It is determined whether there is an entry to be retained. (Step 501)

If no entry matches the memory address, the result is a miss-hit. In such a case, the following replacement operation is performed. First, an entry to be replaced is optionally determined through the replacement entry selection circuit 140, as described above (step 502). Next, a replacement operation is performed on the selected entry. The bus cycle is driven by the bus cycle control unit 250 (step 503). In this bus cycle, an address value matching the memory address is output to the address bus AB.

The memory data obtained by the replacement bus cycle is stored in the data portion 121 of the data memory portion 120 of the selected entry. In addition, when a trap interruption request is input to the trap interruption terminal ETRAP by the above-mentioned alternative bus cycle, the interruption control circuit 150 is coupled with the assignment signal TIN synchronized to the bus cycle signal BCYC. The timing control signal TSET is generated. As a result, the trap bit 112 for the entry of the tag memory section 110 selected by the replacement entry selection circuit section 140 has a set assignment signal TIN (step 504). The trap interruption request is notified from the prefetch unit 210 in the instruction cache memory unit 260 and from the direct trap interruption requistion terminal (ETRAP) in the data cache memory unit 270. .

Further, the memory address is stored in the address portion 113 of the entry (step 505), and the valid bit 111 is set in the selected entry (step 506). Immediately following the storage of the memory data in the data portion 121, the same memory data is transferred to the internal data bus ID or decoding unit 220 which is the request source (step 508).

In step 501, if there is an entry that matches the memory address, the first task is to check whether the valid bit 111 of the entry is set or not (step 507). If the valid bit 111 is not set, the replacement operation starting at step 502 is performed even if the entry in question matches the memory address, because the entry is essentially invalid.

In step 507, when the valid bit 111 is set, the memory data stored in the data portion 121 of the associated entry is transferred to the internal data bus (ID), or decode unit 220, which is the requesting source (step 508). The transmission takes place simultaneously with storage in the data portion 121.

Whether the allocation signal TIN in the trap bit 112 of the entry selected in the memory address is set after transferring the memory data stored in the data portion 121 to the internal data bus (ID) or the decoding unit 220 as a request source. Is checked (step 509). If not set, processing terminates. When the allocation signal TIN is set, the signal output TOUT is generated toward the interruption control circuit 150. This output signal TOUT is used to detect (confirm) the allocation of the trap interaction of the associated memory address (the detection is done by the interruption control circuit 150), and the circuit is a trap interruption detection signal ( TRAPDET) (step 510).

Then, if the cache memory data is an instruction code, the trap interruption detection signal TRAPET is notified to the decoding unit 220 of the microprocessor 200, and if the cache memory data is essentially data, the direct processing execution unit ( 230, the detection signal TRAPET is notified.

Receiving a trap interruption detection signal TRAPET, and after terminating the instruction execution processing, the processing execution unit 230 performs interruption processing without performing the next processing operation. Similar to the case of the normal interruption request from the interruption request terminal (INT), trap interruption processing loads the contents of the current program counter (PC) and program status word (PSW) into the stack of the external memory device 310. Evacuate the area and, depending on the type of interruption request, the processing branches to the reserved address.

It should be noted that there are three different operations as the operation after generation of the trap interruption detection signal TRAPET. The first operation is to generate a trap interruption for the associated associated memory address without changing the appropriate trap bit 112. This is the operation described in the flowchart above.

The second operation clears the appropriate trap bit 112 and the valid bit 111, follows a forcible replacement opration to the appropriate memory address, and reassigns the trap interaction. will be. In a third operation, the appropriate trap bit 112 is cleared and no subsequent trap interruption of the appropriate memory address occurs.

This operation is selectively used according to the debugging purpose, and the interruption control circuit unit 150 facilitates the control selectively. However, the appropriate trap bit 112 is easily cleared by the control signal TCLR.

4 shows the structure of the cache memory unit of the present invention through the second embodiment.

In this embodiment, the trap bits 412 are organized in a structure in which the data memory 420 is set rather than the tag memory 410. All other structural characteristics are generally the same as those shown in FIG. In addition, the cache memory unit operation of this embodiment is the same as that shown in the cache memory unit of FIG. 1, and has the same effect.

According to the microprocessor of the present invention, trap interruption is accurately realized even for memory data hit in the cache memory. As a result, trap interruption can be applied to all instruction code and memory operands regardless of the localization of the program, thereby enabling simple and efficient program debugging.

In general, when the trap function is realized through a single step interruption function, approximately 10-20 instructions are required for evacuation and restoration of certain conditions and software traps. The overhead to execute each specific instruction in the program to be debugged is required, and the processing speed during the trap function is more than 10 times slower than that of conventional program execution. Therefore, trap interruption control is performed by retaining interruption data in the cache memory, and the trap function can be realized at the same processing time as the execution time of the original program by setting the overhead to 0.

Various modifications can be made within the scope of the present invention in addition to the above-described embodiments.

Claims (6)

A microprocessor having a built-in cache memory unit, comprising: a processing execution unit for processing data; A bus cycle control device for driving a bus cycle to access an external memory; A cache memory unit for caching data processed by the processing execution device, wherein the cache memory unit includes a cache memory having a plurality of entries for storing addresses and data, and an interruption control device for controlling trap interruption; Wherein the cache memory has an interruption data area for each entry indicating whether or not the associated entry is the subject of a trap interruption, and the interruption control device requests a trap interruption upon replacement of the cache memory entry. A function of registering an interruption allocation signal in the interruption data area of the cache memory entry when a signal is input in synchronization with the bus cycle, and an interruption in the interruption data area when a data request relating to the cache memory entry is requested. Whether there is an allocation signal After a built-in cache memory unit with a microprocessor which has a function of outputting an interruption detection signal. 2. The microprocessor of claim 1, comprising a first cache memory unit for caching instruction code and a second cache memory unit for caching data. 2. The built-in cache memory of claim 1, wherein the cache memory of the cache memory unit includes an address storage memory and a data storage memory, wherein the address storage memory has the interruption data area for each entry. Microprocessor with unit. 2. The built-in cache memory unit of claim 1, wherein the cache memory of the cache memory unit includes an address storage memory and a data storage memory, wherein the data storage memory has the interruption data area for each entry. Microprocessor with. 2. The cache memory unit of claim 1, wherein the cache memory unit has a selection device for selecting an entry required for replacement by hysteretic data of each entry during a cache memory entry replacement time. Microprocessor. 2. The microprocessor of claim 1, wherein the cache memory has a data storage area that indicates whether an entry is valid or invalid for each entry.