JPS595931B2 - Address stop method for arithmetic processing system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an address stop method for an arithmetic processing system that arbitrarily stops the address of an arithmetic processing unit in an arithmetic processing system having an instruction prefetch circuit.

In order to improve processing performance, an arithmetic processing system includes an arithmetic processing unit, a bus control circuit that operates independently of the arithmetic processing unit, and an instruction prefetch circuit.

By the way, the arithmetic processing unit normally performs the following operations.

1 First, read the command word.

2. Decode the read instruction word.

3. Manipulate the address according to the contents of the decoded instruction word.

4. Output the contents of the address to a predetermined register, memory, or external device.

It operates by reading the tertiary command word.

By the way, in the above-mentioned arithmetic processing system, 2 to 4
During this operation, the external bus is not used, and the bus control circuit is operated during this period to output an address to the external bus, and an instruction to be executed by the arithmetic processing section in the future is preempted and stored in the instruction prefetch circuit. This allows the arithmetic processing unit to perform high-speed processing by using the prefetch instructions stored in the instruction prefetch circuit. However, such an arithmetic processing system requires the address where the arithmetic processing unit is executed,
Since the address used to access the external bus is different, it is not possible to determine which address the instruction is actually executed in the arithmetic processing unit.

Therefore, when you discover an error in a program and try to correct it by stopping the arithmetic processing unit at an arbitrary address, in the above system, the address output from the arithmetic processing unit to the external bus and the address you want to stop are A method is used to compare them and, when they match, send a stop signal to the arithmetic processing unit.

However, in an arithmetic processing unit that has an instruction prefetch circuit, the address output to the external bus is an address for entering the instruction prefetch circuit, and is earlier (or later) than the address currently being executed in the arithmetic processing unit. there is a possibility.

Therefore, if you compare the address that appears on the external bus with the address you want to stop at and send a stop signal to the arithmetic processing unit when they match, you will end up stopping at an address before the address you actually want to stop. It's getting old and inconvenient. Therefore, conventionally, as a means for stopping at an arbitrary address, there is a method in which the program itself monitors it. One method is to read out the command words of the monitored program (including the address you want to stop) word by word to the monitoring program, execute the command, check the address, and check whether it is the address you want to stop. It is. Another method is to rewrite the instruction word of the address of the monitored program to be stopped with a command to forcibly stop the program, and then stop the address.

However, the former method is slower than normal operation because it reads and processes each instruction word at a time, and the latter method cannot rewrite the instruction words if they are written in read-only memory. There are drawbacks.

The present invention has been made in view of the above circumstances, and includes:
By matching the stop addresses in advance with an external comparison circuit, storing a code in place of the command word in the address output circuit, and executing the stop command when the stop address is reached in the process of arithmetic processing, the conventional The present invention provides an address stop method for an arithmetic processing system that eliminates various inconveniences.

Embodiments of the present invention will be described below with reference to the drawings. In the figure, reference numeral 10 denotes a central processing unit for processing data according to addresses, and this is composed of an address output circuit 11, an instruction prefetch circuit 12, and a calculation unit 13. That is, this address output circuit 11 outputs an address signal for accessing an external memory, and the addresses output from this circuit are collectively held in an external latch circuit, which will be described later. The instruction prefetch circuit 12 automatically takes in address data from the address output circuit 11 when the data bus is not in use, so that it can be executed by the arithmetic unit 13 in the future. This arithmetic unit 13 performs arithmetic operations based on an instruction word that enters the instruction prefetch circuit 12 from the external data bus via the address output circuit 11. 20 is an external bus control circuit.

This bus controller circuit 20 has a comparison circuit 21,
This compares the address of the address output circuit 11 latched by the address latch circuit 22 with the preset address of the stop address setting circuit 23 to determine whether the addresses match or do not match. 24 is an address decoder that takes in and decodes the address held in the address latch circuit 22 when the addresses do not match; 25 is a memory that outputs the data contents of a predetermined address to the data bus 26 in response to a signal from the address decoder 24; .

27 is a stop instruction code output circuit that outputs a stop instruction code to the data bus 26 in place of the address when the addresses match in the comparison circuit 21.

Next, a series of operations of the method of the present invention will be explained. First, when the bus of the arithmetic unit 13 is not used, the instruction prefetch circuit 12 takes in the instruction word at the address of the address output circuit 11 and sends it to the arithmetic unit 13.
create an executable state. Therefore, if the instruction word is stored in the instruction prefetch circuit 12, the arithmetic section 13 fetches it and executes the operation. When an address is output from the address output circuit 11, this address is collectively held in an external address latch circuit 22.

The address held by the address latch circuit 22 is input to a comparison circuit 21, which also contains an address from the stop address setting circuit 23. Therefore, the address of the latch circuit 22 and the preset stop address are compared in the comparison circuit 21, and if they do not match, the address held in the address latch circuit 22 is used to select and designate the memory 25 via the address decoder 24. As a result,
When data is output from the selected memory 25, this data is stored in the instruction prefetch circuit 12 via the data bus 26 and the address output circuit 11.

On the other hand, when the address output from the address output circuit 11 matches the address of the stop address setting circuit 23 in the comparison circuit 21, a stop command is issued from the stop command code output circuit 27 instead of the contents of the address specified from the address output circuit 11. Output the code.

Therefore, in this case as well, the stop instruction code is taken into the instruction prefetch circuit 12 via the data bus 26 and the address output circuit 11. The arithmetic unit 13 sequentially processes the contents entered in the instruction prefetch circuit 12, and when the stop address is reached, the process stops by executing the stop instruction.

In this way, when the stop addresses match externally, instead of sending a stop signal to the central processing unit 10 to stop it at that point, by changing the command word and reading it into the command prefetch circuit when they match, Even a central processing unit having an instruction prefetch circuit can be reliably stopped at a specified address.

Note that a "zip-up command" may be used instead of the stop command described in the above embodiment.

At this time, if the specified address is reached, it is possible to jump to any program address. Furthermore, if the central processing unit 10 determines whether the address is input from the central processing unit 10 to the instruction prefetch circuit 12 or the address is intended for processing by the arithmetic unit 13,
As for what is input into the instruction prefetch circuit, the address can be stopped using the above-mentioned method, and when a match is found in the target address of the arithmetic unit 13, the address can be stopped by directly sending a stop signal. As described in detail above, according to the present invention, when a stop address matches externally, a stop signal is not sent to the arithmetic processing unit to stop it, but when a match occurs, the instruction word is changed and stored in the instruction prefetch circuit, and the operation is executed. The stop command is executed when the stop address is reached in the process of processing the contents of the instruction prefetch circuit.
A central processing unit with an instruction prefetch circuit can reliably stop at a specified address.

[Brief explanation of the drawing]

The figure is a block diagram showing an embodiment to which the address stop method of the arithmetic processing system according to the present invention is applied. 10...Central processing unit, 11...Address output circuit, 12...Instruction prefetch circuit, 1
3...゜゜operating section, 30...bus control circuit, 21...comparison circuit, 22...
・Address latch circuit, 23...Stop address setting circuit, 24...Address decoder, 25.
...Memory, 26...Data bus, 27
...Stop command code output circuit.

Claims (1)

[Claims] 1. In an arithmetic processing system in which an instruction prefetch circuit fetches the address of an address output circuit and performs arithmetic operations, the designated address of the address output circuit is compared with a preset stop address of a stop address setting circuit, and the difference between the two addresses is determined. When the memory is selected at the designated address and data from the memory is input to the instruction prefetch circuit, and when both addresses match, a stop instruction code is output to the instruction prefetch circuit in place of the data from the memory indicated by the address. An address stop method for an arithmetic processing system that stops when a stop command code is reached in the process of arithmetic processing.