JP3024719B2 - Arithmetic processing method of programmable controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a central processing unit (C)
The present invention relates to an arithmetic processing method of a programmable controller in which a sequence instruction is executed by two processors, a PU and a bit operation processor (BP).

[0002]

2. Description of the Related Art Conventionally, in a programmable controller that automatically controls an electronic device by executing a sequence program, a bit operation processor (hereinafter, referred to as a BP) that performs a bit operation in a sequence instruction in order to realize a high-speed operation process. ) And a central processing unit (CPU) for executing a sequence instruction other than a bit operation (hereinafter, this instruction is referred to as an application instruction). As a bit operation, a logical operation of bit information such as AND and OR, and read / write of bit information are mainly performed. In a programmable controller, a BP is used for a logical operation of contact information and input / output processing. The application instruction is an instruction for instructing the execution of a numerical operation other than the bit value or various information processing.

[0003] The BP determines whether or not the sequence instruction read from the user memory can be executed by its own BP. If the sequence instruction cannot be executed by the BP, the execution right of the sequence instruction is determined by the CPU. Handed over to When receiving the execution right of the sequence instruction, the CPU executes an actual operation process corresponding to the type content of the sequence instruction. More specifically, for each type of sequence instruction, detailed program information that prescribes arithmetic processing corresponding to the instruction is stored in the system program memory in advance. To identify or calculate the read start address. Next, the program information is read out using the calculated head address, and the operation is executed.

In connection with the execution of the operation, information indicated by an operand portion (storage address of a parameter value used in the operation) in the sequence instruction is read from various memories. CPU
When the CPU executes the application instruction, the CPU transfers the execution right of the sequence instruction to the BP. The BP to which the execution right has been transferred performs the same processing as described above for the next sequence instruction. In this way, the BP and the CPU execute the sequence command in the sequence program according to the type of the sequence command.

[0005]

As described above, the processing speed of the programmable controller has been improved, but further high-speed processing is desired.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an arithmetic processing method of a programmable controller which can increase the speed of executing a sequence program of the programmable controller in view of the above points.

[0007]

In order to achieve the above object, according to the first aspect of the present invention, a first processor executes a bit operation instruction in a sequence instruction described in a sequence program, The second processor executes an application instruction other than the bit operation instruction, the first processor identifies a type of a sequence instruction, and determines a processor to execute the sequence instruction. For each type of sequence instruction executed by the second processor, program information indicating the processing content indicated by the sequence instruction is stored in a memory in advance, and when the first processor identifies the sequence instruction, The type identification of the application instruction is also executed, and the program information stored in the memory corresponding to the identification result is also executed. With hand over of the storage address to the second processor, the first processor is the
When the type of application instruction is identified,
From the target sequence instruction, the second processor
Fetch the operand information used to execute the
Is delivered to the processor .

[0008]

[0009]

According to the present invention, conventionally, a BP (first processor) identifies a sequence instruction to select a processor to execute the sequence instruction, and a CPU (second processor) stores program information corresponding to the sequence instruction. Focusing on identifying (or calculating) a sequence instruction for determining the storage address of the first processor, the present invention utilizes the identification processing of the first processor to store the program storage address and operand information required by the second processor. From the first processor to the second processor.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a circuit configuration of a programmable controller to which the present invention is applied.

In FIG. 1, a CPU 10 includes a system RO
In addition to controlling the operation of the entire apparatus in accordance with a system program stored in an M (read only memory) 30, the system executes an application instruction in a sequence program of a user RAM (random access memory) 50 during system operation.

The CPU 10 is provided with a program counter 10A for designating a read address of the user RAM 50. From the address indicated by the program counter 10A, a sequence instruction is sent to the CPU 10 or the BP.
20 and sent out on the bus. CPU10
The BP 20 and the BP 20 are connected to signal lines other than the bus, and an operation timing signal and an information signal according to the present invention are exchanged via the signal lines.

The BP 20 uses a processor that can read / write data from and to a memory and performs a bit-wise operation. BP
A sequence instruction-address conversion circuit 20A and an operand information generation circuit 20B according to the present invention are provided in the block 20.

Sequence instruction-address conversion circuit 20A
Is a circuit for calculating the head storage address of a detailed program for a sequence instruction by hardware, which has conventionally been performed by the CPU by software processing. The following processing is executed using a shift register or the like as an example of the circuit.
That is, a plurality of bits representing an instruction code in a sequence instruction are masked by shift processing, and a specific address in the masked bit information is extracted to create a read address.

FIG. 2 shows a circuit configuration of the operand information creating circuit 20B. In FIG. 2, a decoder 101 performs signal identification to determine whether a BP should be executed by a read sequence instruction as in the related art. When the decoder 101 detects a BP non-executable sequence instruction (application instruction) as a process related to the present invention, the decoder 101 generates a control signal for storing an operand portion in the sequence instruction in the register 102. The operand stored in the register 102 is passed to the CPU 10 as information necessary for the CPU 10 to execute the application instruction.

Referring back to FIG. 1, the system ROM 30 stores C
A system program that defines system processing executed by the PU 10 is stored. The difference from the conventional system ROM is that the system ROM 30 of the present embodiment does not describe a detailed program of a sequence instruction (application instruction), but describes it on the system RAM 40.

The system RAM 40 is readable / writable, and stores data used for arithmetic processing of the CPU 10 as a work memory. The storage area according to the present invention includes:
For each type of sequence instruction executed on the CPU side, an area (hereinafter referred to as a jump table) 40A for storing a detailed program, that is, a program executed by the CPU 10 is provided. Further, an area (referred to as a jump destination designation register) 40B for storing an address (jump destination designation information) to be actually accessed (read) by the CPU in the jump table is also provided.

The contents of the jump table 40A are written into the CPU 10 during initialization processing such as when power is turned on.
The contents of the jump destination designation register 40B are written by the BP 20 during system operation.

The user RAM 50 stores a sequence program for controlling an electronic device input from a programming device (not shown).

The execution processing of a sequence instruction in such a circuit will be described with reference to FIGS. FIG. 3 is a flowchart showing a hardware processing procedure executed by the BP 20, and FIG. 4 is a flowchart showing a software processing procedure executed by the CPU 10.

When the power is turned on, the content to be described in the jump table is stored in the CPU 10 from a predetermined memory such as an external storage device such as a memory cassette or an internal memory.
And written into the jump table 40A (step T10 in FIG. 4). CP according to system startup
U10 sets the start address of the sequence program in the program counter 10A, and activates the BP 20 (step T11 in FIG. 4).

The BP 20 that has received the activation instruction (step S10 in FIG. 3) reads a sequence instruction from the user RAM 50 address indicated by the program counter 10A, and determines whether the read sequence instruction can be executed by the BP 20. (Step S1 in FIG. 3)
2). If a determination of execution is obtained, B
The bit operation indicated by the sequence instruction is executed in P20 (steps S20 → S21 in FIG. 3).

Thereafter, the BP 20 updates the value of the program counter 10A in the CPU 10 to an address value to be read next (step S22 in FIG. 3).

While the BP 20 is executing the bit operation processing, the CPU 10
The writing of P20 is monitored, and internal processing such as system processing is performed (steps T13 → T14 → T21 → T1 in FIG. 4).
3 loop processing).

On the other hand, if the sequence instruction read by BP 20 is, for example, an application instruction relating to an addition process, if it is determined in step S12 of FIG. 3 that the BP 20 cannot be processed, the sequence instruction-address conversion circuit 20A in BP 20 Creates the jump destination address of the CPU 10, and writes the jump destination address to the jump destination designation register 40B in the system RAM 40 by the read / write function of the BP 20 (steps S31 → S4 in FIG. 3).
1).

The operand in the sequence instruction is set in the register 102 of FIG. 2, and this operand information is transferred to the CPU 10 (step S4 of FIG. 3).
2). In this way, the BP 20 sends the operand information to the CPU 10 at the same time as writing the jump destination address of the CPU 10 to the register 40B. After this, BP2
If the value is 0, the program counter in the CPU 10 is advanced and stopped (step S44).

When the CPU 10 detects the writing to the jump destination specifying register 40B on the CPU 10 side, the CPU 10 reads the content of the jump destination specifying register 40B (step T13 in FIG. 4), and reads the read content, that is, the jump in the jump table 40A. The processing jumps to a destination address, in this example, an address for storing a detailed program related to the addition processing. Thereafter, the CPU 10 reads this detailed program from the jump table 40A, reads the addend from the memory based on the operand information sent from the BP 20, and performs an addition process (steps T31 to T32 in FIG. 4). After completing the addition processing in the application instruction, the CPU 10 sets the BP 20
To restart. In response to the restart instruction, the BP 20 executes the above-described determination processing for the next new sequence instruction and the sequence bit operation processing or the application instruction related processing.

As described above, in this embodiment, BP2
When determining the execution processor on the 0 side, for the application instruction, the jump destination address of the CPU 10 and the operand information necessary for the operation are created by hardware.

For this reason, as compared with the conventional case where a plurality of steps are performed on the CPU side to calculate the jump destination address and the operand information by software, the CPU on the BP side
In this embodiment, which is created by hardware in parallel with the above processing, the processing time is shortened.

In addition, as the number of sequence application instructions increases, the processing time of the entire sequence program is greatly reduced.

The following example can be realized in addition to the present embodiment.

1) In this embodiment, the CPU 10 monitors the writing of the BP 20 into the jump destination designation register 40B.
The CPU 10 may read the jump destination designation register 40B when the data is received by the side. When this stop instruction is given to the CPU 10 by an interrupt instruction, C
It is also possible to monitor the change of the jump destination designation register in the interrupt processing on the PU 10 side. However, in this case,
Push and pop processing of a register in the CPU 10 is required as in the related art.

2) In this embodiment, a jump table of 4 bytes per sequence instruction is assumed. However, the present invention is not limited to this, and the jump table can have a desired number of bytes.

3) Storing the jump table in the rewritable memory (RAM) as in this embodiment has the following advantages.

A) A sequence command desired by a user can be selected for a sequence command to be provided to a user.
The capacity of the system ROM can be reduced, which can contribute to a reduction in manufacturing cost.

B) If a detailed program is stored in a memory cassette or the like for storing a sequence program and transferred to the system RAM when the system is started, the user can create a desired sequence command using a programming device.

4) The following types of program information are described in the jump table.

A) When a sequence instruction is composed of only an instruction code without operand information in a sequence instruction such as a function instruction, the bit operation processor determines only the address of the jump destination table according to the identification result of the decoder. (Corresponding to the invention of claim 1).

B) In addition, if the sequence instruction contains operand information, for example, the storage address of the data to be operated, etc., the operand information is fetched and delivered based on the identification result of the decoder as in this embodiment. (Corresponding to the invention of claim 2).

[0041]

As described above, according to the present invention, by using the identification processing on the first processor (BP) side, the storage address of the program information required for the application instruction on the second processor (CPU) side, and the like. Prepare operand information. As a result, a part of the processing conventionally performed in time series by the second processor is performed in parallel on the BP side, so that the processing time of the sequence instruction is shortened as compared with the related art.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a system configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of an operand information creation circuit 20B of FIG.

FIG. 3 is a flowchart illustrating a processing procedure executed by a BP 20 of FIG. 1;

FIG. 4 is a flowchart illustrating a processing procedure executed by a CPU 10 of FIG. 1;

[Explanation of symbols]

 10 CPU 10A Program counter (PC) 20-bit arithmetic processor (BP) 20A Sequence instruction-address conversion circuit 20B Operand information creation circuit 30 System ROM 40 System RAM 40A Jump table 40B Jump destination designation register 50 User RAM

Claims (1)

(57) [Claims] 1. A first processor executes a bit operation instruction among sequence instructions described in a sequence program, and a second processor executes application instructions other than the bit operation instruction. Is determined by the first processor, and a processing method of the programmable controller that determines a processor to execute the sequence instruction. The processing content indicated by the sequence instruction is determined for each type of the sequence instruction executed by the second processor. Program information to be stored in a memory in advance, and when the first processor identifies the sequence instruction, the first processor also executes type identification of the application instruction, and stores the program information in the memory in accordance with the identification result. the storage address of the program information stored with delivery to the second processor, the first The first processor has a kind knowledge about the application instruction.
If another is performed, the sequence
From the instruction, the operand used to execute the second processor
Computer program information which is extracted and passed to the second processor .