JPH05341820A - Arithmetic processing method for programmable controller - Google Patents

Abstract

PURPOSE:To shorten the processing time of a sequence instruction by preparing the operand information as well as the storing address of the program information necessary for the applied instruction of a 2nd processor through the identification processing of a 1st processor. CONSTITUTION:The bit arithmetic instruction described in a sequence program is carried out by a bit processor 20, and other applied instructions are carried out by a CPU 10. The type of the sequence program is identified by the processor 20 and an executing processor is decided. The processor 20 also identifies the types of the applied instructions together with identification of the type of the sequence instruction. Then the processor 20 produces a jumping destination address of the CPU 10 through a sequence instruction/address converter 20A with an instruction that cannot be executed by the processor 20. This jumping destination address is written in a jumping destination designating register 40B. At the same time, the operand information is sent to the CPU 10. The CPU 10 reads a detailed program out of a jump table 40A based on those information and carries it out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a central processing unit (C
The present invention relates to an arithmetic processing method of a programmable controller in which a sequence instruction is executed by two processors, a PU) and a bit arithmetic processor (BP).

[0002]

2. Description of the Related Art Conventionally, in a programmable controller for automatically controlling electronic equipment by executing a sequence program, in order to realize high-speed arithmetic processing, a bit arithmetic processor (hereinafter, BP) for performing bit arithmetic in sequence instructions. And a central processing unit (CPU) for executing sequence instructions other than bit operations (hereinafter, these instructions are referred to as application instructions). The bit operation mainly performs logical operation of bit information such as AND and OR and read / write of bit information, and the programmable controller uses BP for logical operation of contact information and input / output processing. In addition, the application instruction is an instruction for instructing execution of numerical operations other than bit values and various information processing.

The BP determines whether or not the sequence instruction read from the user memory can be executed by its own BP. If the sequence instruction cannot be executed by the BP, the execution right of the sequence instruction is determined by the CPU. Be delivered to. When the CPU receives the right to execute the sequence instruction, the CPU executes the actual arithmetic processing corresponding to the type content of the sequence instruction. More specifically, for each type of sequence instruction, detailed program information that defines the arithmetic processing corresponding to the instruction is stored in advance in the system program memory, so that the CPU determines from the instruction code of the sequence instruction to the system program memory. The read start address of is identified or calculated. Next, the program information is read out by using the calculated start address and calculation is executed.

In connection with the execution of this operation, the information indicated by the operand portion (storage address of the parameter value used in the operation) in the sequence instruction is read from various memories. CPU
When the application instruction is executed on the side, the CPU hands over the execution right of the sequence instruction to the BP. The BP to which the execution right has been handed over performs the same processing as described above for the next sequence instruction. In this way, the BP and the CPU execute the sequence command in the sequence program in accordance with the type of the sequence command.

[0005]

In this way, the processing speed of the programmable controller has been improved, but much higher speed processing is desired.

Therefore, in view of the above points, an object of the present invention is to provide an arithmetic processing method of a programmable controller capable of further increasing the sequence program execution speed of the programmable controller.

[0007]

In order to achieve such an object, the invention of claim 1 is such that a first processor executes a bit operation instruction in a sequence instruction described in a sequence program, In the arithmetic processing method of a programmable controller, the second processor executes an application instruction other than the bit operation instruction, the type of the sequence instruction is identified by the first processor, and the processor that executes the sequence instruction is determined. The program information indicating the processing content of the sequence instruction for each type of the sequence instruction executed by the second processor is stored in advance in the memory, and the application is performed when the first processor identifies the sequence instruction. The type identification of the instruction is also executed, and the program information stored in the memory is associated with the identification result. Wherein the hand over paid address to the second processor.

According to a second aspect of the present invention, when the first processor identifies the type of the application instruction,
It is characterized in that the operand information used for the execution of the second processor is extracted from the sequence instruction which is the object of identification and is passed to the second processor.

[0009]

According to the present invention, conventionally, the BP (first processor) identifies the sequence instruction for the selection of the processor that executes the sequence instruction, and the CPU (second processor) program information corresponding to the sequence instruction. Paying attention to the point of identifying (or calculating) the sequence instruction for determining the storage address of the program, the present invention utilizes the identification process of the first processor to utilize the program storage address and operand information required by the second processor. Is transferred from the first processor to the second processor.

[0010]

Embodiments of the present invention will now be described in detail with reference to the drawings.

FIG. 1 shows the circuit configuration of a programmable controller to which the present invention is applied.

In FIG. 1, the CPU 10 is a system RO.
In addition to controlling the operation of the entire apparatus in accordance with a system program stored in M (read only memory) 30, application instructions in the sequence program of user RAM (random access memory) 50 are arithmetically executed during system operation.

A program counter 10A for designating a read address of the user RAM 50 is provided in the CPU 10, and a sequence command is issued from the address designated by the program counter 10A to the CPU 10 or BP.
It is read by 20 and sent out on the bus. CPU10
And BP20 are connected to signal lines other than the bus, and operation timing signals and information signals relating to the present invention are exchanged via these signal lines.

The BP 20 is readable / writable with respect to the memory and uses a processor which performs bit-by-bit arithmetic. BP
Within 20 is provided a sequence instruction-address conversion circuit 20A and an operand information creation circuit 20B according to the present invention.

Sequence instruction-address conversion circuit 20A
Is a circuit for performing, by hardware, calculation processing of a head storage address of a detailed program for a sequence instruction, which is conventionally performed by software by the CPU. As an example of the circuit, a shift register or the like is used to execute the following processing.
That is, a read address is created by masking a plurality of bits representing an instruction code in a sequence instruction by shift processing and extracting a specific bit from the masked bit information.

The circuit configuration of the operand information creating circuit 20B is shown in FIG. In FIG. 2, the decoder 101 performs signal identification for determining whether or not the read sequence instruction should be executed by the BP as in the conventional case. In addition, when the BP non-execution sequence instruction (application instruction) is detected, the decoder 101 also generates a control signal for storing the operand portion of the sequence instruction in the register 102, as a process related to the present invention. The operand stored in the register 102 is delivered to the CPU 10 as information necessary for executing the application instruction of the CPU 10.

Returning to FIG. 1, the system ROM 30 stores C
A system program that defines the system processing executed by the PU 10 is stored. The point different from the conventional system ROM is that the detailed program of the sequence instruction (application instruction) is not written in the system ROM 30 of this embodiment, but is written in the system RAM 40.

The system RAM 40 is readable / writable and stores data used for arithmetic processing of the CPU 10 as a work memory. As the storage area related to the present invention,
An area (hereinafter, referred to as a jump table) 40A for storing a detailed program, that is, a program executed and executed by the CPU 10, is provided for each type of sequence instruction executed on the CPU side. Further, an area (referred to as a jump destination designation register) 40B for storing an address (jump destination designation information) to be actually accessed (read) by the CPU in this jump table is also provided.

The contents of the jump table 40A are written in the CPU 10 in the initialization processing such as when the power is turned on,
The contents of the jump destination designation register 40B are written by the BP 20 during system operation.

The user RAM 50 stores a sequence program for controlling electronic equipment, which is input from a programming device (not shown).

The sequence instruction execution process in such a circuit will be described with reference to FIGS. 3 is a flowchart showing a hardware processing procedure executed by the BP 20, and FIG. 4 is a flowchart showing a software processing procedure executed by the CPU 10.

When the power is turned on, the contents to be written in the jump table are stored in the CPU 10 from an external storage device such as a memory cassette or an internal memory, which is a predetermined memory.
Is read out and written in the jump table 40A (step T10 in FIG. 4). CP depending on system startup
U10 sets the top read address of the sequence program in the program counter 10A and activates the BP 20 (step T11 in FIG. 4).

The BP 20 which has received this start-up instruction (step S10 in FIG. 3) reads a sequence instruction from the user RAM 50 address indicated by the program counter 10A, and determines whether or not the read sequence instruction can be executed by the BP 20. (Step S1 of FIG. 3)
2). If it is determined that execution is possible, B
The bit operation designated by the sequence instruction is executed in P20 (steps S20 → S21 in FIG. 3).

After that, the BP 20 updates the value of the program counter 10A in the CPU 10 to the address value to be read next (step S22 in FIG. 3).

While the BP 20 is executing the bit operation processing, the CPU 10 sends B to the jump destination designation register.
The writing of P20 is monitored and internal processing such as system processing is performed (steps T13 → T14 → T21 → T1 in FIG. 4).
3 loop processing).

On the other hand, if the sequence instruction read by the BP 20 is an application instruction relating to addition processing, for example, if it is determined in step S12 in FIG. 3 that the BP 20 cannot be processed, the sequence instruction-address conversion circuit 20A in the BP 20 is obtained. The jump destination address of the CPU 10 is created by this, and the jump destination address is written in the jump destination designation register 40B in the system RAM 40 by the read / write function of the BP 20 (steps S31 → S4 in FIG. 3).
1).

The operand in the sequence instruction is set in the register 102 of FIG. 2 and the operand information is delivered to the CPU 10 (step S4 of FIG. 3).
2). In this way, the BP 20 writes the jump destination address of the CPU 10 to the register 40B and sends the operand information to the CPU 10 at the same time. After this, BP2
0 advances the program counter in the CPU 10 and stops it (step S44).

When the CPU 10 detects writing to the jump destination designation register 40B, the CPU 10 reads the contents of the jump destination designation register 40B (step T13 in FIG. 4), and the read contents, that is, the jump in the jump table 40A. It jumps to the destination address, in this example, the address that stores the detailed program related to the addition process. Thereafter, the CPU 10 reads this detailed program from the jump table 40A, reads the addend from the memory based on the operand information sent from the BP 20, and performs addition processing (steps T31 to T32 in FIG. 4). After the addition processing in the application instruction is completed, the CPU 10 causes the BP 20
To reboot. In response to the restart instruction, the BP 20 executes the above-mentioned discrimination processing for the next new sequence instruction and the sequence bit operation processing or application instruction related processing.

As described above, in this embodiment, BP2
When determining the execution processor on the 0 side, the jump destination address of the CPU 10 and the operand information necessary for the operation are created by hardware for the application instruction.

Therefore, the CPU on the BP side is different from the conventional case in which the jump destination address and operand information are calculated by software by taking a plurality of steps on the CPU side.
The processing time is shortened in the present embodiment in which the processing is performed by hardware in parallel with the above processing.

In addition, as the number of sequence application instructions increases, the processing time of the entire sequence program is greatly shortened.

In addition to this embodiment, the following example can be realized.

1) In this embodiment, the CPU 10 monitors the writing to the jump destination designation register 40B of the BP 20, but the CPU 10 issues the stop instruction of the BP 20.
The CPU 10 may read out to the jump destination designation register 40B when the side receives. In addition, when issuing this stop instruction to the CPU 10 as an interrupt instruction, C
It is also possible to monitor whether or not the jump destination designation register has been changed in the interrupt processing on the PU 10 side. However, in this case,
As in the conventional case, the push and pop processing of the register in the CPU 10 is required.

2) In this embodiment, a jump table of 4 bytes per sequence instruction is assumed, but the jump table is not limited to this, and the jump table can have a desired number of bytes.

3) By storing the jump table in the rewritable memory (RAM) as in this embodiment, there are the following advantages.

A) Regarding the sequence command provided to the user, the user can select the sequence command desired by the user,
It is possible to reduce the capacity of the system ROM and contribute to a reduction in manufacturing cost.

B) By storing the detailed program in a memory cassette for storing a sequence program and transferring it to the system RAM when the system is started up, the user can also create a desired sequence command using the programming device.

4) The program information described in the jump table has the following types.

A) When there is no operand information in the sequence instruction and the sequence instruction is composed of only the instruction code like the function instruction, the bit arithmetic processor only makes the address of the jump destination table correspond to the identification result of the decoder. (Corresponding to the invention of claim 1).

B) In addition, when the sequence instruction includes operand information, for example, the storage address of the data to be operated, the operand information is taken out and passed based on the identification result of the decoder as in the present embodiment. Is performed by the BP (corresponding to the invention of claim 2).

[0041]

As described above, according to the present invention, by using the identification processing on the first processor (BP) side, the storage address of the program information necessary for the application instruction on the second processor (CPU) side and Prepare operand information. As a result, a part of the processing conventionally performed by the second processor in time series is processed in parallel on the BP side, so that the processing time of the sequence instruction is shortened as compared with the conventional technology.

[Brief description of drawings]

FIG. 1 is a block diagram showing a system configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of an operand information creation circuit 20B of FIG.

FIG. 3 is a flowchart showing a processing procedure executed by the BP 20 of FIG.

FIG. 4 is a flowchart showing a processing procedure executed by a CPU 10 of FIG.

[Explanation of Codes] 10 CPU 10A Program Counter (PC) 20-bit Arithmetic Processor (BP) 20A Sequence Instruction-Address Conversion Circuit 20B Operand Information Creation Circuit 30 System ROM 40 System RAM 40A Jump Table 40B Jump Destination Specification Register 50 User RAM

Claims (2)

[Claims] 1. A type of sequence instruction in which a first processor executes a bit operation instruction among sequence instructions described in a sequence program and an application instruction other than the bit operation instruction is executed by a second processor. In the arithmetic processing method of the programmable controller for determining the processor that executes the sequence instruction by identifying the processing content indicated by the sequence instruction for each type of the sequence instruction executed by the second processor. The program information shown in the memory is stored in advance in the memory, and when the first processor identifies the sequence instruction, the first processor also performs type identification for the application instruction, and stores in the memory in association with the identification result. The storage address of the program information in the storage is transferred to the second processor. Programmable controller processing method. 2. When the first processor identifies the type of the application instruction, it extracts the operand information used for the execution of the second processor from the sequence instruction that is the subject of identification, and The arithmetic processing method of the programmable controller according to claim 1, wherein the arithmetic processing is delivered to the second processor.