JP3441262B2 - Data processing device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for executing data processing by executing a program consisting of variable word length instructions.

[0002]

2. Description of the Related Art Conventionally, in a data processing device that handles a variable word length instruction (hereinafter, referred to as a "variable word length instruction"), an operation code part of a constant length constituting a variable word length instruction and a number of words Different address parts are stored at consecutive addresses in the program memory, and the processor sequentially reads the operation code part and the address part forming the variable word length instruction according to the address and executes the operation.

By the way, in such a data processing device that executes a variable word length instruction, if the execution condition is not satisfied for some reason and the operation is skipped, the processor executes the instruction until the beginning of the next instruction to be read. It couldn't be executed and effectively stopped executing the operation.

Therefore, in a data processing device that handles such variable word length instructions, when skipping instruction operations,
The challenge is how to read the beginning of the next instruction to be executed at high speed. Conventionally, for example, the instruction operation is skipped by the method shown in (1) to (3) below and the next instruction to be executed is I was trying to read at high speed.

(1) As shown in FIG. 7, the head word of each instruction stored in the program memory PM is provided with a recognition bit D1 indicating whether or not it is the head of the instruction. How to recognize and skip to the beginning of the next instruction.

(2) As shown in FIG. 8, when a table T indicating the instruction word length for each instruction stored in the program memory PM is provided in another area and a certain instruction is skipped, A method to skip to the beginning of the next instruction by reading the word length of that instruction from the table and adding it to the program counter.

(3) As shown in FIG. 9, the word length data D2 of the instruction is stored in the head word (usually the operation code part) of each instruction stored in the program memory PM,
A method for reading the next instruction by skipping the word length based on the word length data D2.

[0008]

However, in the conventional method (1), when skipping up to the first word of the instruction to be executed next, the operation code part and address part of the instruction being skipped are all read. Since it had to be done, it took a long time to read an instruction on the way, and there was a problem that the efficiency was low.

Further, in the conventional method (2), the number of skips to the beginning of the next instruction is calculated by reading the data in the table indicating the word length of the instruction word. There is a problem in that it is necessary to calculate the table address corresponding to the instruction and read the table data, which requires time.

Further, in the conventional method (3), since the number of words of the instruction word is incorporated at the head of the operation code portion, the number of information bits in one word is reduced as the operation code portion, and it has been used conventionally. There has been a problem that such an information bit cannot be newly added to the received instruction word.

As described above, in the conventional methods (1) to (3), it is impossible to determine the skip number of each instruction without reading the operation code part at the head of each instruction. In the conventional methods of) to (3), it is not possible to determine whether to execute or skip the instruction without reading the opcode part at the beginning of each instruction. However, there is a problem that it is necessary to read all the command heads of the respective commands to be skipped, and it takes time to read the command heads of the respective commands to be skipped.

Therefore, the present invention has been made by paying attention to such a problem. Even when a large number of instructions to be skipped in a program consisting of variable word length instructions, they are skipped at high speed to execute instructions. It is an object of the present invention to provide a data processing device capable of

[0013]

In order to achieve the above object, the invention according to claim 1 executes a program consisting of a variable word length instruction composed of an operation code part and an address part having a different number of words depending on an instruction. In a data processing device for performing data processing by means of a program, a program storage means for storing the program by storing an opcode part and an address part forming a variable word length instruction at consecutive addresses for each opcode part and the address part; The label storage means stores a plurality of labels set corresponding to the opcode part and the address part of the variable word length instruction stored in the storage means at the same address, and a plurality of labels are stored at the same address in the label storage means. Labels are read out at the same time by one access, and a plurality of labels are referred to to read the program storage means. Characterized by comprising an instruction execution unit for executing variable word length instruction reads, the.

According to a second aspect of the present invention, in the data processing apparatus according to the first aspect, the label storage means has an instruction head indicating whether or not the operation code portion and the address portion forming the variable word length instruction are the instruction head. It is characterized in that a label consisting of information and an execution condition indicating whether or not an operation code part and an address part forming a variable word length instruction are to execute an operation is stored.

According to a third aspect of the present invention, in the data processing apparatus according to the second aspect, the instruction executing means reads the variable word length instruction from the program storing means with reference to a plurality of labels and executes it once. It is judged whether or not there is a label indicating the instruction head based on the instruction head information among the labels read out simultaneously by the access. If there is no label indicating the instruction head, the label storage means stores the next label. If there is a label that indicates the beginning of an instruction while reading multiple labels stored at the address of, the execution condition of that label is subsequently determined, and if the execution condition indicates that the operation is executed The corresponding opcode part or address part is read from the program storage means and executed, and if no operation execution is indicated, the corresponding opcode part or address part is replaced by the program. Skip without issuing read from the storage means, characterized in that.

According to a fourth aspect of the present invention, in the data processing apparatus according to the second aspect, the instruction execution means sets the operation result when the basic instruction is executed, and the setting is set in the basic instruction. It has a power flow register used to judge the execution condition of the subsequent application instruction, and the program storage means stores the program consisting of the basic instruction and the variable word length instruction of the application instruction, while the label storage means is the instruction head. A label consisting of information and an execution condition indicating whether or not an operation code part and an address part forming a variable word length instruction are executed based on the setting of the power flow register is stored, and the instruction execution is performed. The means simultaneously reads a plurality of labels stored at the same address of the label storage means with one access, and refers to the plurality of labels to refer to the label. Performs program execution processing to be executed from gram storage means reads a variable word length instruction cyclically, characterized in that.

According to a fifth aspect of the present invention, in the data processing apparatus according to the fourth aspect, the instruction executing means reads the variable word length instruction from the program storing means with reference to a plurality of labels and executes it once. It is judged whether or not there is a label indicating the instruction head based on the instruction head information among the labels read out simultaneously by the access. If there is no label indicating the instruction head, the label storage means stores the next label. While reading multiple labels stored at the address of the label, if there is a label indicating the beginning of the instruction, then the execution condition of that label is judged based on the setting of the power flow register, and the execution condition is If the operation execution is indicated based on the setting of the flow register, the corresponding opcode part or address part is read from the program storage means and executed, and the power flag is read. Skip corresponding operation code or the address unit unless represents an operation performed based on the setting of the over register without issuing read from said program storage means, characterized in that.

Therefore, in the inventions according to claims 1 to 5 configured as described above, the program storage means continuously operates the opcode part and the address part forming the variable word length instruction for each of the opcode part and the address part. The label storage means stores a plurality of labels set corresponding to each of the opcode part and the address part of the variable word length instruction at the same address. , A plurality of labels stored at the same address of the label storage means are read simultaneously by one access, and the variable word length instruction is read from the program storage means and executed by referring to the plurality of labels read at the same time.

[0019]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a data processing apparatus according to the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a programmable controller which is an embodiment of the data processing device according to the present invention.

As shown in the figure, this programmable controller includes a processor 11, a system memory 12 in which a system program is stored, a work memory 13 used as a work area of the processor 11, a user program memory 14, and data. A memory 15 and an input / output (I / O) interface 16 are connected to each other via an internal bus 17 composed of an address bus and a data bus.

The processor 11 executes the system program stored in the system memory 12 to
What is called input / output processing, program execution processing, peripheral service processing, etc. are cyclically performed, and function as instruction execution means during the program execution processing, which will be described later.
According to the procedure shown in (1), each variable word length instruction such as a ladder language which constitutes the user program stored in the user program memory 14 is read or skipped to execute the operation.

As shown in the figure, the processor 11 has a power flow register 11a built therein.

The power flow register 11a is "LOA
When a basic instruction such as "D", "AND" or "OR" is executed, the operation result is set by 1 bit, and the application instruction following the basic instruction is calculated in the user program based on the setting. It is used for determining whether to execute or does not execute an operation, and is peculiar to a programmable controller that cyclically executes program execution processing and the like.

The user program memory 14 is a program storage means for storing in advance a user program in which various variable word length instructions such as the ladder language consisting of the basic instructions and the application instructions are programmed according to user settings.

The data memory 15 stores input / output (I / O) data, and also includes an opcode part and an address part of each variable word length instruction constituting a user program stored in the user program memory 14 as label storage means. Labels, which will be described later, are stored for each instruction component.

FIG. 2 shows a method of storing a variable word length instruction constituting a user program in the user program memory 14.

The user program memory 14 stores each variable word length instruction constituting the user program at consecutive addresses for each instruction constituent element of the operation code portion and address portion constituting the instruction.

Specifically, the user program memory 14
Then, as shown in the figure, for example, variable word length instructions (referred to as "instructions" in the figure) 1 to 4 are stored in consecutive addresses "XX1 to XX7" for each instruction constituent element. Cage,
The variable word length instruction 1 is stored only in one address "XXX1" because it consists of only the head word of the opcode part, and the variable word length instruction 2 is stored in the top word of the opcode part and two address parts. It consists of three consecutive addresses "XXXXX2"
~ ××× 4 ”and the variable word length instruction 3 is stored in two consecutive addresses“ ××× 5 to xx × 6 ”because it consists of the first word of the operation code part and one address part. However, the variable word length instruction 4 is stored only in one address "XXX7" because it consists of only the first word of the operation code part.

Labels 1 to 10 consisting of instruction head information and execution conditions, which will be described below, are provided for each instruction component of the opcode part and address part of each variable word length instruction 1 to 4 stored at each address. Is set.

FIG. 3 shows the contents of the label L set for each instruction constituent element of the operation code section and the address section constituting each variable word length instruction.

The label L is L0 to L3 as shown in the figure.
It consists of 4 bits, and the most significant 1 bit L3 is
This is instruction head information indicating whether or not the corresponding opcode part and address part are the head word of the command, and the lower 3 bits L2 to L0 perform arithmetic operation based on the value (PF) of the power flow register of the processor 11. It is an execution condition indicating whether or not.

Specifically, when the bit of L3 which is the instruction head information is "1", it is the instruction head, and when the bit of L3 is "0", it is not the instruction head.
Also, the lower 3 bits of L2 to L0, which are execution conditions, are
In the case of "000", the execution condition is shown that the calculation is always executed. In the case of "001", the calculation is executed when the value (PF) of the power flow register 11a is "1".
In the case of "010", the execution condition is such that the operation is executed when the value (PF) of the power flow register 11a is "0", and in the case of "111", the operation is not always executed.

FIG. 4 shows the program memory 14 shown in FIG.
7 shows a specific example of the contents of labels 1 to 7 for each instruction constituent element of each variable word length instruction stored in.

That is, as shown in the figure, the label 1 is "1".
000 "is set to indicate that the corresponding opcode part or address part always executes the operation at the head of the instruction. Labels 2 and 5 are set to" 1001 ", and the corresponding opcode part or address is set. It is shown that the part executes the operation when the value (PF) of the power flow register 11a is "1" at the head of the instruction.

Labels 3, 4, and 6 are set to "0000", indicating that the corresponding opcode part or address part is not the head of the instruction, and label 7 is "1".
010 "is set, which indicates that the corresponding operation code portion or address portion is to execute the operation when the value (PF) of the power flow register 11a is" 0 "at the head of the instruction.

FIG. 5 shows a label storage method in the data memory 15.

Although not shown in the figure, the data memory 15 stores input / output data in 16 bits. Therefore, as shown in the figure, a variable word length instruction The above-mentioned 4-bit label for each instruction constituent element is stored four at the same address so that four labels can be read simultaneously by one access.

Specifically, as shown in the figure, labels 1 to 4 are stored in the address "ΔΔΔ1", labels 5 to 8 are stored in the address "ΔΔΔ2", ... Labels 9 to 12 are stored in the address "ΔΔΔ3", and four consecutive labels are stored in sequence at the same address, such as ...

Next, the arithmetic processing of the programmable controller configured as described above will be described.

FIG. 6 shows the procedure of arithmetic processing of this programmable controller.

In the programmable controller, the processor 1 performs arithmetic processing. First, the processor 1 accesses the label storage area in the data memory 15 and simultaneously reads out the four labels stored at the same address (step 100), by referring to the instruction start information of the most significant bit of each of the read four labels, the instruction start information is “1” in order from the smallest label number among the four labels. That is, it is determined whether or not there is a label whose instruction head information indicates the head of the instruction (step 200).

If the instruction head information does not include a label indicating the instruction head (step 200 "N").
o "), the process returns to step 100 and the four labels at the next address are read out.

On the other hand, if the instruction head information has a label indicating the head of the instruction (step 200 "Yes"
s "), and subsequently, it is judged whether or not the execution condition composed of the lower 3 bits of the label indicates the execution of the operation (step 300), and only when the execution condition indicates the execution of the operation (step 300" Yes ”), based on the value of a program counter (not shown) and the like, the instruction component such as the corresponding opcode portion and address portion is read from the program memory 14 (step 400), and the operation of the instruction component is executed (step 500). ).

Here, the operation execution of the instruction component is 0.
If it is an instruction word of the address system, the operation code part is decoded and executed, and if it is an instruction word other than the 0 address system,
If the instruction component is the opcode part, decoding of the opcode part, selection of an arithmetic circuit according to the decoding result, and the like, if the instruction component is the address part,
This is a process of reading data, which is an operand indicated by the address portion, from the data memory 15 and performing an arithmetic operation or the like by the arithmetic circuit selected above.

Then, returning to the processing of step 200 again, it is judged whether or not there is a label whose instruction head information indicates the instruction head among the remaining labels read at the same time, and the instruction head information indicates the instruction head. If there is a label (step 200 “Yes”), the above step 300
Similarly, when the instruction head information does not include a label indicating the instruction head (step 20).
0 "No"), the process returns to step 100 and the four labels at the next address are read out.

Next, the flow of the arithmetic processing shown in FIG. 6 will be concretely described with reference to the labels 1 to 7 shown in FIG. 4 and FIG.

The value (PF) of the power flow register 11a in the processor 11 is initially set to "0".

First, the processor 11 executes the process of step 100 of FIG.
Labels 1 to 4 are read out at the same time from ΔΔ1 ”, and label 1 is“ 1000 ”as shown in FIG. 4, which indicates that the operation is always executed at the beginning of the instruction.
It is determined that the label is the head of the instruction by the processing of 00, and that the operation is executed by the determination of the following step 300.
By the processing of steps 400 and 500, the operation code part of the instruction 1 corresponding to the label 1 is read from the program memory 14 and the operation is executed.
The process returns to 0.

Returning to the processing of step 200, next, of the remaining labels 2 to 4 read at the same time as the label 1, the content of the label 2 is "1001" as shown in FIG. When the value is 1, it indicates that the operation is executed. Therefore, the label 2 is determined to be the label at the beginning of the instruction in the determination in step 200. Then, the value of the power flow register 11a is determined to be "0" by the judgment at the subsequent step 300.
Since it is set to No., it is determined that the operation is not executed, and the processing of reading and executing the operations of steps 400 and 500 is skipped and the process returns to step 200.

Returning to the processing of step 200, the contents of the remaining labels 3 and 4 are both "0" as shown in FIG.
000 ", it is determined in step 200 that there is no label at the beginning of the instruction, and steps 300 to 50
It skips without reading the address part of the instruction 2 which is the instruction constituent element corresponding to the labels 3 and 4 which is the processing of 0, and does not execute the operation, and returns to the processing of step 100. As a result, for the instruction 2, neither the operation code portion nor the address portion is read or operated.

Returning to the processing of step 100, the processor 11 simultaneously reads the labels 5 to 8 by designating the next address "ΔΔΔ2" of the data memory 15 as shown in FIG. 5, and shown in FIG. As described above, the label 5 is "1001", which indicates that the operation is executed when PF = 1 at the beginning of the instruction as in the case of label 2. Therefore, it is determined in step 200 that the label is the beginning of the instruction, and the subsequent step 300 The value of the power flow register 11a is "0".
Since it is determined that the calculation is not executed with the setting set to,
Skip steps 400 and 500 and skip
The process returns to step 200.

Returning to the processing of step 200, next, of the remaining labels 6 to 8 read simultaneously with the label 5, the content of the label 6 is "0000" as shown in FIG. , Label 6 is skipped by the determination in step 200. as a result,
For instruction 3, neither the operation code part nor the address part is read or operated.

On the other hand, the content of the label 7 is "1010" as shown in FIG. 4, which indicates that the operation is executed when PF = 0 at the beginning of the instruction. It is determined that it is the label at the beginning of the instruction, and the power flow register 11
Since the value of "a" is set to "0", it is determined that the label 7 is to be operated, and the operation code portion of the instruction 4 corresponding to the label 7 is stored in the program memory by the processing of steps 400 and 500. 14, the calculation is executed, and the process returns to step 200.

As described above, the variable word length instructions 1 to 4 as shown in FIG. 2 to which the labels 1 to 7 shown in FIG. 4 are set correspondingly.
Therefore, when the instructions 2 and 3 are skipped and executed, the operation code part which is the first word of the instructions 2 and 3 to be skipped in the conventional technique is also read, and all the operation code parts of the respective instructions 1 to 4 are read. However, according to the present embodiment,
For the instructions 2 and 3 to be skipped, it is not necessary to read the operation code part from the program memory 14.

Therefore, according to the present embodiment, the processor 11 judges the contents of the label consisting of the instruction head information and the execution condition so that only the instruction to be executed is read from the program memory 14 and executed, while the execution is executed. Since an instruction not to be executed is skipped without reading even the operation code part from the program memory 14, when the instruction operation is skipped, the instruction to be executed next can be skipped at high speed.

Therefore, most of the operation time of the processor 11 is used only for effective operation execution of the instruction to be executed, and the operation speed of the processor 11 can be increased and the skipped instruction can be executed. It is possible to eliminate useless access such as memory access to the operation code part of.

Further, according to the present embodiment, four 4-bit labels for each instruction constituent element of each instruction are sequentially stored in the same address of the data memory 15, and when reading each instruction, the data memory is stored. After reading four labels of the same address from 15, each of the four instruction elements of each instruction determines whether it is the instruction head and the execution condition, and then reads the instruction element of each instruction from the program memory 14. Since the instructions are executed by executing the instruction, if the instruction has a short word length, the labels of a plurality of instructions can be read at the same time to determine the execution condition and the like, and the operating speed of the processor 11 is also increased in this respect. .

In the present embodiment, the label is represented by 4 bits and the execution condition is set based on the value of the power flow register 11a. However, the present invention is not limited to this. The label may be other than 4 bits, and the execution condition may be set regardless of the value of the power flow register 11a. In this case, the power flow register 11
Since a is not necessary, the present invention can be applied to a general data processing device including a processor without the power flow register 11a.

[0060]

As described above, according to the present invention, a label consisting of instruction head information and an execution condition is stored for each opcode section and address section which compose a variable word length instruction, and the label is stored in one memory address. Therefore, it is possible to read a few words from the program storage means and read only the instruction to be executed from the program storage means by referring to the label, and skip the instructions not executed without reading them from the program storage means. When the instruction calculation is skipped, the instruction to be executed next can be skipped at high speed.

Therefore, most of the operation time is used only for effective operation execution of the instruction to be executed,
The calculation speed can be increased, and unnecessary access such as memory access to the skipped instruction can be eliminated.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a programmable controller that is an embodiment of a data processing device according to the present invention.

FIG. 2 is an explanatory diagram showing a method of storing a variable word length instruction that constitutes a user program in a user program memory.

FIG. 3 is an explanatory diagram showing the contents of a label L set for each instruction constituent element of an operation code section and an address section which constitute each variable word length instruction.

FIG. 4 is an explanatory diagram showing a specific example of contents of labels 1 to 7 for each instruction constituent element of each variable word length instruction stored in a program memory.

FIG. 5 is an explanatory diagram showing a label storage method in a data memory.

FIG. 6 is a flowchart showing a procedure of arithmetic processing of the programmable controller.

FIG. 7 shows an example of a method of skipping a variable word length instruction in a conventional data processing device.

FIG. 8 is another example of a method of skipping a variable word length instruction in a conventional data processing device.

FIG. 9 is another example of a method of skipping a variable word length instruction in a conventional data processing device.

[Explanation of symbols]

11 processor (instruction executing means) 11a Power flow register 12 system memory 13 work memory 14 program memory (program storage means) 15 data memory (label storage means) 16 Input / output (I / O) interface L label L3 instruction start information L2-L0 execution conditions

─────────────────────────────────────────────────── --- Continuation of the front page (56) Reference JP-A-8-320786 (JP, A) JP-A-6-161747 (JP, A) JP-A-3-216734 (JP, A) JP-A-3- 63725 (JP, A) JP-A-2-278303 (JP, A) JP-A-63-36405 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 9 / 30-9 / 42

Claims (5)

(57) [Claims] 1. A data processing device for executing data processing by executing a program consisting of a variable word length instruction composed of an operation code portion and an address portion having a different number of words depending on the instruction, and an operation code portion forming the variable word length instruction. A program storing means for storing the program by storing the program and the address portion at consecutive addresses for each of the opcode portion and the address portion; and for each of the opcode portion and the address portion of the variable word length instruction stored in the program storing means. The label storage means in which a plurality of labels set corresponding to each other are stored at the same address, and the plurality of labels stored in the same address of the label storage means are simultaneously read by one access, and the plurality of labels are referred to to read the program. Instruction execution means for reading out and executing the variable word length instruction from the storage means, The data processing apparatus according to claim. 2. The label storage means includes instruction head information indicating whether or not an opcode portion and an address portion forming a variable word length instruction are instruction heads, and an opcode portion and an address portion forming a variable word length instruction. The data processing device according to claim 1, wherein an execution condition indicating whether or not an operation is executed and a label consisting of are stored. 3. The instruction executing means refers to a plurality of labels and reads out and executes a variable word length instruction from the program storage means, based on the instruction head information among the labels read out simultaneously in one access. It is judged whether or not there is a label indicating the beginning of the instruction. If there is no label indicating the beginning of the instruction, the plural labels stored at the next address are read from the label storage means while the beginning of the instruction is read. If there is a label shown, then the execution condition of that label is judged, and if the execution condition indicates the execution of operation, the corresponding opcode part or address part is read from the program storage means and executed. If the operation execution is not indicated, the corresponding opcode part or address part is skipped without being read from the program storage means. 2. The data processing device according to 2. 4. The instruction execution means is a power flow register used to determine the execution condition of an application instruction subsequent to the basic instruction, as well as to set the operation result when the basic instruction is executed. The program storage means stores a program including variable word length instructions of the basic instruction and the application instruction, while the label storage means has instruction head information and an opcode part and an address part that constitute the variable word length command. A label consisting of an execution condition indicating whether or not to execute an operation based on the setting of the power flow register is stored, and the instruction executing means stores a plurality of labels stored at the same address of the label storing means. Are read at the same time by one access, and a variable word length instruction is read from the program storage means by referring to the plurality of labels and executed. Performed cyclically beam execution process, the data processing apparatus according to claim 2, wherein a. 5. The instruction executing means refers to a plurality of labels and reads out and executes a variable word length instruction from the program storage means based on instruction head information among labels read out simultaneously by one access. It is judged whether or not there is a label indicating the beginning of the instruction. If there is no label indicating the beginning of the instruction, the plural labels stored at the next address are read from the label storage means while the beginning of the instruction is read. If there is a label shown, then the execution condition of that label is judged based on the setting of the power flow register, and if the execution condition indicates execution of operation based on the setting of the power flow register, the corresponding opcode Section or address section is read from the program storage means and executed, and if the execution of the operation is not shown based on the setting of the power flow register, the corresponding operation is performed. The opcode portion or the address unit skips without getting read from said program storage means, the data processing apparatus according to claim 4, wherein a.