JPH10111704A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To change a program at high speed, to reduce a memory area used for a differential flag and to make hardware constitution for executing an instruction fetch processing at the time of executing differential instruction to be simple. SOLUTION: When the instruction stored in an address value is decoded from a program storage memory 12, an instruction decoder 112 outputs a differential number to a differential flag address generator 112 if the received instruction is the differential instruction. The differential number flag address generator 112 refers to the differential number and outputs the address value for reading the differential flag stored in a differential flag storage memory 13. An AND circuit 117 outputs '1' to an arithmetic part 114 when a power flow(PF) value is 'l' and the differential flag is '0', namely, in the case of a rise-type differential instruction and the arithmetic part 114 executes processing following a content which the instruction decoder 112 decodes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a programmable controller for controlling an external device such as a sensor using a sequence program including a ladder program.

[0002]

2. Description of the Related Art Generally, a conventional programmable controller has an MPU 50 for managing the whole as shown in FIG.
A work memory 51 of the MPU 50, an R0M 52 for storing a program for the MPU 50, an interface 53 for other I / O, a sequence engine 54 for executing a sequence operation, a differential instruction to be described later and other instructions , A normal instruction), a program storage memory 55 for storing a sequence program, a data storage memory 56 for storing data, and a differential flag storage memory 57 for storing a differential flag.

In addition, since the conventional programmable controller cannot predict where the differential instruction is located in the program storage memory 55, the address corresponding to each instruction constituting the sequence program has a one-to-one correspondence. Is stored in the differential flag storage memory 57.

Accordingly, in such a conventional programmable controller, although the address space of the program storage memory 55 and the address space of the differential flag storage memory 57 are separate spaces, each instruction constituting the sequence program and the differential flag When fetching an instruction, the lower address of the address is made common, or the same address is used, and only the difference of the data bus 59 is used.

That is, the differential flag of the differential instruction of interest is associated and specified by the program counter.

Here, the differential instruction is an instruction for determining whether or not to be executed by a differential flag. The differential instruction includes an output type rising differential instruction and an output type falling differential instruction.

The output type rising differential instruction is executed when the differential flag is "0" and the value of the PF is "1", assuming that the PF has risen, and is not executed under other conditions. The output-type falling differential instruction is executed when the differential flag is “1” and the value of PF is “0”, assuming that PF has fallen. The instruction to be executed.

[0008] The differential flag is the PF value of each instruction in the previous cycle. That is, if a certain instruction has “1” as the PF value this time, after executing this instruction, the differential flag for this instruction becomes “1”.

Here, the process of executing such a differential instruction of the programmable controller will be described with reference to the flowchart of FIG.

When the sequencer engine 54 reads the differential instruction from the program storage memory 55, the sequencer engine 54 reads the differential instruction stored in the differential flag storage memory 57 at the address value corresponding to (calculated) the address value of the read differential instruction. The flag is read (step 210).

Next, the sequencer engine 54 determines whether or not to execute this differentiation command based on the PF value and the read differentiation flag (step 220).

That is, when the read differentiation flag is 0 and the power flow (hereinafter, referred to as PF) is 1 (step 220; Y), the sequencer engine 54 determines the instruction to execute the read differentiation instruction. On the other hand, otherwise (step 220; N), it is determined that the read differential instruction should not be executed.

Subsequently, the sequencer engine 54 updates the PF as a differential flag, regardless of whether the read differential instruction is an instruction to be executed or an instruction not to be executed. (Steps 230 and 240) (the above is the differential instruction execution determination processing A described above).

When the differential instruction execution determination processing A is completed, the sequencer engine 54 executes the instruction if the read differential instruction is an instruction to be executed (step 250). Processing that is not executed when it is not an instruction to be executed (hereinafter referred to as normal processing B)
I do.

[0015]

However, in such a conventional programmable controller, a differential flag corresponding to each instruction constituting a sequence program stored in the program storage memory 55 is stored on a one-to-one basis. 57, it is necessary to change the differentiation flag in accordance with the change of the program when the program is changed, and there is a problem that the program change is wasted time.

For example, as a program change, FIG.
Address 0x2014 shown in (a) ("Other instruction 1")
In the case where one new instruction is added to the instruction stored at the address 0x2015 before the new instruction is added, as shown in FIG.
In this case, the differential flag and the corresponding differential flag are shifted by 0x12 before being added.
It must be shifted backward by one from address 015 (see FIG. 9C).

Further, although the ratio of the differential instructions to be processed to all the instructions is considerably small, the differential flag storage memory 57 needs to have the differential flag areas corresponding to all the instructions, so that the memory area is considerably redundant. There was a problem that had to be.

Further, when updating the differential flag, the instruction reading is temporarily suspended, and an address for the differential flag is generated on an address bus 58 which is common to the program storage memory 55 and the differential flag storage memory 57. Since it is necessary to write the differential flag into the differential flag storage memory 57 via the flag data bus 60, there is a problem that the hardware configuration for the sequence engine 54 to fetch an instruction is complicated.

Accordingly, the present invention has been made in view of the above-described problems, and enables a program to be changed at a high speed, a memory area used for a differential flag to be reduced, and an instruction fetch at the time of executing a differential instruction. It is an object of the present invention to provide a programmable controller having a simplified hardware configuration for performing processing.

[0020]

According to one aspect of the present invention, there is provided a programmable controller for executing a program instruction comprising a normal instruction and a differential instruction. A differential instruction having an operand having a differential number indicating a storage position is executed.

According to a second aspect of the present invention, there is provided a programmable controller including a program storage memory for storing a program instruction composed of a normal instruction and a differential instruction, and a differential flag storage memory for storing a differential flag. If the read instruction is a differential instruction, a differential flag address for outputting the address of the differential flag for the differential instruction stored in the differential flag storage memory from the differential number of the read differential instruction Output means.

According to a third aspect of the present invention, in the second aspect of the present invention, the differential flag address output means adds an offset address to a head address of the differential flag storage memory, and further adds a differential number. Is the address of the differentiation flag for the above differentiation instruction.

The invention according to claim 4 is the invention according to claim 2 or 3.
In the described invention, a differential flag value for the differential instruction instructed from the differential flag address output means,
Determining means for determining whether or not to execute the read differential instruction from the power flow value.

According to a fifth aspect of the present invention, in the fourth aspect of the present invention, when the determining means is different from a differential flag value for the differential instruction instructed by the differential flag address output means and a power flow value. Is determined to execute the read differential instruction.

According to a sixth aspect of the present invention, a normal instruction is executed after executing a differential execution determination instruction including an operation code indicating that a differential execution is performed and an operand indicating a differential number indicating a storage position of a differential flag.

According to a seventh aspect of the present invention, there is provided a program storage memory having a differential execution determination instruction including an operation code indicating execution of differentiation and an operand indicating a differentiation number indicating a storage position of differential flag information, and a normal instruction. If the instruction read from the program storage memory is a differential execution determination instruction, and if the instruction read from the program storage memory is a differential execution determination instruction, the differential flag storage A differential flag address output means for outputting an address of a differential flag for the differential instruction stored in the memory.

According to an eighth aspect of the present invention, in the seventh aspect of the present invention, the differential flag address output means adds an offset address to a head address of the differential flag storage memory, and further adds a differential number. Is the address of the differentiation flag for the differentiation execution determination instruction.

The invention according to claim 9 is the invention according to claim 7 or 8.
In the described invention, a differential flag value for the differential instruction instructed from the differential flag address output means,
Determining means for determining whether to execute the normal instruction read next from the differential flag storage memory from the power flow value.

According to a tenth aspect of the present invention, in the ninth aspect of the present invention, the determining means determines that a differential flag value and a power flow value for the differential execution determination command output from the differential flag address output means are different. If not, it is determined that the normal instruction read next from the differential flag storage memory is to be executed.

According to the present invention, a differential instruction having an instruction opcode and an operand having a differential number indicating a storage position of a differential flag stored in a differential flag storage memory is executed. Therefore, it is not necessary to change the differential flag with the change, and the differential flag storage memory does not need the differential flag area corresponding to all instructions.

Further, after executing a differentiation execution determining instruction comprising an operation code indicating that differentiation is to be performed and an operand indicating a differentiation number indicating a storage position of the differentiation flag information, a normal execution instruction is executed. Differential execution is possible with any ordinary instruction immediately after.

[0032]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a programmable controller according to the present invention will be described below with reference to the drawings.

<First Embodiment> FIG. 1 is a block diagram showing a configuration of a first embodiment of a programmable controller according to the present invention.

The programmable controller of this embodiment is for processing a differential instruction having a configuration as described later and a normal instruction, and includes a sequence engine 11 for executing a sequence operation, and a sequence engine 11 for executing a normal instruction and a differential instruction to be described later. And a differential flag storage memory 13 for storing a differential flag corresponding to each differential instruction.

The sequence engine 11 includes a program counter 111 for indicating the address of the instruction to be executed, an instruction decoder 112 for decoding the read instruction, a differential address generator 113, an operation unit 114 for processing the read and decoded instruction, and a buffer. 115, a 1-bit register 116 for storing a PF value, and an AND circuit 117.

The differential address generator 113 is configured to output an address value for reading a corresponding differential flag from the differential flag storage memory 13.

The buffer 115 temporarily stores the PF value necessary for updating the differential flag in the differential flag storage memory 13 and temporarily stores the differential flag read from the differential flag storage memory 13. .

Here, the differential instruction executed by the programmable controller of this embodiment is formed of a differential instruction opcode, an operand representing a differential number, and a plurality of other operands.

Incidentally, the program instruction shown in FIG. 2 is a differential addition instruction (see a in the figure), and the differential instruction read out from the differential flag storage memory 13 with reference to the differential number (see b in the figure). If this differential instruction is to be executed based on the flag, the operand (A) shown in FIG.
A + B obtained by adding the data A stored in the operand (B) and the data B stored in the operand (B) shown in FIG.
Is stored in the operand (C) shown by e in the figure.

The programmable controller of this embodiment, which executes such a differentiation instruction, should read the corresponding differentiation flag from the differentiation flag storage memory 13 with reference to the differentiation number when executing this instruction. The address is calculated.

For example, as shown in FIG. 3, the operation code of the instruction m is stored at the address 0x02012 of the program storage memory 12, the differential number “13” of the instruction m is stored at the address 0x02013, and the address 0x02016 is stored at the address 0x02016. Assume that the operation code of the instruction n stores “14” as the differential number of the instruction n at address 0x02017.

Then, the programmable controller according to the present embodiment uses the program memory 0x020
When executing the instruction stored at the address 0x022014 from the address 12 as shown in FIG. 4, to read the differential flag from the differential flag storage memory 13, if the address to be offset is set to 0x10000, this differential Start address of flag storage memory 13 + 0x10000 for offset + 0x12 for differential number "13"
The differential flag stored at address 013 is read.

Further, the programmable controller of this embodiment is configured such that 0x0201 of the program storage memory 12
To read the differential flag from the differential flag storage memory 13 at the time of executing the instruction stored at the address 0x02018 from the address 6, 0x12014
The differential flag stored at the address is read.

Next, the operation of the programmable controller of this embodiment will be described with reference to FIG.

When the program counter 111 in the sequence engine 11 outputs an address to be read, and receives an instruction stored at the address value from the program storage memory 12, the instruction decoder 112 decodes the received instruction.

If the received instruction is a normal instruction as a result of decoding, the instruction decoder 112 outputs the decoded contents to the arithmetic unit 114, and the arithmetic unit 114 performs processing according to the instruction.

On the other hand, if the received instruction is a differential instruction, the instruction decoder 112 outputs the differential number to the differential flag address generator 112.

Then, the differential flag address generator 113
Refers to the differentiation number, and as described above, differentiates the address value of the differentiation flag stored in the differentiation flag storage memory 13 calculated by the start address of the differentiation flag storage memory 13 + the offset number + the differentiation number. Output to the flag storage memory 13.

After that, the buffer 4 temporarily stores the differential flag stored in the address value read from the differential flag storage memory 13 and then stores the AND flag in the AND circuit 117.
Output to the inverting terminal.

The current PF value is input from the 1-bit register to another terminal of the AND circuit.

The AND circuit 117 has a PF value of “1”,
When the differential flag is “0”, that is, in the case of a rising-type differential instruction, “1” is output to the arithmetic unit 114,
The processing according to the contents decoded by the instruction decoder 112 is performed.

On the other hand, if the PF value is “1” and the differential flag is other than “0”, that is, if the differential flag is not a rising differential instruction, the AND circuit 117 outputs “0” to the arithmetic unit 114. The instruction to output the next instruction without outputting the instruction content from the instruction decoder 112 is output to the program counter.

In the programmable controller of this embodiment, the reference number for calculating the address of the differential flag read from the differential flag storage memory 13 is stored in the differential instruction to be executed. Assuming that one new instruction is added to the address 0x2015 shown in FIG. 4, the instructions stored after the address 0x2015 before the new instruction is added are shifted backward by one, as shown in FIG. However, for example, the differential flag corresponding to the instruction n at the changed addresses 0x02017 to 0x02019 remains unchanged before the storage position is changed.

This means that, as shown in FIG. 5A, when a program (instruction) is added to the program storage memory 12 (change of the program), the differentiation flag stored in the differentiation flag storage memory is also changed. The processing (step X) performed by the conventional programmable controller to move in accordance therewith is not necessary in the programmable controller of this embodiment, so that the program can be changed at high speed.

Further, in the programmable controller of this embodiment, since the management of the differential flag is provided as the differential number in the operand of the instruction, the storage location of the differential flag is not restricted, and the memory allocation is facilitated.
The derivative flag can be handled as mere data.

By the way, considering the frequency of appearance of differential instructions in the ladder program and the instruction length of one instruction, there is no particular problem even if the differential flag storage area is about half of the program storage area. Although the differential flag storage memory area is the same as the conventional program area, the differential flag storage area can be saved.

Conventionally, a separate memory chip was required for storing the differential flag as a system. However, in the programmable controller of this embodiment, the cost of the entire system can be reduced by using one area in the data memory. can do.

<Second Embodiment> The programmable controller according to the above-described embodiment uses a differential instruction opcode, an operand representing a differential number, and other instructions formed of a plurality of operands. As shown in FIG. 6, the differential instruction may be divided into a differential execution determination instruction including an operation code of a differential execution determination instruction and an operand of a differential number, and a normal instruction.

The normal instruction immediately after the differential execution determination instruction executes / non-executes according to the execution condition of the differential execution determination instruction.

The configuration of the programmable controller for processing the above-described differential execution determination instruction and the ordinary instruction is essentially the same as the configuration of the above-described programmable controller, but the program storage memory has the same configuration as the above-described programmable controller instead of the differential instruction. It has a differentiation execution determination command including an operation code indicating that differentiation is to be performed and an operand indicating a differentiation number indicating a storage position of a differentiation flag.

In the programmable controller of this embodiment, when the instruction read from the program storage memory is a differential execution determining instruction, the differential flag address generator generates the differential execution determining instruction. It is configured to output the address of the differentiation flag for the differentiation instruction stored in the differentiation flag storage memory from the differentiation number.

In the programmable controller according to this embodiment, the differential flag address generator adds the offset address to the head address of the differential flag storage memory, and furthermore, adds the value obtained by adding the differential number to the differential flag for the differential execution determination instruction. Address.

Further, the programmable controller according to the present embodiment, based on the differential flag value and the power flow value for the above-mentioned differential execution determination instruction instructed from the differential flag address generator, generates a normal instruction to be read next from the differential flag storage memory. It is configured to determine whether or not to execute.

Further, the programmable controller of the embodiment, when the power flag value is different from the differential flag value corresponding to the differential execution determination command instructed from the differential flag address output means, reads the next value from the differential flag storage memory. It is configured to determine that a normal instruction to be executed is to be executed.

FIG. 6 shows C = A + B shown in FIG.
Is divided into a differential execution determination instruction and a normal instruction.

As described above, by making the differential execution determination instruction a separate instruction, it becomes possible to perform differential execution with any normal instruction immediately after the differential execution determination instruction.

For this reason, conventionally, the normal instruction and the differential instruction have to be treated as separate instructions, so that the restrictions on the implementation (restriction of the area representing the instruction pattern, etc.) and the normal instruction are implemented. Can bypass the limitation that it is not supported.

That is, if implemented as a normal instruction,
By inserting a differentiation execution determination command before the command, the device can operate as a differentiation command.

[0069]

According to the present invention, the differential instruction to be executed has the instruction opcode and the operand consisting of the differential number indicating the storage position of the differential flag stored in the differential flag storage memory. When changing the program,
There is no need to change the derivative flag with the change in the program.

Therefore, it is not necessary to change the differentiation flag in accordance with the change in the program, and the program can be changed at a high speed.

Further, it is not necessary to hold a one-to-one corresponding differential flag in the differential flag storage memory for each instruction constituting the sequence program stored in the program storage memory, and it is not necessary to have a redundant memory area. .

Further, the hardware configuration for the sequence engine to perform the instruction fetch can be simplified.

In particular, since a differential execution determination instruction including an operation code indicating that a differential execution is to be performed and an operand indicating a differential number indicating a storage position of differential flag information is executed, a normal instruction is executed. Any normal instruction immediately after the judgment instruction enables differential execution.

Therefore, if implemented as a normal instruction,
If a differentiation execution determination command is inserted before the command, the operation can be performed as a differentiation command.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a first embodiment of a programmable controller according to the present invention.

FIG. 2 is a block diagram showing a configuration of a differential instruction used in the program controller of the embodiment.

FIG. 3 is an explanatory diagram of a configuration of a program storage memory and a differential flag storage memory in FIG. 1;

FIG. 4 is an explanatory diagram of a configuration of a program storage memory and a differential flag storage memory in FIG. 1;

FIG. 5 is a flowchart showing a difference in processing between the programmable controller of this embodiment and a conventional programmable controller.

FIG. 6 is a block diagram showing a differential execution determination instruction and a normal instruction executed by a programmable controller according to a second embodiment of the present invention.

FIG. 7 is a block diagram showing a schematic configuration of a conventional programmable controller.

FIG. 8 is a flowchart showing the operation of a conventional programmable controller.

FIG. 9 is an explanatory diagram of an address change when one instruction is added to the program storage memory in FIG. 8;

[Explanation of symbols]

 11 Sequence Engine 12 Program Storage Memory 13 Differential Flag Storage Memory 111 Program Counter 112 Instruction Decoder 113 Differential Flag Address Generator 114 Operation Unit 115 Buffer 116 1-bit Register 117 AND Circuit

Claims (10)

[Claims] 1. A programmable controller for executing a program instruction including a normal instruction and a differential instruction, wherein the programmable controller executes a differential instruction having an instruction opcode and an operand including a differential number indicating a storage position of a differential flag. Programmable controller. 2. A programmable controller comprising: a program storage memory for storing a program instruction including a normal instruction and a differential instruction; and a differential flag storage memory for storing a differential flag, wherein the instruction read from the program storage memory is A differential flag address output means for outputting, from a differential number of the read differential instruction, an address of a differential flag for the differential instruction stored in the differential flag storage memory, if the instruction is a differential instruction; A programmable controller, characterized in that: 3. The differential flag address output means adds an offset address to a head address of the differential flag storage memory, and sets a value obtained by adding the differential number as an address of a differential flag for the differential instruction. 3. The programmable controller according to claim 2, wherein: 4. A determining means for determining whether or not to execute the read differential instruction from a differential flag value for the differential instruction specified by the differential flag address output means and a power flow value. The programmable controller according to claim 2 or 3, wherein the programmable controller is provided. 5. The method according to claim 1, wherein the determining means executes the read differential instruction when the power flow value is different from the differential flag value for the differential instruction specified by the differential flag address output means. The programmable controller according to claim 4, wherein: 6. An operation code indicating execution of differentiation,
A programmable controller characterized by executing a normal instruction after executing a differential execution determination instruction including an operand indicating a differential number indicating a storage position of a differential flag. 7. A program storage memory having a differential execution determination instruction including an operation code indicating execution of differentiation and an operand indicating a differentiation number indicating a storage position of a differentiation flag, a program storage memory having a normal instruction, and a differentiation flag storing a differentiation flag. If the instruction read from the storage memory and the program storage memory is a differential execution determination instruction, the differential number stored in the differential flag storage memory is obtained from the differential number of the read differential execution determination instruction. A differential flag address output means for outputting an address of a differential flag for the differential instruction. 8. The differential flag address output means adds an offset address to a head address of the differential flag storage memory, and further sets a value obtained by adding the differential number as an address of the differential flag for the differential execution determination instruction. The programmable controller according to claim 7, wherein: 9. Based on a differential flag value and a power flow value for the differential instruction specified by the differential flag address output means, it is determined whether or not to execute the normal instruction read next from the differential flag storage memory. 9. A judgment means for judging, wherein:
The programmable controller as described. 10. When the power flag value is different from the differential flag value for the differential execution determination command output from the differential flag address output means, the determination means reads the differential flag value from the differential flag storage memory next. 10. The programmable controller according to claim 9, wherein it is determined that the normal instruction is executed.