JPH08272411A - Ladder instruction processor - Google Patents

Abstract

PURPOSE: To speed up processing by completing ladder instruction processing without performing arithmetic processing in accordance with a ladder instruction when an input/output value relating to ladder instruction processing is equal to the one stored in an input/output data table. CONSTITUTION: A comparison part 27, when input data 1, 2 and output data being fetched from a variable area (memory) 23 corresponding to the ladder instruction 21, takes out data 1-3 in accordance with the previous ladder instruction based on a table address stored in an input/output data table position information storage part 25, and compares the input data 1, 2 and the output data taken out from the variable area (memory) 23 with the data 1-3 in accordance with the previous ladder instruction taken out from the input/output data table 26. When coincidence between them is obtained, it is assumed that the processing this time by the ladder instruction 21 is the same one by the previous ladder instruction, and a processing completion part 28 completes the processing relating to the ladder instruction 21.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a ladder instruction processing device mounted on a programmable controller for executing a ladder instruction, and more particularly to a ladder instruction processing device improved to speed up ladder instruction processing.

[0002]

2. Description of the Related Art Generally, a ladder instruction installed in a programmable controller reads a value in a variable area as an input value, performs an operation unique to each instruction, and writes the operation result in the variable area. Here, the ladder instruction includes a basic instruction that performs a simple bit operation and an application instruction that performs a complicated operation.

FIG. 4 is a block diagram showing a processing system configuration of a conventional ladder instruction processing device for executing a ladder instruction mounted on a programmable controller. In FIG. 4, a program area 20 stores a program including a plurality of ladder instructions. Then, the ladder instructions 21 are sequentially fetched from the program area 20 and the desired ladder instructions are executed.

The ladder instruction 21 is composed of an operation code, an operand 1, an operand 2 and an operand 3. here,
The operation code specifies the operation of the ladder instruction, and operand 1, operand 2, and operand 3 are
It specifies the data to be the target of the operation specified by the operation code.

The operand 1, operand 2, and operand 3 of the ladder instruction 21 fetched from the program area 20 are converted into addresses in a variable area (memory) 23 for storing the target data in the address conversion section 22.

Here, the operand 1 and the operand 2 of the ladder instruction 21 specify the input data 1 and the input data 2 stored in the variable area (memory) 23, and the operand 3 is stored in the variable area (memory) 23. If the output data is specified, the arithmetic processing unit 24
Is the input data 1 stored in the variable area (memory) 23 corresponding to the address converted by the address conversion unit 22.
And the input data 2 are read as input values, and the ladder instruction 2 based on the input data 1 and the input data 2 is read.
The predetermined operation designated by the operation code 1 is executed, and the operation result is written as an output value in the output data of the variable area (memory) 23.

FIG. 5 is a flow chart showing a ladder instruction processing algorithm in the conventional ladder instruction processing apparatus shown in FIG. Both the basic instruction and the application instruction are processed by the processing algorithm shown in FIG.

In FIG. 5, first, the program area 2
The operation code and the operand that compose the ladder instruction 21 are read from 0 (step 11), and the operand address corresponding to the operand is resolved (step 1).
2).

Then, the data (input data) of the source address resolved from the variable area (memory) 23 by the processing of the above step 12 is loaded (step 13),
Output data is generated by processing the operation peculiar to the instruction with this input data (step 14).

After that, the output data generated in step 14 is stored in the resolved destination address of the variable area (memory) 23 (step 15).

[0011]

By the way, in the conventional ladder instruction processing apparatus described above, it is required to speed up the ladder instruction processing.

The following two methods can be considered as methods for speeding up the ladder instruction processing: 1) speeding up by mounting hardware logics 2) speeding up by improving algorithms.

Here, the method 1) by implementing the hardware logic has an advantage that the speed can be increased without changing the current algorithm, but on the other hand, the implementation becomes difficult as the processing becomes complicated, In addition, it has a drawback that it is difficult to change the processing content.

In other words, the method of implementing the hardware logic of 1) is difficult to apply to application instructions whose processing is complicated.

Therefore, in order to be applicable to the application instruction, it is preferable to adopt the method of improving the algorithm of 2).

By the way, in the conventional ladder instruction processing, each ladder instruction is executed every time it is generated. Here, if there is a ladder instruction process that does not need to be executed,
It can be expected that the ladder command processing can be speeded up by omitting the processing.

Therefore, considering the conventional ladder instruction processing, if the value of the variable area used as the input / output data in a certain ladder instruction does not change from the previous execution of the ladder instruction, the processing for this ladder instruction is executed. It is useless to do. This is because the calculation result of this process is the same as that of the previous execution, and the same value is overwritten on the output data of the variable area.

However, in the conventional ladder instruction processing, regardless of the value of the input / output data in the variable area,
Since the ladder instruction is configured to be executed every time each ladder instruction is generated, the above wasteful processing is also executed, and as a result, the ladder instruction processing can be sufficiently speeded up. There will be no.

Therefore, an object of the present invention is to provide an improved ladder instruction processing device so as to speed up the ladder instruction processing.

[0020]

In order to achieve the above object, the present invention reads the value of a variable area as an input value in response to a ladder instruction, and based on the input value, performs arithmetic processing corresponding to the ladder instruction. A ladder command processing device for executing a ladder command process for writing the calculation result as an output value in the variable area after performing an input / output data table storing the input value and the output value corresponding to the input value, When executing the ladder command processing, comparing means for comparing the input / output value related to the ladder command processing with the input / output value stored in the input / output data table, and the input / output related to the ladder command processing by the comparing means. When the value matches the input / output value stored in the input / output data table, the ladder instruction processing is ended without performing the arithmetic processing. Characterized by comprising a physical means.

According to the present invention, in addition to the above configuration, the storage position of the input value of the input / output data table and the output value corresponding to the input value every time the ladder command processing corresponding to the ladder command is executed. Is further provided with position information updating means for updating the position information indicating.

[0022]

In the ladder instruction processing device of the present invention, the input value read corresponding to the ladder instruction and the output value which is the operation result obtained by performing the arithmetic processing corresponding to the ladder instruction on the input value are stored in the input / output data table. When storing and executing the ladder instruction processing, the comparing means compares the input / output value related to the ladder instruction processing with the input / output value stored in the input / output data table, and if the two match by the comparison,
The processing means terminates the ladder instruction processing without performing arithmetic processing corresponding to the ladder instruction.

Further, every time the ladder command processing corresponding to the ladder command is executed, the position information updating for updating the position information indicating the storage position of the input value and the output value corresponding to the input value in the input / output data table is updated. It can be configured by further including means.

Further, the comparing means can be configured to compare the input / output value relating to the ladder command processing with the input / output value of the input / output data table corresponding to the position information.

Further, the processing means can be operated only when the specific operation time corresponding to the ladder instruction is longer than the comparison time by the comparison means.

Here, the processing means can operate only when the ladder instruction is an application instruction that performs a complicated operation.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of a ladder instruction processing device according to the present invention will be described below in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a schematic system configuration of an embodiment of a ladder instruction processing device according to the present invention. In FIG. 1, the same reference numerals as those used in FIG. 4 are given to the portions having the same functions as those of the conventional ladder instruction processing device shown in FIG.

In FIG. 1, a program area 20 stores a program including a plurality of ladder instructions. Then, the ladder instructions 21 are sequentially fetched from the program area 20 and the desired ladder instructions are executed.

The ladder instruction 21 is composed of an operation code, operand 1, operand 2 and operand 3. here,
The operation code specifies the operation of the ladder instruction, and operand 1, operand 2, and operand 3 are
It specifies the data to be the target of the operation specified by the operation code.

The operand 1, operand 2, and operand 3 of the ladder instruction 21 fetched from the program area 20 are converted into addresses in the variable area (memory) 23 for storing the target data in the address conversion section 22.

Here, the operand 1 and the operand 2 of the ladder instruction 21 designate the input data 1 and the input data 2 stored in the variable area (memory) 23, and the operand 3 is stored in the variable area (memory) 23. If the output data is specified, the ladder command 2
Input data 1 and input data 2 and output data corresponding to the address converted corresponding to 1 are taken out from the variable area (memory) 23.

On the other hand, the input / output data table 26 stores data 1 corresponding to the input data 1 relating to the previous ladder instruction, data 2 corresponding to the input data 2 and data 3 corresponding to the output data.

The input / output data table position information storage unit 25 stores position information indicating the storage positions of data 1, data 2 and data 3 corresponding to the previous ladder instruction in the input / output data table 26, that is, table addresses. It is stored.

When the input data 1, the input data 2, and the output data are taken out from the variable area (memory) 23 in response to the ladder instruction 21, the comparison unit 27 stores them in the input / output data table position information storage unit 25. Input data 1, input data 2, output data and input / output data table extracted from the variable area (memory) 23 based on the table address The data 1, data 2, and data 3 corresponding to the previous ladder instruction extracted from 26 are compared.

In the comparison in the comparison unit 27, the input data 1 and the input data 2 and the output data extracted from the variable area (memory) 23 and the data corresponding to the previous ladder instruction stored in the input / output data table 26 are stored. If 1, data 2 and data 3 match, it is determined that the processing by the ladder instruction 21 this time is the same as the processing by the previous ladder instruction, and the processing termination unit 28 terminates the processing related to this ladder instruction 21.

In the comparison in the comparison unit 27,
Input data 1, input data 2 and output data fetched from the variable area (memory) 23 do not match data 1, data 2 and data 3 corresponding to the previous ladder instruction stored in the input / output data table 26. Then, assuming that the processing by the ladder instruction 21 this time is different from the processing by the previous ladder instruction, the same arithmetic processing as the conventional one is executed.

That is, the arithmetic processing section 24 has a comparison section 27.
The input data 1 and the input data 2 fetched from the variable area (memory) 23 are read as input values via the, and a predetermined operation designated by the operation code of the ladder instruction 21 is performed based on the input data 1 and the input data 2. Along with the execution, a process of writing the operation result as an output value into the output data of the variable area (memory) 23 is executed.

When the arithmetic processing section 24 executes the arithmetic processing, the input / output data table updating processing for writing new data 1, data 2 and data 3 in the input / output data table 26 in accordance with the arithmetic result. To execute.

The table address stored in the input / output data table position information storage unit 25 is updated every time one instruction is executed.

FIG. 2 is a flow chart showing a ladder instruction processing algorithm in the ladder instruction processing device shown in FIG.

In FIG. 2, first, the program area 2
The operation code and the operand that form the ladder instruction 21 are read from 0 (step 101), and the operand address corresponding to the operand (source address corresponding to operand 1 and operand 2 and destination address corresponding to operand 3) is resolved ( Step 102).

Then, data (input data 1, input data 2, output data) is loaded from the source address / destination address resolved from the variable area (memory) 23 by the processing of step 102 (step 103).

Next, in the comparison unit 27, the load data (input data 1, input data 2,
The output data) is compared with the values (data 1, data 2, data 3) of the input / output data table 26 obtained from the position information (table address) of the input / output data table position information storage unit 25 (step 104).

Then, in the comparison of step 104,
Input data 1, input data 2, output data and data 1,
It is determined whether or not the data 2 and the data 3 match.

When it is determined in step 105 that the input data 1, input data 2 and output data match the data 1, data 2 and data 3 (step 1
(YES in 05), assuming that the process by the ladder command 21 this time is the same as the process by the previous ladder command, the process proceeds to step 109, the input / output data table update process is executed, and this ladder command process is ended (step 11
0).

If it is determined in step 105 that the input data 1, input data 2, and output data do not match data 1, data 2, and data 3 (NO in step 105), the current ladder command Assuming that the processing by 21 is different from the processing by the previous ladder instruction, the same arithmetic processing as the conventional one is executed.

That is, the arithmetic processing unit 24 reads the input data 1 and the input data 2 fetched from the variable area (memory) 23 as input values, and the input data 1
And the input data 2 is used to process an operation peculiar to the instruction specified by the operation code of the ladder instruction 21 to generate output data (step 106), and the generated output data is stored in the destination address resolved in step 102. Store (step 108).

Thereafter, the input / output data related to the operation of the above step 106 is stored in the input / output data table 26 (step 108), and the process proceeds to step 109 to execute the input / output data table update process to execute this ladder command process. The process ends (step 110).

FIG. 3 shows a format example of the input / output data table 26. As shown in FIG. 3, the input / output data table 26 is a fixed-length table, and has a storage area corresponding to the total number of commands used in the table. There is one input / output data table 26 for each command. To do. That is, one input / output data table 26-1 to 26-n exists corresponding to one instruction.

Therefore, this input / output data table 2
6 has position information (table address), and this table address is updated every time one instruction is executed. This table address is stored in the input / output data table position information storage unit 25.

It should be noted that, in the processing of the above-described embodiment, it is in the case of the application instruction that the operation time peculiar to each instruction is long that contributes to the speedup of the ladder instruction processing, and for the basic instruction where the operation time peculiar to the instruction is short, It may make little contribution or may rather increase the processing time.

Among the application instructions, there are some that are relatively simple in arithmetic processing such as simple data transfer. With these instructions, the comparison time of the input / output data, which is the additional processing of the algorithm according to this embodiment, becomes longer than the operation time unique to each instruction, and as a result, the execution time cannot be shortened.

Therefore, the processing of the above embodiment may be executed only when the relation of the operation time peculiar to each instruction> the comparison time of input / output data corresponding to each instruction is satisfied.

Some instructions have input / output data in a variable area table. In this case, however, the length of the input / output data table becomes indefinite. Not applicable.

Further, it is preferable that the position information of the input / output data table is updated inside the ladder instruction. This is because if the position information is updated outside the ladder instruction, information on the use / non-use of the input / output data table is required for each instruction.

[0057]

As described above, according to the ladder instruction processing device of the present invention, the input value read in correspondence with the ladder instruction and the operation result obtained by performing the arithmetic processing corresponding to the ladder instruction on the input value. A certain output value is stored in the input / output data table, and at the time of executing the ladder instruction processing, the input / output value related to the ladder instruction processing is compared with the input / output value stored in the input / output data table by the comparing means, and the comparison is made. Therefore, when the two match, the ladder instruction processing is configured to be terminated without performing the arithmetic processing corresponding to the ladder instruction. Therefore, the ladder instruction processing device and method improved so as to speed up the ladder instruction processing. Can be provided, and further various effects as described below can be obtained.

1) The processing time of application instructions can be shortened. 2) By reducing the ladder instruction processing time, the processing capacity of the MPU that executes the ladder instruction processing can be allocated to other processing, and the efficiency of resource allocation can be improved. 3) By speeding up on software, MPU,
It is possible to easily follow the increase in the speed of memory etc.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic system configuration of an embodiment of a ladder instruction processing device according to the present invention.

FIG. 2 is a flowchart showing a ladder instruction processing algorithm in the ladder instruction processing device shown in FIG.

FIG. 3 is a format diagram showing a format example of the input / output data table shown in FIG.

FIG. 4 is a block diagram showing a processing system configuration of a conventional ladder instruction processing device that executes a ladder instruction installed in a programmable controller.

5 is a flowchart showing a ladder instruction processing algorithm in the conventional ladder instruction processing device shown in FIG.

[Explanation of symbols]

 20 Program Area 21 Ladder Command 22 Address Conversion Unit 23 Variable Area (Memory) 24 Arithmetic Processing Unit 25 Input / Output Data Table Position Information Storage Unit 26 Input / Output Data Table 27 Comparison Unit

Claims (5)

[Claims] 1. A variable area value corresponding to a ladder instruction is read as an input value, arithmetic processing corresponding to the ladder instruction is performed based on the input value, and then the arithmetic result is output to the variable area as an output value. In a ladder command processing device that executes a ladder command process to write, an input / output data table that stores the input value and the output value corresponding to the input value, and an input / output table related to the ladder command process when executing the ladder command process. Comparing means for comparing the output value with the input / output value stored in the input / output data table; and input / output values related to the ladder instruction processing by the comparing means and the input / output values stored in the input / output data table. And a processing unit that terminates the ladder instruction processing without performing the above arithmetic processing, the ladder instruction. Management apparatus. 2. A position information update that updates position information indicating a storage position of the input value and the output value corresponding to the input value in the input / output data table each time the ladder command processing corresponding to the ladder command is executed. The ladder instruction processing device according to claim 1, further comprising means. 3. The ladder according to claim 2, wherein the comparing means compares an input / output value related to the ladder command processing with an input / output value of the input / output data table corresponding to the position information. Instruction processor. 4. The ladder instruction processing device according to claim 1, wherein the processing means operates only when a specific operation time corresponding to the ladder instruction is longer than the comparison time by the comparison means. 5. The ladder instruction processing device according to claim 4, wherein the processing means operates only when the ladder instruction is an application instruction that performs a complicated operation.