JP2522372B2 - Data driven computer - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a so-called data-driven computer that employs a method of driving processing based on a dependency relationship between data to be processed.

[Conventional technology]

Typical examples of conventional data-driven computers are pages 19 to 22 and IEEE COMPCON '84 of the proceedings of the high-speed computing system research and development results presentation for science and technology (June 25, 1984).
It is disclosed on pages 486 to 490 of the SPRING Proceedings (English). All of these known materials describe the configuration and operation of a data driven computer called Sigma-1. The prior art will be described below based on these publicly known materials.

FIG. 5 shows the configuration of the above-mentioned conventional data driven computer.

This data-driven computer has a network interface 14 that is an interface with the outside of the computer, a matching memory 10 that detects two data whose destination node numbers match from each data to be processed, and an operation instruction code based on the node number. An instruction fetch unit 15 for fetching, an instruction execution unit 12 for executing arithmetic processing according to an instruction code, a destination designation unit 16 for designating a next destination node number of data after arithmetic processing, and the like, and a data path connecting these. Has been done.

Further, FIG. 4 is an example of a program (data flow graph) for explaining a specific operation of the conventional data driven computer.

In this data flow graph, data A and B are added at node # 0, the resulting data G and another data C are multiplied at node # 2 to obtain the resulting data I, and the other is data D. E and E are added at node # 1, and the resulting data H and another data F are added to node # 1.
4 to obtain the result data J ... The data W and X are multiplied at the node # 7096, and the result data Y and the previously obtained data I are obtained at the node # 70.
At 97, the result is added to obtain the data Z, and so on.

Packet (data with tag information) A (201) input from outside via the network interface 14
Is composed of a destination node number <0> and data [A]. This packet 201 is sent to the matching memory 10, and at the same time, the destination node number <0> (203) in the packet 201 is also sent to the instruction fetch unit 15.
Assuming that packet B having data [B], which is a partner of binary operation of data [A], has already been input and is waiting in matching memory 10, these two packets A,
Since the destination nodes of B match with each other at # 0, the matching memory 10 outputs the packet 206 including the data [A] and the data [B] as a pair.

On the other hand, the instruction fetch unit 15 reads and outputs the instruction code “+” (205) which is the content of the address corresponding to the node number <0>.

 The memory configuration of the instruction fetch unit 15 is shown in FIG.

Next, the destination node number <0> input to the instruction fetching unit 15 is sent as it is to the destination specifying unit 16 as the node number <0> (20). Further, the instruction code “+” (205) read by the instruction fetching section 15 is a data pair [A],
It is given to the instruction execution unit 12 as a packet 207 together with the packet 206 of [B]. At this time, in the destination designation unit 16, the node number <0> in the data flow graph of FIG.
<2> (208) representing the node # 2 to which the result data of the addition, which is the operation corresponding to, is to be read next is read.

 The memory configuration of the destination specifying unit 16 is shown in FIG. 6 (b).

At the same time, in the instruction execution unit 12, [A] + [B]
The calculation result data [G] (209) is output. Output 208 of destination designation unit 16 and output 209 of instruction execution unit 12, that is, destination node number <0> and data [G]
And the packet 210 as a network interface 14
And is sent again to the instruction fetch unit 15 and the matching memory 10.

Through the chain of processing as described above, the operations corresponding to all the nodes of the data flow graph shown in FIG. 4 are performed, and the execution of the program ends. At this time, the processing in the node having the data dependency, for example, the node # 0 and the node # 2 can be executed only sequentially in this order, but the node having no data dependency, for example, the node # 0. The processes in the node # 1 can be executed in parallel as long as the processing resources allow. Note that here, the data dependency relationship is a connection relationship between two nodes.
It means that the connection relationship is such that the input data necessary for performing the other process is supplied only after the process of one node is completed.

The memory configurations of the instruction fetch unit 15 and the destination designating unit 16 are shown in FIGS. 6 (a) and 6 (b), respectively, as described above. Since the bit width of each information is not clearly described in the publicly known material, here, the bit width of the instruction code is 4 bits,
The bit width of the destination node number is assumed to be 16 bits. Further, since there is no specific description about the data copy operation in the publicly known material, it is assumed that a widely known method is used for the data copy.

The most significant bit "COP in the memory in the destination specifying unit 16"
Y "is a copy bit, and when the operation result at a node in the data flow graph shown in FIG. 4 is sent to multiple nodes, data copy is performed and the destination node number is assigned to each data. For example, the copy bit at the second address of the memory is "1" in response to the operation result in the node # 2 being sent to both the node # 7097 and the node # 5. Is stored. In this case, the destination node number # 7097 is read, added to the operation result [I] and output, and then the next address (third address) is continuously read and the destination node number # 7097 is read. The number # 5 is added to the same calculation result [I] and output.

[Problems to be Solved by the Invention]

By the way, the conventional data driven computer as described above has a problem that the scale of the program memory becomes large.

In the case of the Neumann computer, which is widely used at present, since the sequential processing is performed in the order described in the program, the execution address is centrally managed by one register called a program counter. Therefore, it is not necessary to specify the address (jump destination address) of the next instruction to be executed other than the branch instruction, and it is possible to store programs of the same content in a program memory of a smaller scale than a data-driven computer. it can. On the other hand, in the case of a data driven computer, since the processing of each instruction is executed in parallel, it is impossible to centrally manage the execution address.
For this reason, in a data-driven computer, it is necessary to specify the address (destination node number) of the next instruction to be executed for all instructions in principle, which causes the scale of the program memory to increase. Has become. Also in the above-mentioned conventional example, the destination node number occupies 16 bits out of the bit width of 21 bits per instruction (instruction code 4 bits + destination node number 17 bits).

In view of such circumstances, the present invention reduces the hardware scale of a data driven computer by compressing the scale of the program memory, and at the same time improves performance by shortening the memory access time accompanying the compression of the memory scale. It is a matter of illustration.

[Means for solving the problem]

The data-driven computer of the present invention has a configuration in which the destination node number in the program memory is represented by a relative address having a variable length from the storage address of the current instruction.

[Action]

In the data driven computer according to the present invention, since the storage address of the instruction to be executed next is represented by, for example, the relative address with respect to the current instruction, the storage address of the instruction next is
It is obtained by performing an operation between the address of the current instruction and the relative address of the next instruction.

Example of Invention

Hereinafter, the present invention will be described in detail with reference to the drawings showing an embodiment thereof.

FIG. 1 is a block diagram showing the configuration of an embodiment of a data driven computer according to the present invention.

The data-driven computer of the present invention is a network interface 14 that is an interface with the outside, a matching memory 10 as a match detection unit that detects two data whose destination node numbers match from each data to be processed, a node number. A program memory 11 having a function of taking out the code of the operation instruction based on the above and two functions of designating the next destination node number of the data after the operation processing, an instruction as an operation processing unit for executing the operation processing according to the instruction code It is composed of an execution unit 12, an adder 13 as an arithmetic means for updating the destination node number, and a data path connecting them.

With such a data driven computer of the present invention,
The operation will be described for the case of executing the program (data flow graph) shown in the figure. The data flow graph shown in FIG. 3 is the same program as the program shown in FIG. 4 described above, but the node numbers are assigned differently for the purpose of explaining the present invention.

In this data flow graph, data A and B are added at node # 0, the resulting data G and another data C are multiplied at node # 2 to obtain the resulting data I, and the other is data D. E and E are added at node # 1, and the resulting data G and another data C are added to node # 1.
5, the resulting data J is obtained, the data W and X are multiplied at node # 7096, and the result data Y and the previously obtained data I are obtained at node # 70.
At 97, the result is added to obtain the data Z, and so on.

The packet 101 input from the outside via the network interface 14 includes the destination node number <0>, the data [A], and the instruction code “+”.

In the data driven computer of the present invention, pipeline processing of two cycles is performed. The first stage is waiting for data in the matching memory 10. The packet 101 input from the outside is sent to the matching memory 10. At this time, if the packet including the partner data [B] of the binary operation “+” has not arrived, the input packet 101
101 is once stored in the matching memory and waits for the arrival of a packet containing data [B]. Also, when a packet including the other data [B] has already arrived and is stored in the matching memory, it is detected that the destination node numbers <0> of these two packets match. A packet 102 in which data [B] is added to the input packet 101 is sent out from the matching memory 10.

Of the information included in the packet 102, the destination node number <0> (103) is sent to the program memory 11 and the adder 13 described later, and the remaining data [A] and [B] and the instruction code “+” Is sent to the instruction execution unit 12 as a packet 104.

In the instruction execution unit 12, the data [A] and [B] are added according to the instruction code “+”, and the addition result data [G] (107) is output.

On the other hand, the processing in the program memory 11 that is executed in parallel with the processing in the instruction execution unit 12 will be described below.

FIG. 2 shows the memory configuration of the program memory 11 of the data driven computer according to the present invention.

In the memory of FIG. 2, the most significant bit "EXT" of each word is an extended address flag described later.

The lower bit "COPY" is the "COP" in the conventional example.
It has the same meaning as the Y "bit, and if this" COPY "bit is" 1 ", there are multiple destination nodes of the operation result, and the operation code and destination node number information for each destination node are It indicates that it is stored after the next address.

The instruction code (OPECODE) to be executed in the next cycle is stored in the lower 4 bits following this "COPY" bit, and the destination node number is the current node number in the lower 6 bits. It is stored as a relative address (RNODE) with respect to.

A specific operation of the data driven computer of the present invention as described above will be described.

When the packet 101 is detected as matching in the matching memory 10 and the packet 102 is output, the node number <0> (103) of the packet 102 is output to the program memory 11. As a result, the address 0 of the memory shown in FIG. 2 is accessed, and the instruction code “*” and the relative destination node number <2> are successively output, and the instruction code register (OPE-RE
G) 131 and destination node number register (DEST-REG) 132, respectively.

The instruction code is output from the instruction code register 131 as it is. On the other hand, the relative destination node number <2> is sent from the destination node number register 132 to the adder 13, and the adder 13 inputs the input node number <0> (10
3) and the absolute value of the destination node number <2> (106)
Is obtained.

The packet 108 composed of the instruction code “*”, the destination node number <2>, and the data [G] output from the instruction executing unit 12 thus obtained matches again via the network interface 14. The entire program is executed by being supplied to the memory 10 and repeating such processing.

However, in the present invention, since the bit width of the memory of the program memory 11 for storing the relative destination node number is limited to 6 bits, the actual value of the relative destination node number is 255.
Overflow occurs when (= 2 ⁶ -1) is exceeded.

For example, the relative destination node number corresponding to the arrow from the node # 2 to the node # 7079 in the data flow graph of FIG. 3 corresponds to this. In such a case, the most significant bit "EX" of the program memory corresponding to each node number
By setting T "to" 1 ", the present invention is configured so that the next address can be used as an extended address bit area for storing an overflow digit.

The input data [G] and [C] necessary for the processing in the node # 2 in FIG. 3 are complete, and the destination node number <2>, the instruction code “*”, the data [G] and [C] are acquired from the matching memory 10. A case will be described in which the packet composed of is output.

As described above, the instruction code and the data are sent to the instruction execution unit 12 to be multiplied, and the result data [I] is output. In parallel with this, the destination node number <2> is sent to the program memory 11, and the destination node numbers are successively output.
The detailed logical operation of the program memory 11 when the input node number is <N> is shown in the flowchart of FIG.

In this flowchart, "READ M" is an operation for reading the M address of the memory, bits (6: 0), etc. are a bit string composed of bits 6 to 0, "EXT", "COP".
Y "represents the value of the extended address flag bit and the copy flag bit in the program memory, respectively.

When the packet having the destination node number <2> is input to the program memory 11, the content of the second address of the program memory 11 is read (step S4). Of the read contents, the instruction code “+” indicates that the instruction code register 131
And the relative destination node number <4> is written in the lower 6 bits of the destination node number register 132, that is, in bits (5: 0) (steps S5 and S6).

Since the "EXT" bit of the read word is "0" (step S7), the instruction code and the value <4> of the destination node number register and the input node number <2>6> is output as the destination node number (step S8).

At this time, since the "COPY" bit of the read word is "1", the read address <2> is incremented (step S10), and the loop count <L> and the contents of the destination node number register 132 are cleared ( Step S2,
S3), the third address, which is the address after the increment, is read (step S4).

Similar to the case of the first read, the instruction code "+" in the read word and the relative destination node number <55> (= "11011
1 ") are written in the lower 6 bits of the instruction code register 131 and the destination node number register 132, respectively (step S
5, S6). Since the "EXT" bit of the read word is "1" (step S7), the read address is incremented (step S11), the contents of address 4 are read, and the lower 10 bits of the read word are set to the destination node. Number register 13
Write from bit 15 to bit 6 of 2 (step S13). Since the value of the EXT bit of the last read word is “0” (step S15), the current instruction code “+” and the contents of the destination node number register 132 <7095> (= “0001 1011 1
011 0111 ") and the addition result of the input node number # 2 <7
097> is output (step S8).

The value of the COPY bit of the last read word is "0".
Therefore (step S9), the series of processes for the input packet having the node number <2> ends.

As described above, when the relative destination node number is given as the destination node number, even if the relative destination node number overflows beyond the predetermined bit width, the next address of the program memory is set to the extended address of the relative destination node number. The present invention can be applied to a program of which scale is completed by using it as an area and which node number is assigned.

Generally, since the connection between nodes is local, it is considered that the relative destination node number rarely takes a large value regardless of the program scale. In fact, we evaluated the statistical distribution of the relative destination node numbers when the node numbers were assigned to the test program consisting of 3987 nodes so that the nodes nearer to the input would be assigned smaller node numbers. . The results are shown in the graph of FIG. The horizontal axis of the graph shows the relative destination node number, the vertical axis shows the percentage of the cumulative frequency, and the numbers for each section indicate the number of nodes included in that section.

From the graph of FIG. 8, it is easily understood that about 90% (88%) of the total have relative destination node numbers within 63 addresses. In other words, even if the bit width of the relative destination node number is 6 bits, it means that there is about a 10% possibility that the extension bit as described above is needed.

The bit width of the program memory in the conventional example is 21 bits (instruction fetching section 4 bits + destination designating section 17 bits), whereas in the case of the present embodiment it is 12 bits, which is expanded when the present invention is carried out. Even if the number of extra words required to store the address is about 10% from the above statistics, the memory size is compressed to (12 × 1.1) / 21 ≈ 0.63 times. In this embodiment, the program memory space is
Although 16 bits is used, this compression effect becomes more remarkable as the program memory space increases. For example, if the program memory space is 32 bits, the relative destination node number space is expanded to 8 bits, and even if the proportion of extended address bits required is estimated to be 20%, the memory scale will be And substituting the actual number of bits, It is doubled and can be compressed to less than half.

In the above embodiment, the relative destination node number is limited to a positive number for the sake of simplification of description. However, by using a signed number (two's complement representation), the node number smaller than the output side node number. It becomes possible to send data to a node having. As a result, the present invention can be applied to a program including a repeating structure.

Further, in this embodiment, the overflow bit of the relative destination node number is assigned to the extension bit. However, as another method, the program is divided into page units, and the page internal address is represented by, for example, 6 bits, and the page is crossed. It is also possible to adopt a method of assigning the relative page number to the extension bit when the destination node exists.

In the above embodiment, the instruction fetching unit and the destination designating unit of the data driven computer shown in the conventional example are integrated into one program memory, and this program memory is arranged in parallel with the instruction executing unit, so that the redundant input is performed. The hardware scale is reduced by omitting the address latch and decoder.

By arranging the program memory and the instruction execution unit in parallel in this way, the basic cycle for executing one instruction is two pipelines: processing in the matching memory and processing in the "program memory + instruction execution unit". Since it is composed of stages, a short basic cycle comparable to that of the conventional data driven computer is obtained, and the response time for a single instruction can be suppressed to be short.

〔The invention's effect〕

As described above, in the data-driven computer of the present invention, the destination node number is stored by designating the destination node number in the program memory by, for example, the relative address from the storage address of the current instruction. It is possible to significantly reduce the bit width of and reduce the scale of the program memory.

Generally, a data-driven computer is built on a calculation model suitable for parallel and distributed processing, and it has the distinctive feature that multitasks are autonomously executed in parallel without special control. It is considered. However,
In the case of the current method in which the address of the program memory that stores each of the multitasks is fixedly determined, the task Ta currently being executed and the other task Tb that may share the area of the program memory are , Even if there is a free area in the program memory, it cannot be executed at the same time. Therefore, the current situation is that the current data-driven computer has not been able to fully utilize the inherent characteristic of being suitable for multitasking.

On the other hand, in the data-driven computer of the present invention, since the node numbers of all nodes are specified by the relative destination node numbers from other nodes, if there is a free area in the program memory, it will be irrelevant to the absolute address. , A new task can be externally loaded to any free area and executed in parallel with other tasks.

The above is a description of multitask execution on one processor, but as shown in FIG. 9, it seems that a plurality of data driven computers (processors) # 0 to #N are connected via a network. In such a configuration,
If the individual tasks Ta, Tb, Tc across each processor occupy the same program memory area within each processor, multitask execution can be performed even for multiprocessors that perform packet communication with each other via a network. Also, it is possible to generate a task, and it is possible to easily execute high-speed parallel distributed processing using a plurality of data-driven computers.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a data driven computer according to the present invention, and FIG. 2 is a memory configuration of a program memory of the data driven computer according to the present invention, more specifically, FIG. 3 is a schematic diagram showing the memory contents when the program of FIG. 3 is stored, FIG. 3 is a schematic diagram showing an example of a program (data flow graph) executed by the data driven computer of the present invention, and FIG. FIG. 5 is a schematic diagram showing an example of a program (data flow graph) executed by the data driven computer, showing a program similar to that shown in FIG. 3 except for node number assignment, and FIG. 6 is a block diagram showing an example of a computer, FIG. 6 (a) is a diagram showing a memory configuration of an instruction fetching unit in a conventional data driven computer, and FIG. 6 (b) is a memory configuration of a destination designating unit. And FIG. 7 is a schematic diagram showing a configuration, each showing memory contents when the program shown in FIG. 4 is stored, and FIG. 7 is a flowchart showing a detailed processing procedure in the program memory of the data driven computer of the present invention, FIG. 8 is a graph showing the distribution of the values of the relative destination node numbers, and FIG. 9 is a conceptual diagram showing a map of the program memory in the execution state of multitask in the multiprocessor configuration. 10 …… Matching memory, 11 …… Program memory, 12
... Instruction execution unit, 13 ... adder In the drawings, the same reference numerals indicate the same or corresponding parts.

Continuation of the front page (56) References Omori et al. "Proposal on program storage method of data driven processor-proposition" Parallel Processing Symposium JSSP'89 Proceedings (1989-02-02-04) PP.85-90. Arvind & V. Katha il "A Multiple Process Processor Data Flow Machined Supports Generalized Procedures 285-1981.

Claims (1)

(57) [Claims] 1. A match detection unit for detecting two data whose destination node numbers are attached to each piece of data to be processed, and data for the two data for which a match is detected by the match detection unit. An arithmetic processing unit for performing arithmetic processing in accordance with the attached instruction code, and its contents are read by using the destination node number attached to the data processed by the arithmetic processing unit as an address, and the contents are read based on the read contents. In a data-driven computer including a program memory that updates a destination node number of data and an instruction code, the program memory stores the destination node number attached to the data processed by the arithmetic processing unit and the destination node number. An address calculation means for performing a predetermined calculation with the variable length address information read from the program memory as an address, A data-driven computer, characterized in that the result of calculation by the address calculation means is set as the updated destination node number.