JPH0533409B2 - - Google Patents

Description

Claim 1: In a computer system executing a program, some of which are time-dependent, each concurrent process having a plurality of instructions, the computer system comprises: forming a second pointer for each process to point to a program step for said process; scheduling a plurality of processes to direct processes; and identifying a time-dependent collection of processes executed by the processor, wherein the processes in the collection are executed by the next process. each scheduling time is given to each process in said collection, and the execution of said current process is terminated before the current process continues execution. instructions including time-related instructions indicating a scheduling time; and (a) determining whether the scheduling time has already arrived; and (b) the scheduling time has not yet arrived. (i) storing a second pointer to the process; (ii) stopping execution of the current process; and (iii) adding the stopped process to the collection and adding it to its schedule. (iv) further directing the execution of instructions related to said time by setting the current process's instructions to indicate which processes are to be scheduled; a step of executing a sequence of instructions to direct the next process at a time after the scheduling time of the next process; and executing the next process at a program stage indicated by the second pointer to the next process in response to execution of an instruction to stop the current process. How to run concurrent processes to. 2. Upon execution of a time-related instruction, if the step of determining whether the scheduling time has already arrived indicates that the scheduling time has already arrived, the current process stops. 2. The method according to claim 1, wherein the method continues execution. 3 (a) providing a work area in memory for each process, each having a plurality of addressable memory locations, and storing associated variables of the process corresponding to said locations in each work area; and (b) within the work area of each process in the list, scheduling time instructions for said process;
and forming a time-dependent collection by providing an indication of the first pointer to a process having a next scheduling time. or the method described in paragraph 2. 4. Scheduling of a plurality of processes includes the step of identifying a scheduled collection of processes waiting for execution by said processor without waiting a scheduling time, said next process receiving said scheduled collection. 4. A method according to any one of claims 1 to 3, characterized in that the method is added to and removed from the time-dependent collection after the scheduling time. 5. The method of claim 5, wherein the scheduled collection is formed as a list, and each process on the scheduled list stores within its workspace the indication of a first pointer to the next process in the list. The method described in Scope Items 3 and 4. 6, further comprising the step of indicating a priority for each process, and providing first and second time-dependent collections of processes, wherein the first time-dependent collection is a common first priority process. and wherein the second time-dependent collection comprises a common second priority process different from the first priority. Method described in Crab. 7. further comprising the step of transmitting messages between simultaneous processes via a plurality of addressable communication channels to enable data communication between the processes; 6. A method as claimed in any of claims 1 to 5, characterized in that a series of instructions in a program containing common instructions are executed to complete message transmission between processes. 8. Executing a process having a plurality of components associated with alternative times; and dictating the time associated with each component;
8. A method according to any one of claims 1 to 7, further comprising the step of determining whether a time associated with some of the components has already occurred. 9. The method further comprises: unscheduling the process if the earliest time associated with some of the components associated with the alternative time has not yet occurred; and adding the process to a time-dependent collection. 9. The method according to claim 8, characterized in that: 10, further comprising the step of loading into a memory location associated with the process at least one special value indicating the state of the process and indicating that the process has an alternative component. The method according to claim 8 or 9. 11 a first special value indicating that the process need not be unscheduled when at least one of the alternative components is ready or while waiting for the arrival of a time associated with one of the alternative components; 11. The method of claim 10, further comprising the step of loading another special value into the memory location indicating that the process is to be unscheduled. 12 yet another special value indicating that none of said alternative components has been selected yet;
loading into a memory location associated with said process and in response to said further special value;
selecting one of the alternative components when a process is scheduled.
The method according to any one of Items 1 to 11. 13. At least one of the alternative components comprises inputting via one communication channel, determining whether the earliest time of the time-related component has already occurred, and determining whether the communication channel is waiting for message input. Claims 7 to 12 further comprising the step of determining whether or not
The method described in any of the paragraphs. 14 a processor for executing a plurality of simultaneous processes, at least some of which are time-dependent, and addressable storage elements for indicating the current process being executed by the processor; and a timer list for identifying one or more processes forming a collection waiting to be executed by the processor after each scheduling time, the timer list comprising: , a microcomputer having process instruction means for instructing the next process in a collection for execution by said processor after its scheduling time has occurred, each of the processes in said collection being scheduled for execution when a process in said collection is ready for execution; A memory location 69 is associated with the timer list for indicating the scheduling time and the temporal ordering between earlier processes having earlier scheduling times and later processes having later scheduling times. , a control system 13, 14, 15, 32 for adding one further process to a location within said collection. 15. For each process, said memory has a work area 60 having addressable storage locations, each of said work areas having, for a process on said temporally ordered list: (i) a corresponding one; (ii) a second memory location 65 for storing program steps related to the corresponding process; and (iii) a next memory location 65 on said temporally ordered list. a third storage location 68 for directing the process of
Claim 14, characterized in that it comprises: and
Microcomputer as described in Section. 16 Storage means 52, 56, 66 are processor 1
2 to identify a collection of scheduled processes waiting to be executed by the timer, and to add one process to said collection at the same time as removing it from said timer list after its scheduling time has arrived. Characteristic Claim No. 14
16. The microcomputer according to item 1 or 15. 17. An additional memory location 66 for indicating the next process within the scheduled collection such that the timer list and scheduled collection each have a list linked via the process work area 60. 17. The microcomputer according to claim 15, wherein the microcomputer has a working area of . 18. Microcomputer according to any one of claims 14 to 17, characterized in that the addressable communication channels 70, 25 enable synchronized message transmission between processes. DETAILED DESCRIPTION The present invention relates to computers including microcomputers, and more particularly to microcomputers capable of executing time-dependent processes. BACKGROUND OF THE INVENTION Our European patent specification 0110642 includes:
A microcomputer is described that includes scheduling means that enable a processor to share its processing time among multiple simultaneous processes. You can form a linked list of scheduled processes waiting to run. You can unschedule a currently running process, and you can schedule a process by adding it to a scheduled list when requested. This may occur, for example, when transmitting messages between two processes where the two processes are required to be at corresponding stages of a program sequence when the message transmission occurs. However, that patent does not describe the use of time-dependent processes such that scheduling of a process can be done according to the times indicated for that process. OBJECTS OF THE INVENTION It is an object of the invention to provide an improved microcomputer for use in executing time-dependent processes. Another object of the invention is a means for scheduling multiple simultaneous processes such that a processor shares its processing time among the multiple processes;
An object of the present invention is to provide an improved microcomputer having means for responding to time-dependent parameters for one or more processes. Although the term microcomputer refers to a small computer based entirely on integrated circuits, it does not impose any constraints on how small the computer can be. SUMMARY OF THE INVENTION The present invention comprises a memory and a processor configured to execute a plurality of simultaneous processes according to a program, the program comprising a plurality of instructions for sequential execution by the processor, the program comprising: (1) a plurality of registers and data transfer means used to transfer data between those registers; and (2) receiving each instruction and loading the value associated with that instruction into one of the processor registers. and (3) a controller that controls in accordance with instructions received from the data transfer means and the register and operates the processor in accordance with the instructions, wherein: (a) a certain process is executed by the processor; including means for instructing when it is to be executed;
scheduling means for sharing processing time of a processor among multiple concurrent processes; and (b)(1) identifying one or more processes for execution by the processor; At least one timer collection (timer
(2) means for indicating a scheduling time at which each process is allowed to execute in said timer collection; and (3) means for providing one or more additional (4) means for removing processes from the timer collection; a process time controller comprising: a microcomputer comprising: a means for adding processes; The means for instructing the timer collecting process to form a time-ordered sequence depending on the scheduling time of the timer collecting process or each process is preferably arranged. Preferably, means are provided which can comprise an addressable memory location to indicate the timer collecting process which has the earliest scheduling time during the collection and forms the first process during the collection. The memory preferably provides each process with a work area having a plurality of addressable locations containing locations for recording variables associated with the process, one of the processor registers comprising:
It is configured to hold a work area pointer value that identifies the address of the current process's work area. The work area of each process preferably contains linkage means that hold pointer values for subsequent processes during timer collection. The linking means is used when a process is in the process of collecting timers to point to the next process in the process of collecting timers, thereby pointing to the linked timer list of the process. Preferably, the linking means of each process work area is configured to hold a special value to indicate that the process is the one with the last scheduling time on its timer list. In order to dictate the scheduling time of each process, the work area of that process should include as much addressable space as possible. In a preferred embodiment, the microcomputer includes means for assigning one of a plurality of priorities to each process, and the time controller includes means for forming two or more of the timer collections; Each timer collection has a process with a common priority that is different from the common priority of processes in another timer collection. The scheduling means (1) indicates the current process being executed by the processor; and (2) identifies the one or more processes forming the scheduled collection that are awaiting execution by the processor. (3) means for adding one or more further processes to said scheduled collection; and (4) means for adding a next process in said scheduled collection to be executed by a processor. process instruction means, responsive to a selected instruction to terminate execution of said current process by a processor and said next processor instruction means to make that process the current process; A processor is configured to do this, whereby the processor is operated to share its processing time among multiple simultaneous processes. Scheduled collections should also preferably be combined lists. Having a process of common priority that is different from the priority of the processes in two or more scheduled collections. The invention also includes a network of a plurality of the microcomputers interconnected. Each microcomputer has communication channels provided with one or more communication links. These communication links are dedicatedly connected to similar links on other devices, thereby allowing synchronized message transmission between simultaneous processes on various microcomputers. The microcomputer is preferably configured to execute processes with multiple separate time-related components. The microcomputer includes means for indicating the time associated with each component, means for testing the time associated with each component, and means for determining whether the earliest time associated with a component has not yet occurred. provided. means for specifying a length of time for a process to run and, responsive to the length of time, to stop execution of the current process after the time has elapsed;
and preferably means for causing the processor to reschedule the process by adding it to some scheduled collection.

[Brief explanation of the drawing]

Hereinafter, the present invention will be described in detail with reference to the drawings. Fig. 1 is a block diagram showing the main features of a microcomputer embodying the present invention, and Fig. 2 is a block diagram of a part of the microcomputer. Divided into parts, this figure particularly shows the interfaces between the central processing unit registers and data paths and arithmetic logic units, and between the central processing unit and memory and communication links, with FIG. 3 forming part of FIG. 2B. 4 shows the relationship between the artifacts of a scheduled list of high priority processes for execution by a microcomputer and the processor registers, and FIG.
Similar to Figure 6, but showing a scheduled list of low priority processes while high priority processes are running, Figure 6 shows high priority processes waiting for a predetermined time before being rescheduled. FIG. 8 shows a network of microcomputers communicating in accordance with the present invention, in which the word lengths of the microcomputers are different;
Figures 9A-9D illustrate a sequence of operations for a process that performs a "timer input"operation;
Figures 10A-10E show sequences for inserting processes into the timer list, and Figures 11A-1
Figure 1C shows the sequence of operations for the Time Alternative process, and in particular shows how the process determines which of the alternative times is faster;
Figure C shows a sequence of operations by the process of selecting between one of several alternative times (one of which has already been reached),
Figures ~14D illustrate a series of operations for an alternative to inputting a message channel or for a process that selects between certain occurrences of time, and that message channel communicates when the process initiates the selection. It is now possible to do
Figures 15A-15F illustrate alternative input through a message channel, or the times that occur when the channel is not configured to input a message and the process attempts to select one of the alternatives. 1 shows a sequence of operations for a process that selects occurrences at a specified time such that they do not have . DESCRIPTION OF THE PREFERRED EMBODIMENTS The microcomputer described in this example is an integrated circuit device comprised of a single silicon chip, having a processor, memory in the form of RAM, and links to enable external communication. including. The main elements of this microcomputer are shown in Figure 1.
It is shown on a single silicon chip 11 using p-well complementary MOS technology. A timer 9 is provided in the central processing unit (CPU) 12 to enable time control of process execution. The central processing unit has a read-only memory (ROM) 13
Also included. This read-only memory is coupled to memory interface 14. This memory interface is controlled by interface control logic 15. CPU 12 includes an arithmetic logic unit (ALU) and a register data path. They are shown in more detail in FIG. CPU1
2 and memory interface 14 are connected to bus 16. This bus interconnects the elements on chip 11. A plurality of input pins 18 are provided on the service device 17 . This microcomputer has random access memory (RAM)19 and
A ROM 20 is provided. To allow processor 12 to operate without external memory, the amount of memory on the chip is no less than 1K byte. The memory on the chip should be at least 4K bytes if possible. An external memory interface 23 is provided. The external memory interface is connected to a plurality of pins 24 for connection to optional external memory. A plurality of serial links 25 having input pins 26 and output pins 27 are provided in order to be able to link this microcomputer to other computers to form a network. As shown in Figure 8, the input and output pins of one series link are:
Each with its own single wire non-shared unidirectional connection can be connected to the input and output pins corresponding to the serial link of another microcomputer. Each serial link is connected to a synchronization logic unit 10 having process scheduling logic. This embodiment is a development of the microcomputer described in our pending PCT Patent Application No. PCTGB84/00379 and European Patent Application No. 84307586.2. To avoid unnecessary repetition of the description, full details of the construction and operation of the microcomputer are not discussed below, but the description in those patent applications is included herein by reference. This embodiment provides an improved version of the Transputer (trademark of INMOS International plc) microcomputer. This microcomputer is
Timer control is performed so that a process that has been waiting for a specified time until it can be executed can be executed depending on timer data and a timer list. The overall configuration of this microcomputer is generally similar to the overall configuration of the microcomputer described in the aforementioned patent application. In the following description, parts corresponding to the embodiments in the said patent application are given analogous designations.
The memory provides multiple process work areas with addressable locations. Their addressable locations can be indicated by pointers. Message communication can occur via channels. These channels can include addressable memory locations in the case of interprocess communication on the same microcomputer. In order to provide inter-processor communication between different microcomputers, a serial link is provided with input and output channels. The channels can also be addressed in a manner similar to addressing locations in memory. Various changes to the structure and operation of the microcomputer are necessary to achieve the improvements described above, and the following discussion is directed to those aspects in which the changes are included to effectuate those improvements. As in the example in the patent application, the specific word length in the example described is 16 bits, but 8,
It will be appreciated that word lengths such as 16, 24, 32 or other word lengths can be used. Furthermore, in this case, the eighth
As shown in the figure, microcomputers with different word lengths can be connected in the same network. Each pointer is a single word and is treated as a two's complement signed value. This means that if the most significant bit in the pointer is 1, that most significant bit is treated as negative, and all remaining bits represent positive numbers. If the most significant bit is 0, all bits in the pointer are taken to represent positive values. This allows standard comparison functions to be used on pointer values in the same way that standard comparison functions are used on numeric values. Certain values are reserved to indicate that some special action is desired, so they are never used as pointers. In the following description, names are used to represent these and other values: MostNeg Most negative value (MSB is 1, all other bits are 0) MostPos Most positive value (MSB is 0, all other bits are 1) MachineTRUE 1 MachineFALSE 0 NotProcess.p MostNeg Enabling.p MostNeg+1 Waiting.p MostNeg+2 Ready.p MostNeg+3 TimeSet.p MostNeg+1 TimeNotSet.p MostNeg+2 Dual use of values MostNeg+1 and MostNeg+2 TimeSet.p and
The special value for TimeNotSet.p is never used in the same place as Enabling.p or Waiting.p. As in the example of the above patent application, each process has a work area consisting of a vector of words in memory used to hold local variables and temporary values handled by the process. A workspace pointer WPTR is used to indicate the configured location for the process workspace. Each process can be identified by a "process descriptor." The least significant bits of the process descriptor indicate the priority of the process, and the most significant 15 bits indicate a word in memory that identifies the process work area. In this example, the microcomputer assigns each process one of two possible priorities. High priority processes are given the name Pri=0, and low priority processes are given the name Pri=1. Each process descriptor is therefore a work area pointer.
1 formed by taking the "bitwise OR" of WPTR and process priority Pri
It can be seen that there are two words. At the same time, the work area pointer WPTR can be obtained from the process descriptor by performing a "bitwise AND" of the process descriptor and NOT 1. Process priority can be obtained by performing a "bitwise AND" of the process descriptor and 1. CPU Data Path and Registers Central processing unit 12 and its operation will be better understood with reference to FIG. Although FIG. 2 has been separated into FIGS. 2A and 2B for convenience, it should be understood that the diagrams in FIGS. 2A and 2B can be combined together to form register sets and data paths. . CPU 12 includes an arithmetic logic unit (ALU) 30 and a plurality of data registers. those registers
bus, Y bus, Z bus and bidirectional data
connected to the bus. the operation of those registers,
Interconnection to the bus is controlled by a plurality of switches, diagrammatically represented at 32. These switches 32 are controlled by signals derived from a microinstruction program contained in ROM 13. Communication between the CPU and memory occurs via a unidirectional address path 33 to a memory interface 14 and a data bus 31. As in the above patent application, each instruction consists of 8 bits. Four bits represent the desired function of the instruction and four bits are allocated for data. Each instruction obtained from the program sequence for a process is stored in the instruction buffer 3.
4, and the instruction is decoded by decoder 35. The output of this decoder is applied to a microinstruction register 37 via a condition multiplexer 36. This microinstruction register is a microinstruction register.
Used for addressing ROM13. The operation of the instruction buffer 34, decoder 35, condition multiplexer 36, MIR 37, microinstruction ROM 13, and switch 32 is generally described in the above patent application and the European patent specification.
It is as described in 0110642. Since this embodiment is configured to handle two sets of processes: a process with priority 0 and a process with priority 1,
Two register banks are provided. A register bank 38 is provided for priority 1 processes and a similar register bank 39 is provided for high priority 0 processes.
provided for the process. Both registers
Banks have similar register sets, and those register sets are connected to the X, Y, Z buses and the data bus.
Similarly connected to the bus. For simplicity, the registers and their connections are only shown in detail for register bank 38. In addition to the two register banks that are assigned specific priorities, the CPU also has a constant box 40, a register bank selector 41, and a second
Contains several other registers shown in Figures A and 2B. Those other registers are common to both priority 0 and priority 1 processes. Those registers are:

【table】

[Table] Holds the time when the file is ready
Register 85.
Bank 3 of registers for priority 0 processes
9 is the same as already mentioned for the priority 1 process. In the following description, the suffix [1] indicates a register associated with the priority 1 bank, and the suffix [0] indicates that the register is associated with the priority 0 bank. The suffix [Pri] indicates that if the priority is not known, the appropriate priority register for the process is used.
shows. These registers have a 1-bit flag, 4
Apart from registers 7, 48, 58, 59, 82, 83, and 84, the registers in this case have a total word length of 16 bits. Only one command at a time
If it is configured to hold one instruction, it can be eight bits long. A,
B, C register stacks 54, 55, 56 are:
It is the source and destination for most arithmetic and logical operations. They are organized as stacks. In addition to registers and flags, each bank 3
8 and 39 are configured to receive inputs from a valid time flag 84, a next time register 85, and a clock register 81. Timer logic 86 will be described in more detail below with reference to FIG. Clock register 81 receives input from process clock 87. Timer logic 86 for each register bank is
This constitutes the timer 9 shown in the figure. For processes of both priorities, OREG 57 in both register banks 38, 39 so that the portion of the instruction given to the OREG register reaches the decoder and is used to generate the appropriate microinstruction. is the decoder 35
connected to. Both priority banks' SNP flag 58, copy flag 59, insert flag 82, delete flag 83, and timer logic 86 are also connected to a condition multiplexer. The work area pointer (WPTR) of a process is
It is sometimes necessary to calculate an offset value from the location pointed to by the workspace pointer, since it is then used as the basis for addressing local variables of the process. Constant box 40 is connected to the Y bus and allows constant values to be placed on that bus under control of microinstruction ROM 13. They indicate offset locations within the process work area and can be used to provide time slice periods. To select one or the other of register banks 38 or 39, register bank selector 41 selects RPI flag 47.
, PROCPRI flag 48, and microinstruction
Receives input from ROM13. That register
The output terminal from the bank selector is connected to condition multiplexer 36, decoder 35 and switch 32. Depending on the output of the microinstruction ROM 13, the selector sets the PRI flag 47 or PROCPRI.
The register bank indicated by flag 48 is selected. Timer logic 86 is similar to each register bank. One of them is shown in more detail in FIG. Logic unit 86 has a subtractor 88. This subtractor receives input via line 89 from the next time register. This time value is subtracted in subtractor 88 from the time value supplied via line 90 from clock register 81. The most significant bit of the difference is sent to the inverter 9 via the output line 91.
given to 2. This inverter connects the signal to line 93
through a logic AND gate 94. The gate also receives input from valid time flag 84 via line 95. AND gate 94 sends the output to line 96
to the conditional multiplexer. The signal on line 96 is called the "timer request" signal and is configured to cause the processor to take a process from the top of the timer list so that the process from the top of the timer list can only be executed. Ru. This will be explained in detail later. Third
It will be appreciated that the logic diagram shown is configured such that a "timer request" signal is output on line 96 only when two conditions are met simultaneously.
Initially, valid time flag 81 must be set to a value of 1 and the time indicated by clock register 81 must be after or equal to the time indicated by next time register 85. Subtractor 88 is used to subtract the value contained in next time register 85 from the value held in clock register 81; if the result of the subtraction is a negative number; Since we are using two's complement signed values as described above, the least significant bit is 1. For this reason, line 90 is configured to output the least significant bit obtained by the subtraction, and when the result of the subtraction is positive and provides a 0 bit to line 91, AND gate 94 indicates a "timer request". Inverter 92 is required to only provide a signal. Memory Allocation for Process Work Areas As in the example described in the aforementioned patent application, a microcomputer divides its time between several processes and runs the processes together. Processes that are running together are called concurrent processes, and processes that are running at any given time are called the current process. Each concurrent process has an area of memory called a work area for holding local variables and temporary values handled by the process. 1st work area
The address of the local variable is indicated by the work area pointer (WPTR). This is shown in FIG. In FIG. 4, four simultaneous processes, processes L, M, N, and O, are in work areas 60 and 6.
1,62,63. Figure 4 shows the work area 60
is detailed and the work area pointer held in the WPTR register 51, in this example
Shows the 0 location, which is a single word location with an address shown as 10000. Other local variables for this process are addressed as positive offset addresses from the word pointed to by the work area pointer. Any workspace location with a small negative offset from the zero location is used for timing and communication scheduling purposes. In this example, below the 0 location indicated by WPTR, five additional word locations 65, 66, 67, 68, and 69 have negative offsets of 1, 2, 3, 4, and 5, respectively. It is shown with Those locations are as follows. Offset Offset name Location name -1 Iptr.s Iptr location -2 Link.s Link location -3 State.s State locaiton -4 TLink.s TLink location -5 Time.s Time location When a process is not the current process, Location 65 is used to hold a pointer (IPTR) to the next instruction to be executed by a process when it becomes the current process. Location 66 is used to store the work area pointer of the next process on the linked list or queue of scheduled processes waiting to execute. Field 67 may alternatively be used to contain an indication of the state of the process performing the input operation, or as a pointer to copy a block of data. Location 68 is used to store the work area pointer of the next process on the linked timer list of processes waiting a predetermined amount of time before being scheduled for execution and alternative timer input operations. It is also used to indicate the state of the process that executes. Location 69 is used to indicate the time after which the process can be executed. This memory also provides space for interprocess communication, and FIG. 3 shows such channels. Notation In the following description of how a microcomputer works, in particular its functions, operations and procedures, OCCAM (INMOS
The notation is used according to the trademark of International) plc) language. This term is a reference to the Programming Manual (OCCAM) published and distributed in the UK by INMOS Limited in 1983.
It is described in a booklet entitled. Furthermore, this notation is described in detail in European Patent Application No. 0110642, but will not be repeated in this specification for the sake of brevity. However, a description of OCCAM and a description of the notation described in European Patent Application No. 0116042 is included here for reference. In addition to the notation above, the following description illustrates certain memory access procedures defined as follows.

[Table] Procedures used by microcomputers The various procedures (PROCs) are shown below. The following nine procedures are used in describing the operation of the processor. Dequeue Run StratNextProcess HandleRunRequest HandleReadyRequest HandleTimerRequest BlockCopyStep Instert Step Delete Step The procedures "HandleRunRequest" and "HandleReadyRequest" and "BlockCopyStep" are described in detail in our pending PCT Patent Application No. PCTG84/00379 and European Patent Application. Those procedural definitions do not change for the present invention and are therefore not repeated in this patent application. The procedure "Dequeue" makes the process at the front of the process matrix scheduled with priority "Pri" the current process. If Pri=1, in order to let other processes run, it is
Set the time slice register 80 to the time at which the process must be temporarily stopped.
The length of the time slice is determined by a constant time length stored in definition box 40 as one of the constants.

[Table] The procedure “Run” has a descriptor of ProcDesc.
Schedule processes as contained in the register. As a result, the priority 0 process immediately starts execution in priority over any process with priority 1 that is already being executed. In the following description, all lines starting with ... are merely illustrative and do not form part of a definition.

【table】

[Table] The procedure ``StratNextProcess'' deschedules the current process and, if there is another executable process, selects the next executable process.
By doing this, if there are no more priority 0 processes to be executed, the interrupted priority 1 process can be restarted. Procedure "StratNextProcess" is always executed as a result of SNPFlag being set. Therefore, the first action in this process is to clear the flag.

The procedure "HandleTimeRequest" is executed as a result of a timer request on line 96 from one of the timer logic units 86. Assuming the request is for a priority 0 process,
A TimerRequest0 signal would have occurred and the processor would have set the ProcPri register to zero. If the request was for a priority 1 process, the TimerRequest1 signal would have been generated and the processor would have set the ProcPri register to zero. This procedure
Identify the process that has become ready from the content of the TPTR word. The procedure schedules the process if appropriate and sets the TPTR word, NextTimeReg and
Update ValidTimeFlag.

【table】

[Table] TptrLoc0 was used as a reference in the above definition.
one for priority 1 and one for priority 0,
You will notice that there are two Tptr locations.
They occupy contiguous memory locations and have address TptrLoc0 for priority 0. In this way, either location can be addressed by an offset of 0 or 1 from TptrLoc0, depending on the priority involved. The procedure "InsertStep" is executed as a result of InsertFlag "Prif" being set. The responsiveness of this procedure inserts the current process into the correct position in the timer list for the current priority level. The Breg[Pri] and Creg[Pri] registers identify the point by which the correct location search has been reached. When the insertion is done, the procedure sets InsertFlag[Pri]
, reset the timer registers appropriately, and run the next process.

【table】

[Table] The procedure "DeleteStep" is executed as a result of DeleteFlag[Pri] being set. The iterative performance of this procedure removes the current process from the timer for the current priority level. Breg
The [Pri] and Creg [Pri] registers identify the point by which the correct location search has reached. When the insertion is done, the procedure deletes DeleteFlag[Pri]
and reset the timer registers appropriately.

【table】

[Table] The processor performs a series of operations. Their operation is due to the current process or serial link 25
or due to a request made by timer 9. Priority 0 Processes Operations performed for priority 0 timers or communication channels that serve priority 0 processes are referred to as "priority 0 operations."
"Priority 1 operation" is defined accordingly. The operations that can be performed for the current process are the procedures "StartNextProcess", "InsertStep",
"DeleteStep", "BlockCopyStep" or fetch, decode and execute instructions. The operations that can be performed by the processor for serial links are the procedures "HandleRunRequest" and "HandleReadyRequest." These are described in detail in our aforementioned pending patent application. The operations that can be performed by the processor for timer 9 are described in the previously defined procedure "HandleTimeRequest". Each of those operations corresponds to a series of microinstructions. The last microinstruction in any sequence that makes up those actions is "NextAction." This causes the processor to select the next operation to perform. The method by which the processor determines which action to perform next when the "NextAction" microinstruction is executed is as follows. The synchronization control logic 10 sends at most one "RunReqest" or "ReadyRequest" to the processor at any given time. If there is a priority 0 request outstanding, the synchronization control logic will not send a priority 1 request. As a result, two signals are input to the conditional multiplexer. One of those signals indicates the presence of a request, and the other indicates the priority of that request. Two signals "TimerRequest0" and "TimerRequest1" are connected to the condition multiplexer. The condition multiplexer selects the currently selected SNPFlag58, DeleteFlag83,
It is connected to the signals from InsertFlag82 and CopyFlag59. Therefore, the selection can be made as follows. If SnpFlag[Pri] is set, the processor executes the procedure "StartNextProcess". Otherwise,
Assuming there is an action that can be performed, the processor selects the priority 0 action. Otherwise, assuming there is an operation that can be performed, the processor selects the priority 1 operation. Otherwise, the processor waits until requested by a timer or communication channel. The processor selects an action for a particular priority level Pri according to the following rules.
If DeleteFlag[Pri] is set, the processor executes "DeleteStep". Otherwise, if InsertFlag[Pri] is set, the processor executes "InsertStep". Otherwise, the processor handles any priority Pri channel requests. Otherwise, the processor handles any priority Pri timer requests. Otherwise,
If CopyFlag[Pri] is set, the processor executes the procedure "BlockCopyStep".
Otherwise, assuming there is a current process with priority Pri, the processor fetches, decodes and executes instructions. Instructions are fetched, decoded and executed as described in our European patent specification 0110642. The following description of the function set refers to four additional procedures: - TimeSlice InsertInTimerList DeleteFromTimerList IsThisSelectedProcess We will refer to relative times in the following definitions of these procedures. Clock register 81 is periodically incremented by one, increasing from the most negative value to the most positive value through successive cycles. The next increment of the most positive value returns that register to the most negative value. In the following explanation, (X after Y)
The expression means that X is later than time Y. All times (X+1) and (X+MostPos) are defined to be after X. (Clock
All time between (Clock Reg+1) and (Clock Reg+MostPros) is considered to be in the future, and (Clock
Reg and(-1)) and (Clock Reg+MostNeg)
All time between is considered to be in the past. The additional procedure definition is as follows:

[Table] It is done.

[Table] Functional set As in European patent specification 0110642,
Each instruction for the microcomputer includes functional elements selected from a functional set. The functions executed by the microcomputer include direct functions, prefixing functions pfix and nfix, and 1
indirect function opr that uses an operand register to select one of a set of operations
and is included. As in the above patent application,
Oreg after execution of all instructions except pfix and nfix
[Pri] is cleared. The improved direct function set and operation set of this application are as follows:

【table】

【table】

【table】

【table】

TABLE All functions and operations listed above, except those with code numbers 31-36, have already been defined in the pending patent application and will not be defined again in this specification. However, the function "jump" and the operation "loop end" have been defined again to allow the use of timer 9, which is now defined as follows.

[Table] Rescheduling a process after a certain amount of time has passed
To make a rule.

[Table] And.
Additional functions and “altend” are as follows.

[Table] Thing.

【table】

【table】

【table】

[Table] Purpose: To start execution of selected components of a selective process. It will be appreciated that the microinstruction ROM 13 contains microinstructions corresponding to all of the above functions and operations such that the microinstructions retrieved from the ROM 13 cause the processor to perform any of the above operations. . A scheduled processor divides its time between several concurrent processes running at two priority levels, 0 and 1. Priority 0 process and priority 1 process
Assuming that processes can be executed together, a priority 0 process always executes with priority over a priority 1 process. Only one process is actually running at any given time, and this process, the current process, has a work area pointer (WPTR) in the WPTR register 51 and an instruction pointer (IPTR) in the IPTR register 50 that The next instruction to be executed from the instruction sequence in the flange related to the process is shown. Any process that is not the current process and is not waiting to run is descheduled. When a process is scheduled, it either becomes the current process or is added to a list or queue of processes waiting to run. Such a scheduled list is formed as a linked list and has a pointer to the work area of that process. The instruction pointer (IPTR) of any process on that list is stored in the IPTR location 65 of its work area, as shown in FIG. In this case, the processor may contain two lists of scheduled processes waiting to be executed. Each of these processes is for each priority level. In addition, two timer lists may be included for descheduled processes to wait a specified amount of time before being scheduled. One timer list is provided for each priority. Figure 4 shows a scheduled list with high priority 0,
Figure 5 shows a low priority 1 process when a certain priority 0 process is the current process as shown in Figure 4.
Shows the scheduled list of. In this case, since the current process is a process with a high priority of 0, the register bank selector 41 selects a register in the bank 39 to be used by the processor. Therefore, the WPTR register [0] is the work area 6 of the current process L, as shown in FIG.
Holds a pointer to the 0 location of 0. IPTR
Register [0] contains a pointer to the next instruction in program sequence 181 stored in memory. Registers 54, 55, 56, 57 shown in FIG. 4 contain further values to be used during the execution of the next process L. The scheduled list of priority 0 processes waiting to be executed is illustrated in FIG. 4 by three processes M, N, and O. The work area of those processes is 61,
Diagrammatically shown at 62, 63. Each of these work areas is generally similar to the work area shown for process L. shown in 53
FRTR register [0] contains a pointer to the work area of process M, which is the first process on this list. The work area of process M is its IPTR
Location 65 contains a pointer to the next instruction in the program sequence to be executed when process M becomes the current process. Process M's link location 66 contains a pointer to the work area of process N, the next process on the list. The last process on the list shown is process O. The process O has a work area indicated at 63. indicated by 52
The BPTR register 52 indicates that this last process O
Contains a pointer to the work area of . The work area 63 of this process O is the ring location 6 of the previous process N.
6, but in this case process O is the last process on the list, so
Process O's link location 66 does not include a pointer. When another process is added to this list, a pointer to that other process's work area is
Since it is placed in the BPTR register, the process O
The link location 66 of contains a pointer to the work area of that other process added to the list. The priority 1 scheduled list is generally similar and is shown in FIG. In this case, the list of priority 1 processes that are scheduled and waiting to be executed consists of processes P, Q, and R. Another priority 1 process, designated by the symbol S, is shown, but it has now been descheduled and no longer forms part of the linked list. FPTR register [1] contains a pointer to the work area of process R, which forms the first process on the list waiting to execute. BPTR register [1] contains a pointer to the work area of process R, which forms the last process on the scheduled list. Each process P, Q, R has an IPTR that points to the program stage in its IPTR location. When the program becomes the current process, the next instruction is taken from that stage. The link location of each process on the scheduled list except the last process contains a pointer to the work area of the next process on the list. A process can be picked from the top of the list for execution by using the procedure ``deque'' defined above. A current process can be descheduled using the procedure ``start next process'' defined earlier. The way to operate the two scheduled process lists shown in Figures 4 and 5 is as follows:
It has already been described in the said patent application and will not be repeated. However, if the current process is a low priority process, then the "time slice"
After a period of time, called Gives the ability to slice time.
When a low priority process is taken from the top of a scheduled list of the kind shown in Figure 5, the processor calls the procedure ``duque''.
As shown in lines 11 and 12 of the procedure definition, if the process is a priority 1 process (this is the case for low priority processes), then according to line 12, Time slice register 80 is loaded with a value that is the sum of the current time indicated by clock register 81 and the determined "time slice length" time.
The length of the time slice can be chosen to suit any time interval, in this case taken to be the time required to execute 1000 instructions. This can of course be changed as required.
This time slice is stored in constant box 40. When a low priority process performs a ``jump'' function or a ``loop end'' operation, the processor executes the procedure ``time slice''. According to the above definition of the procedure "time slice", the priority of the current process is 1,
If the time indicated by the clock register is equal to or later than the time indicated by time slice register 80, the work area pointer and the priority of the current process are loaded into procedure description register 46 and the priority 1, so that adding it to the end of the scheduled list causes that process to be rescheduled.
The processor checks whether the procedure ``run'' is executed. The process stops running the current process,
If there is no higher priority process or request for action by the processor, the procedure causes execution of another process to begin at the top of the priority 1 scheduled list.
Set SNPFlag58 to the value 1. This embodiment also provides for timer lists of the type shown in FIGS. FIG. 6 shows a linked timer list for a low priority 1 process, and FIG. 7 shows a similar linked list for a high priority 0 process. Low priority processes are indicated in Figure 6 by the letters T, U, and V.
The high priority processes in FIG. 7 are given the letters W, X, and V. Since the two lists are generally similar, only the list in FIG. 6 will be discussed in detail. A work area 60 for each process in the list is shown in FIG. Ahead of the timer reset is maintained by a single word memory location 90 that holds a pointer value called TPTR. When there are no processes on the timer list for a particular priority, the TPTR for that priority is set to the special value "NotProcess.p". Otherwise,
The TRTR held in memory location 90 links all processes in its timer list in chronological order. Each process work area has a time location 6 indicating the time at which the process can be scheduled.
Indicates a value within 9. Each process workspace's TLink location 68 contains a pointer to the 0 location of the next process' workspace on the timer list. Each process work area location 65 on the list stores a pointer to the next instruction in the program sequence 181 for use when the process is scheduled to become the current process. Valid time flag 8 when process is on timer list
4 with a value of 1 and has a value of 0 if there are no processes on that timer list. Next time register 85 contains the time taken from the process's location 69 at the front of the timer list. Thus, register 85 is included to indicate the earliest time any process on the associated timer list should be scheduled. There are no registers provided for the timer list to indicate the tail of the list. The work area of the last process on the timer list is ILINK location 68 of its work area.
It has a special value "NotProcessp" inside. The front of the list is indicated by using memory locations 90 rather than registers. In this way, the front of the list is identified by using memory locations in the same way. This is because all intermediate entries to the list are identified, thereby allowing the insertion of another process into the timer list in chronological order or the release of another process on the timer list. This is because it simplifies the operations necessary for this purpose. It may be necessary to insert a process before the first existing process on the timer list, or insert a process halfway through the list depending on when the process to be inserted should be scheduled. You will find that there are times when this is necessary. As can be seen from the previous discussion of the timer logic shown in FIG. 3, any valid time flag 84 is set to a value indicating that the program is on the appropriate priority timer list. Then, the timer logic shown in FIG. 3 clocks the time shown in next time register 85 (representing the first time to schedule any process on the list). Compare with the time indicated by the register,
And assuming the time to schedule that first process has been reached, the timer logic provides the appropriate request signal to the conditional multiplexer. The processor then responds to those request signals by removing the first process from the appropriate timer list and updating the appropriate valid time flag, next time flag, and TPTR location 90.
This will then reflect the new state of the timer list. The value "TimeSet.p" is written to the TLINK location 68 for the process work area to indicate that the process is no longer on the timer list. Assuming that the process is no longer the current process or is already on the scheduled list, it will be placed on the scheduled list of the kind shown in Figures 4 or 5. Becomes the current process if no list has been added or scheduled. The processor action of removing a process from the top of the timer list is described in the definition "HandleTimerRequest" above. TIMER INPUT INSTRUCTION A process loads a time such that after that time the process must be rescheduled to the A register 54.
An instruction containing "TimerInput" can be executed, and then the operation "TimerInput" is executed. First, check whether the current time indicated by the clock register is after the time indicated by the A register, and if so, no action is taken so that the process remains scheduled. do not have. However, if this condition is not met, the sequence described in the definition of "TimerInput" occurs and the special value "Waiting.p" is written to state location 67 of the process work area. Since the time at which the process should be rescheduled should be after the time indicated in the A register, the time indicated in the A register is incremented by one.
Indicates the time at which the process should be rescheduled. The processor executes the procedure "InsertInTimerList". This procedure writes the time location 69 of the process work area to the time at which the process is to be rescheduled and places the process in the appropriate timer list position so that the process follows temporal order. It also sets SNPFlag to the value 1 so that the processor starts executing another process. The instruction that executed the "TimerInput" instruction will be rescheduled when the appropriate amount of time has elapsed. Selective timer input command (Alternative
Timer Input Instrument
ons) Another process is described in the pending patent application. The other processes select one of several other components for execution.
Each separate component consists of an input or skip to which the corresponding process connects. This example shows a timer alternative process.
process), which selects one of several different components for execution. Each component of a separate timer can consist of a message channel input (from an internal or external channel) and a skip or timer input followed by a corresponding process. The message channel input component can be selected if the channel is ready, and the skip component can always be selected as described in the aforementioned pending patent application. The value in the clock register is “after” the time specified by the timer input.
(AFTER), you can select the timer input component. This example performs another process that does not rely on timer inputs in exactly the same way as previously described in the pending patent application. The description thereof will not be repeated in this specification. When the current process has several other components, each component is examined to determine if one or more of those components can be selected. If no components can be selected, the process is descheduled until one of the components can be selected. The process is then rescheduled, the components are examined again, and one of the components is selected. Examination of the message channel input component and the skip component is performed as described in the aforementioned pending patent application. When all components have been examined, the state location 67 of the process work area contains one of two special values: "Enabling.p" or "Ready.p".
Assuming state location 67 contains "Ready.p", then and only one of those components can be selected. While examining the timer input component, TLink68 and time location 6
9 are used for special purposes. TLink location 6
8 takes one of two special values: "TimeSet.p" or "TimeNotSet.p". it is,
It is initialized to ``TimeNotSet.p'' to indicate that no timer inputs have been examined, and changes to ``TimeSet.p'' when the first timer input is examined.
When the first timer input is examined, time location 69
is initialized at the specified time. Thereafter, as each timer input is examined, if the time is earlier than the time recorded in time location 69, the time location is updated to the specified time. Therefore, once all components have been examined, time location 69 holds the earliest time specified by any timer input. Only when TLink location 68 contains the value "TimeSet.p" and the value of the clock register is after the time in time location 69 can another process select the timer input component. A timer selective process determines whether any component can be selected using state location 67, TLink location 68, and time location 69 after all components have been previously viewed. If no component can be selected, the process is descheduled; if any timer input component is examined, the process is placed on the appropriate timer list. Assuming there is at least one component available for selection, each component is examined again and the first selectable component is selected. As described in the aforementioned pending patent application, location 0 of process work area 60 is used to record the component, if any is selected. Retesting of the channel input connector and skip components is performed as described in the aforementioned pending patent application. Re-inspect the timer input component at TLink location 6
8 and time location 69 as follows. If a timer-selective process is not on the timer list when the first timer input component is reexamined, then either the process was placed on the timer list and subsequently removed, or the process is not on the timer list at all. Either it wasn't there or it wasn't. In the former case, time location 69 includes the time when the early timer input component became selectable. In the latter case, immediately after examining the component process, time location 6
9 contains the value "CLOCK REG". The time and place are
Holds the same value for all retests of the timer input component. A timer input component is selectable only if the contents of time location 69 are "after" the specified time.A timer-selective process is placed on the timer list as before when the first timer input component is reexamined. If there is, there is no selectable timer input component, but there is always a selectable channel input component. In this case,
The first re-examination of the timer input component removes the process from the timer list and TLink location 6
Set the value "TimeNotSet.p" to 8 to prevent selection of any timer input component. In this case time location 69 is not used. The instructions that perform the timer selective process are "timer selective start" (timer selective start) followed by "timer enable" for each timer component.
alternative start). If the message channels are included in another structure, the processor also performs a "channel enable" for each and every message channel.
This is followed by "Timer Selective Wait" (timer selective wait).
alternative wait)' followed by 'timer disable' for each timer input,
Followed by ``Channel Disable'' for any channel input. The first instruction executed by a timer-selective process is the "timer selective start" operation, and as can be seen from the definition of this operation, the special value "enabling.p" is set for the process according to the second line. According to line 3, a special value "timeNotSet.p" is written to the TLink location 68 for the process work area. As stated in said pending patent application:
Any channel input component and any skip component are examined by the "channel enable" and "skip enable" operations. By loading the guard value into the A register, loading the specified time for the timer component into the B register, and then performing a "timer enable" operation.
Any timer input component can be examined.
According to the definition of that operation, lines 2 and 3 check whether the guard value in the A register is false. If it is false, the timer input is ignored and the instruction has no other effect. If the guard value is not false according to line 5 of the definition, the processor executes the sequence starting at line 7 of the definition. This loads the value obtained from TLink location 68 into the O register, and line 8 indicates that the value is either "TimeNotSet.p" according to line 9 or "timeSet.p" according to line 13. An inspection is carried out to test whether there is. If we find that the value is "TimeNotSet.p", then the value "TimeSet.p" is 11
The time indicated in the B register is written to the time location 69 for the process work area as required by line 12 of the definition. This occurs for the first timer input component examined by the process. The condition on line 13 may be satisfied for subsequent timer inputs that are examined. In this case the sequence according to line 14 occurs. The time value recorded in time location 69 for the process is O register 5
Line 15 asks that the time value be loaded into 7 and that the time value be tested to see if it meets the conditions in line 17 of the definition.
If the time is "after" the time indicated in the B register, then the time in the B register is written to time location 69 for the process.
Lines 19 and 20 indicate the time indicated in the O register "after" the time indicated in the B register.
If not, no action is taken.
Finally, the value from the C register is loaded, as required by line 21 of the definition. In this manner, the process examines each possible timer input, and the process's time location 69 is updated so that it contains the time of the earliest time component after examination. Therefore, a series of (timer enable) operations for each timer component effectively determines the earliest time of any component and places time location 69 at the earliest time of any component examined. You can see that it will be updated sequentially. The process then executes the operation "Timer Selective Wait." According to the second line of the definition, this initializes the 0 location of the process work area to -1 and then tests to determine which components of the alternative process are already selectable. According to lines 3 and 4 of the definition, it reads the value from TLink location 68 into the B register and the value from time location 69 into the A register. Lines 5 and 6 indicate that if the process has the value ``Timeset.p'' and the clock register indicates a time ``after'' the time indicated in time location 69, then lines 8 and 9 A special value ``Ready.p'' is written to the state location 67 for the process, requesting that the defined sequence occur, and the current time indicated by the clock register is the time for the process. Written to location 69. The process is not descheduled and can move on to its next instruction. However, if the condition in line 6 of the definition were not true, then the process would
Move to line. It loads this into state location 6 for the process by loading it into the C register.
The 14th row tests the contents of 7 and whether it contains the value "Ready.p". If so, according to line 16, the current time indicated by the clock register is written to time location 69 for the process and the process is not descheduled. Instead, for another of the inputs it is ready and the process can move on to the next instruction. However, according to line 16 of the definition, the special value 'enbling.
p'' is found, this indicates that none of the alternative components are ready yet and the sequence starting at line 17 occurs. The special value "waiting.p" is written to the state location 67 for the process, and lines 19 and 20 test whether the process is waiting for the timer component. According to line 20, the process sets the value "TimeSet.p"
, the contents of the A register must be 1 to indicate when the process should be scheduled.
, and the procedure "Insert In Time List" is executed according to line 23. The process is then descheduled, but placed on the appropriate priority timer to include an indication when it should be rescheduled. According to line 24 of the definition, assuming the process does not have any timer components, the B register can have the value "TimeNotSet.p", which means that the process is not a timer input but a channel. Occurs when still waiting for input. In this situation, the sequence following line 25 occurs, the instruction pointer for the process is stored in IPTR location 65 in the process work area, and SNPFlag is set so that the process is descheduled.
is set to the value 1. Therefore, in the definition, lines 6-9 test whether the process is ready for timer input. Lines 13 and 14 test whether the process is ready for non-timer inputs, such as channel inputs; line 16 onwards is applied when the process is found not to be ready. The next instruction executed by a process when it is not descheduled or when it is later rescheduled is the operation ``timer disable'' for each timer component and any It will perform the operation ``Skip Disable'' on the skip component and the operation ``Channel Disable'' on any channel component. The channel input connector and skip component are retested by the "channel disable" and "skip disable" operations as described in the aforementioned pending patent application. The timer selective process reexamines the timer input component according to the definition of operation "timer disable." If a replacement component is to be selected by the process, the A register is first loaded with a code offset to indicate the required offset in the program sequence to place subsequent program instructions. If the guard is false, the process examines the contents of TLink location 68 for that process. There are three cases to consider. First, the TLink location can contain the value "TimeSet.p" according to line 10 of the definition, in which case the time in time location 69 is "after" the specified time in the C register. ”, then the component is selectable. This is the condition on line 14 of the definition, and if this condition is met, the process executes the procedure "IsThisSelected Process." According to lines 5 and 6 of the procedure definition, it checks whether the 0 location of the process work contains the value -1. If so, this component is selected and the code offset from the A register is loaded into the work area at location 0 according to line 8 of the definition. If location 0 of the work area did not have the value -1 according to line 10 of the procedure definition, then the component process is already selected and the current 1 cannot be selected. If the ``timer-disable'' operation finds that the TLink location 68 of the process contains a value other than ``TimeSet.p'' or ``TimeNotSet.p'', then this Corresponds to the situation on line 18. This will occur when the process is still on the timer list so that TLink location 68 contains a pointer to another process on the timer list. Therefore, the timer component cannot be selected because the process is still waiting on the timer list and is removed from the timer list by the procedure "Remove from timer list". This writes the value "TimeNotSet.p" to the TLink location 68 for that process. The "Timer Disable" operation can find that the TLik location contains the value "TimeNotSet.p" according to line 8 of the definition. In this case, TLink location 68 was set to this value by a previous "timer disable" operation executed while the process was on the timer list. Therefore,
The A register has a value according to line 9 of the definition.
MachineFALSE. Once all of the alternative components have been re-examined, the process performs the operation "Alternative End", which, by definition, returns the code stored at location 0 in the process work area. First load the offset into the O register, then adjust the pointer value in the IPTP register with the offset in the O register.
This causes the process to select the next instruction in the program sequence at the appropriate offset to the selected alternate process. Various examples of processes are described below. Example 1 First, consider a priority 1 process executing a "timer input" instruction in a situation where the process is not descheduled. for example,
The A register can be loaded with a value, for example 14, indicating that the process wishes to be spun when the clock register contains a "after" value of 14. Assuming that the instruction is executed when the clock register contains the value 20, the process follows the first two lines of the "timer input" definition so that the value in the clock register is indicated in the A register. Find out if it is after. In this example, that condition applies, so the process continues without descheduling the process. Example 2 This shows the operation of a "timer input" by a process being descheduled.
See Figures 9A-9D. The figures illustrate changes in various word locations and the contents of various registers for process X's work area 60. FIG. 9A shows the position immediately before execution of the "timer input" command. A register 54 contains the value 30 indicating that the process wishes to be scheduled only when the time in clock register 81 is after 30. The clock register currently contains a time value of 20 and the valid time flag 84 is 0.
is set to indicate that there are no processes on the priority 1 timer list. When a ``timer input'' operation is performed, the contents of the clock register are compared to the contents of the A register. The special value "waiting.p" is written to state location 67 of process Like, A
The value in the register is incremented. The process is then inserted into the timer list and the position is as shown in Figure 9B. This means that the clock registers have now been increased to 22. Valid time flag 84 is now set to a value of 1 to indicate that there is at least one process on the timer list. next time register 8
5 contains the value 31. This value is a matter of scheduling the first process on the timer list. TRTR location 90 is process X, the first (and only) process on the timer list.
Contains a work area pointer. The work area of process - Indicates that it is the last process on the list and includes the value 31 in location 69 to indicate the time the process can be rescheduled. When sufficient time has elapsed and the clock register has increased to a value of 31, the position will be as shown in Figure 9C. Since the clock register value is now equal to the value of the next time register and the valid time flag is set to a value of 1, the timer logic issues a time request to the process. This causes the processor to load the value 1 into PROCPRI and execute the "HandleTimeRequest" procedure. This causes process X to be scheduled, clears the reasonable time flag, and
TPTR time 90 is set to "not process.p". This is the position shown in Figure 9D. Example 3 This illustrates how the insert flag 82 can be used to cause a process to be inserted into the timer list in the correct position and time order. Process P performs a timer input operation that causes it to be descheduled. Assume that process P is a priority 1 process and is the only process running. In addition, priority 1 timer
Assume also that there are three other processes waiting on the list. These three processes are process X waiting for time 25, process Y waiting for time 26, and process Z waiting for time 29. FIG. 10A shows the position immediately before executing the timer input command. Process P is running and the A register contains time 27. Clock, register contains time 20. The valid time flag is set to a value of 1 to indicate that the timer list is in use, and the next time register contains a value of 25, where 25 is the time associated with the fastest process on the timer list. It can be seen that there are three processes on the timer list. TPTR location 90 contains a pointer to process X, the first of the processes. Process X
The TLink location 68 of contains a pointer to the second process, and process Y contains a pointer to the third process Z. TLink location 6 of process Z
8 contains the special value "Not Process.p". It indicates that process Z is the last process on the timer list. It can be seen that the timer list is ordered with the earliest processes first and the most recent processes last. Process P
executes the timer list input instruction, the clock register and the A register are compared, and since the clock register is not yet "after" the A register, the special value "waiting.p" is placed in process P's state location 67. , the A register is incremented by 1, and the procedure "insert timer list" is executed. This writes the value in the A register to time location 69 in process R's work area, sets the B register to the point in TPTR location 90, and
The C register is set to the contents of TPTR location 90. The timer input command is then finished and the state location is as shown in FIG. Once the insert flag is set to the value 1, the next action performed by the processor is the procedure ``insert''.
"step". As can be seen from the definition of this procedure, this causes T register 49 to be loaded with the time associated with process X (ie 25) and compared to the time associated with process P (ie 28). Since 28 is ``after'' 25, we have not yet found the correct place to insert process P into the timer list, and the ``insert step'' procedure sets the B register to a pointer to process X's TLink location 68; The C register is forced to set the contents of that location. Then, after completing the procedure, insert
Leave flag set. The resulting situation is shown in Figure 10C. The next action of the process is to execute the procedure "insert step" again. This is performed in a manner similar to that described above, resulting in the situation shown in Figure 10D. Again, the next action of the processor is the procedure ``insert
step”. But in this case, since the time associated with process Z (i.e., 29) is after the time associated with process P (i.e., 28), the processor clears the insert flag and transfers process P's work area pointer to process Y. of
Insert process P between processes Y and Z in the timer list by writing to TLink location 68 and writing process Z's work area pointer to process P's TLink location 68. It then resets the processor's next time register 85 to the time associated with the first process on the timer list and sets the valid time flag to a value of one. Finally, the processor writes process P's instruction pointer to process P's EPTR location 65 and writes SNPFlag
58 to the value 1 to cause process P to be descheduled as the processor's next action. Example 4 This shows a timer-selective process X with three timer input components. Processor X is the only executable process, Process X has priority 1, the first timer input component is 26, Process X has priority 1,
Assume that the first timer input component is 26 and the second timer list input component is 25. This is illustrated in Figures 11A-11C. They show the subsequent status for work area locations 67-69 of process work area 60. FIG. 11A shows the position immediately after execution of the "timer selective start" instruction. Status location 67 contains the special value "enabling.p" and TLink location 68 contains the special value "TimaNotSet.p". The first “timer”
Immediately before the "Enable" instruction is executed, the A register contains the value Machine TRUE and the B register contains the time associated with this timer input, i.e. 26.
When the timer enable instruction is executed, the processor reads TLink location 68 and finds that it contains the value "TimeNotSet.p" indicating that there is no previously examined timer input component. Therefore, the processor uses TLink location 6
8 to the special value "TimeSet.p" and set the time location 69 to the value 26. This is the position shown in Figure 11B. Immediately before the second "timer enable" instruction is executed, the A register is set to the value
MachineTRUE and the B register has a value that is the time associated with the second timer input component.
Contains 25. When the timer enable instruction is executed, the processor reads TLink location 68 and determines that it contains "TimeSet.p" indicating that the time location contains the earliest time associated with the previous timer input component. find out Therefore, the processor reads time location 69 and determines that the time specified for this component, which is 25, is earlier than the time read from the time location containing the value 26. Therefore, the processor writes a new value to the time location, which is the 11th
It is as shown in Figure C. Example 5 This example, shown in Figures 12A-12C,
Figure 3 shows a timer-selective process P with two timer input components. This process P is not descheduled. Process P is the only executable process, Process P has priority 1
Assume that the time specified in the first timer input component is 26 and the time specified in the second timer input component is 25. The execution of the "timer selective start" instruction and the inspection of the timer input component are as described above in Example 4, and the situation immediately before the execution of the "timer selective wait" instruction is as shown in Figure 11C. It is. The first action of "Timer Selective Wait" is to write the value -1 to location 0 of process P's work area 60. This is the location used to select a component from multiple alternative components. Then, since the time in the clock register is "after" the time in time location 69, process P
The processor determines that the process can proceed. Therefore, the processor writes the special value "Ready.p" to state location 67 and the value of the clock register is written to time location 69. As a result of this, the second
The situation is as shown in Figure A, where the clock register has now advanced to the value 31. The position just before the first "timer disable" is shown in Figure 12B. The A register contains the offset from the "selective termination" instruction to the sequence of instructions in the flange associated with the first timer input component, the B register contains the value Machine TRUE, and the C register contains the offset associated with this timer component. Including the time that is 26. The process then executes the "timer disable" instruction. The instruction reads TLink location 68 and determines that it contains the value "TimeSet.p." Therefore, it reads the value 30 from the time location, and since 30 is "after" 26,
This timer input component is selectable. The processor then executes the procedure "InThisSelectedProcess" to select this component. This is because location 0 of the process work area still contains the value -1. The resulting situation is shown in Figure 12C. The second timer input component cannot be selected now, and when the selective termination instruction is executed, the process P
The working area for this is still as shown in FIG. Example 6 This example, shown in Figures 13A-13F,
Figure 3 shows a timer-selective process P with two timer input components. In this case, the process P is descheduled. Process P is the only runnable process, Process P is a priority 1 process, the time specified in the first timer input component is 26, and the time in the second timer input component is 26. It is assumed that it is 25. Example 4: Executing the “Timer Selective Start” instruction and checking the timer input component
The situation immediately before the execution of the "timer selective wait" instruction is as shown in FIG. 11C. The first action of the "timer selective wait" instruction is to write the value -1 to location 0 of process P's work area. The processor compares the value in time location 69 with the value in the clock register, finds that the process cannot continue due to certain timer inputs, and examines the process state location 67. This includes "enabling.p", so
The process is placed on a timer list and descheduled. This is the position shown in Figure 13A. The valid time flag is set to a value of 1 to indicate that the timer list is not empty. The next time register contains the value 26, which is the time that process P will be ready to run.
TPTR location 90 contains a poller for process P's work area and processes P's TLink location 68
contains the special value "not process.p" to indicate that it is the last process on the list. When sufficient time has elapsed, send a "timer request" signal to the processor as described in Example 2. The situation in which the signal is generated is as shown in Figure 13B. When the process is rescheduled, the position is as shown in FIG. The situation immediately before execution of the first "timer disable" instruction is as shown in FIG. 13D. When the timer instruction is executed, TLink location 6
8 is read and found to contain "TimeSet.p".
The processor then compares the time for this time component, 26, to the time shown in time location 69, which is also 26. Since 26 is not "after" 26, this component cannot be selected. Therefore, the processor
The instruction ends by loading MachineFALSE into the A register. Process P is in the 13th situation immediately before executing the second "timer disable" instruction.
It is as shown in Figure E. Execution of this instruction causes the component to be selected, resulting in the situation shown in FIG. 13F. Example 7 This shows a timer-selective process P with one timer input component and one message channel input component. Process P
Assume that is the only runnable process, that it has priority 1, and that the specified time is 40. There are no processes on the timer list, the channel referenced by the channel input component is initially "Ready", and the timer input component cannot be selected.
An example of this is shown in Figures 14A-14D. Process P executes a “timer selective start” instruction;
Load its registers appropriately and execute the "timer enable" instruction. As a result of this, the first
The situation is as shown in Figure 4A. “Channel Enabled” because the channel is “Ready”
The situation after execution of the instruction is as shown in FIG. 14B. The flange then executes the "Timer Selective Wait" command. The time in the clock register has the value 11. This time is not after the time 40 shown in time location 69 for procell P. Then the processor returns the value 'Ready.p'
, and therefore writes the time value in the clock register to time location 69. The situation after the completion of the "Timer Selective Wait" instruction is shown in FIG. 14C. The situation immediately preceding the "timer disable" instruction is executed as shown in FIG. 14D. Time value 12 in time location 69
The timer input component is not selected because is not "after" the time associated with the component. The process then executes a "channel disable" instruction that selects the channel input component. From the above example, when the "timer disable" instruction is executed, the time stored in time location 69 of the process will be used for all timers based on which the timer disable instruction is executed. It will be seen that the standard time remains constant with respect to the input. This allows the various timer inputs to be
Comparisons with times that change due to the passage of time as instructions are executed are avoided. Example 8 This shows a process P that is a timer-selective process with one timer input component specifying time 40 and one channel input component passing through channel 70. This example assumes there are initially two processes on the timer list. Those processes specify times 34 and 54. A message channel is not initially "ready" but becomes "ready" before the first process on the timer list becomes ready. To perform the timer selective process, the process executes a "timer selective start" instruction, a "timer enable" operation for one timer input component, and a "channel enable" operation for the channel 70. run first. The position is then as shown in Figure 15A. Process P has not yet been descheduled and is in "state" location 67
is initialized to ``enabling.p'' to indicate that the process is performing alternative input. TLink location 68 is set to the value "TimeSet.p" to indicate that the timer input has been examined. "Time" location 69 is set to the earliest time of any timer entry examined. The earliest time is 40 in this case, and this time 40 is the only timer input examined. The timer list has two descheduled processes X and Y with scheduling times 35 and 55, respectively. The processor then executes a "timer selective wait" instruction for process P. This is because no channel input was ready, and since the clock register includes time 11 in Figure 15A, it has not yet been time for process P to continue inputting the timer, so is inserted into the timer list and placed in the "state" location 67 of process P to be descheduled.
You will find out from This results in the position shown in Figure 15B. The linked timer list now has a total of three processes X, P, Y in chronological order. Channel 70 becomes "ready" after a certain amount of delay because the output process is attempting to output through that channel. Since that channel contains a descriptor for process P, process P becomes scheduled and loads its registers before executing the "timer destable" instruction, as shown in Figure 15C. situation. The process then performs a "timer disable" operation,
It reads the "TLink location" 68 for process P and determines that the process is still on the timer list because the timer list contains a workspace printer for the next pointer on the timer list. . Since process P is still on the list, the time has not yet come for its timer input component, so the timer component cannot be selected. Therefore, the A register is set to MachineFALSE,
The procedure "delete from timer list" is executed. This sets DELETE FLAG to the value 1, loads the B register with the pointer to TPTR location 90, and loads the C register with the contents of the TPTR location. Then, after the order was finished, the 15th
Leave the position as shown in Figure 0. DELETE FLAG
Since ``delete step'' is set to the value 1, the next action of the process is to execute the procedure ``delete step''. Since the TPTR location contains the workspace pointer of process X, that pointer will be the first workspace pointer of process '' is applied, and the C register does not contain process P's work area pointer. Therefore, according to lines 5 and 6 of the definition of "delete step", the process loads B with a pointer to the TLink location of process X, and loads the C register with the contents of the location pointed to by the B register, i.e. , a pointer to process P's work area, causes the process to step to the next process in the timer list. This is the situation shown in Figure 15E. From there, the procedure “delete”
Since "step" has finished and the DELETE FLAG is still set, the processor's next action is to execute the procedure "delete step" again. Therefore, it will now be seen that the condition in line 7 of the procedure "delete step" applies and the C register will now contain the workspace pointer of the current process, which is process P. This means that the list has now found the process to be deleted, and according to line 9 of the definition of "delete step"
DELETE FLAG is cleared to 0. This prevents further deletion steps from the timer list. 10 and 11 of the definition of "delete step"
TLink location 6 for process P according to line
8 with the value currently held (i.e. the workspace for process Y's workspace), then load the value from the C register into
Process P is removed from the timer list by writing to the location indicated by the B register, which is the TLink location. In other words, the contents of process X's TLink location are changed, replacing the pointer to process P's workspace with the pointer to process Y's workspace. after that,
The processor checks whether there are any remaining processes on the timer matrix according to line 13 of the "delete step" procedure. In that procedure, B.
A register is loaded with the contents of the TPTR location.
According to line 15 of the definition, this results in the value 'not process.
p'', there are no processes left in the list. From there, the valid time flag is set to zero according to line 17. On the other hand, if a value other than "not process.p" is found according to line 18 of the definition, then there is another process on the timer list and the B register is Time location 69 of the indicated process
The next time register is incremented by taking the time from . Finally, after deleting process P from the timer list, the value "TimeNotSet.p" is changed according to line 21 of the definition of procedure "delete step":
Written to TLink location 68 of process P. This results in the position shown in Figure 15F. Although process P is no longer on the timer list, it is still the currently scheduled process. Therefore, it executes the next instruction which is "channel disable". This finds the value -1 in the 0 location of process P's workspace, so channel 70 is selected for input to the process. A code offset is added to the instruction pointer for process P when the next instruction ``selective termination'' is completed so that the process moves to the correct part of the program according to the channel input selection. The appropriate code offset is loaded into the zero location of the work area. Example Program for a Process that Executes Selective Inputs from a Message Channel or a Timer This example program is configured to calculate the number of revolutions per second of a flywheel. The process consists of a channel called ``rotation'' and ``rps'' (which stands for revolutions per second).
is configured to communicate through two channels, one called a channel. 1 flywheel
The process is configured to input from the channel "rotation" each time it completes a rotation. The process can also receive timer input so that the process can respond to the occurrence of a predetermined time. In this example, the predetermined time period is a continuous passage of one second intervals. The process is configured to output the number of revolutions produced in one second every second through the channel "rps". In this program, the following additional notation is used: - The current value of the processor's clock is represented by NOW. occam is a process variable: =NOW assigns the current value of the processor's clock to the variable. The "timer" input is represented as: WAIT NOW AFTER t This input component waits until the processor clock holds time AFTER at time t.
Specifies that the process should proceed. The program for this process is below:

【table】

[Table] The first line of this program indicates that this process is
Specify to use one variable. One of those variables is called "Rotations" and is 1
Used to count the number of revolutions made per second. The other variable "EndOfInterval" is the current 1
Used to record the processor clock value indicating the end of a second. The second line specifies that the sequence is to follow what is described in lines 3-6. In the third line, the rotation count is set to zero. In line 4, the current value of the processor clock is read so that line 5 can calculate the processor value for the end of the second. The value 10000 used in line 5 is the number of processor clock increments in one second. Line 6 indicates that the selective process that follows between lines 7 and 14 should be repeated consecutively. Line 7 identifies the process as a timer selective process. Lines 8 and 10 describe two selective inputs. On the 8th line, a signal from the channel "rotation" can be input when the flywheel completes one revolution. If this input is selected, the corresponding process in line 9 is executed, and the execution of this process increases the number of rotations counted in the current 1 second. The timer input on line 10 can be selected when the current one second period ends. Assuming this timer input to a process is selected, the corresponding processes on lines 12, 13, and 14 are executed. The 12th line sends an output to channel "rsp" that shows the count of revolutions that occurred during one period.
Give through. Line 13 resets the rotation count to 0, and line 14 calculates the time at the end of the next 1 second period. The instruction sequence to implement this program is as follows:-

【table】

【table】

[Table] As shown in this command sequence, the first and second lines initialize the rotation count to 0. Lines 3 and 4 use the pfix function to run the load timer and read the processor clock. 6～
The 11th line is the subsequent pfix function and addition constant function (add
(constant function) is used to calculate the value of the processor's clock at the end of the 1 second interval. The timer selective input signal starts on line 13, and lines 13 and 14 are used to operate "timer selective start".
Use the pfix function. Line 15 loads the pointer into channel ``rotation'', and lines 16a and 17 use the pfix function to activate ``channel enable''. Line 18 is the variable "EndOfInterval"
Load. Line 19 loads the guard value,
Lines 20 and 21 use the pfix function to operate "timer enable". Lines 22 and 23 execute "timer selective standby". Lines 24 to 27 examine the channel input. Line 24 identifies the channel "rotation". The 25th line is the guard value
Load MachineTRUE. Line 26 loads the instruction offset needed when the channel input is selected. Lines 26a and 27 execute the operation "Channel Disable". 28
~Line 32 examines the timer input. Line 28 loads the variable "EndOfInterval". Line 29 loads the guard value, line 30 loads the instruction offset needed when the process selects the timer input, and lines 31 and 32 execute ``timer disable.'' 32a, line 33 Execute "selective termination". Line 35 is the first instruction executed when a channel input is selected. Line 45 is the first instruction executed when the timer input is selected. The invention is not limited to the details of the examples described above.