JPH02165286A - Computer driven by data - Google Patents

Abstract

PURPOSE:To widely compress a bit width for storing a destination node number in a program memory and to make a memory scale small by designating the destination node number using a relative address, for example, from an address for storing a current instruction. CONSTITUTION:The coincidence of a bucket 101 is detected using a matching memory 10 and outputted to a bucket 102, a node number <0> (103) at this time is inputted to a program memory 11. Thus, the 0th address of the memory is accessed, and an instruction code '+' and a destination node number <2> for the other party are read out and respectively written in an instruction code register 131 and a destination node number register 132. While the instruction code is directly outputted from the register 131, the number <2> is sent from the register 132 to an adder 13, added with the previously inputted number <0> (103) here, and an absolute value <2> 106 of the destination node number is obtained. Thus, a bucket 108 composed of the code '+', the number <2>, and data [G] from an instruction execution part 12 is supplied to the memory 10 again, and the whole of the program is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a so-called data-driven computer that employs a method of driving processing based on mutual dependencies between data to be processed.

[Conventional technology]

Typical examples of conventional data-driven computers are pages 19 to 22 of the Proceedings of the Conference on Research and Development Results of High-Speed Computing Systems for Science and Technology (June 25, 1980) and the IEEE
It is disclosed on pages 486 to 490 of the COMPCON '845 PRING proceedings (English). All of these publicly known materials describe the configuration and operation of a data-driven computer called Sigma-1. The prior art will be described below based on these publicly known materials.

FIG. 5 shows the configuration of the conventional data-driven computer mentioned above.

This data-driven computer has a network interface 14 that is an interface with the outside of the computer, a matching memory IO that detects two pieces of data with matching destination node numbers from each data to be processed, and a calculation command based on the node number. an instruction fetching section 15 for extracting the code, an instruction execution section 12 for executing arithmetic processing according to the instruction code, a destination specifying section 16 for specifying the next destination node number of the data after the arithmetic processing, and a data path connecting them. It consists of

In addition, Figure 4 is a program (data flow graph) for explaining the specific operation of a conventional data-driven computer.
This is an example.

This data flow graph connects data A and B to node #
0, and add this resultant data G and another data C
are multiplied at node I2 to obtain the resulting data ■, and on the other hand, data D and E are added at node 1), and the resulting data H and another data F are multiplied at node I4.
Multiply at node #7096 to obtain the resultant data J... Then, multiply data W and The configuration is such that result data Z is obtained.

Packet (data with tag information) A (201) input from the outside via the network interface 14
) is composed of destination node number <0> and data [A]. This packet 201 is sent to the matching memory 10, but at the same time, the destination node number <0> (203) in the packet 201 is also sent to the instruction fetching unit 15. Assuming that packet B containing data [B], which is the target of the binary operation on data [A], has already been input and is waiting in the matching memory IO, the destination nodes of these two packets A and B are Since they both match in IO, the matching memory 10 outputs a packet 206 that is a pair of data [A] and data [B].

On the other hand, the instruction fetching unit 15 reads and outputs the instruction code "+" (205), which is the content of the address corresponding to node number <0>.

The memory configuration of the instruction fetching section 15 is shown in FIG. 6 fat.

Next, the destination node number input to the instruction fetching unit 15 <Q
> is sent as is to the destination specifying unit 16 as the node number <0> (20). Further, the instruction code r + J (205) read out by the instruction extraction unit 15 is given to the instruction execution unit 12 as a packet 207 together with the packet 206 of the data pair [A] and [B]. At this time, in the destination specifying unit 16, the result data of the addition which is the operation corresponding to the node number <0> in the data flow graph of FIG. 4 represents the next node l12 to go to <2
> (208) is read out.

The memory configuration of the destination specifying section 16 is shown in FIG. 6('b).

At the same time, in the instruction execution unit 12, [A]+[B]
The calculation is performed, and the calculation result data [G] (209)
is output. The output 208 of the destination specifying unit 16 and the output 209 of the instruction execution unit 12, that is, the destination node number <Q> and the data [G] pass through the network interface 14 as a packet 210, and are sent to the instruction fetching unit 15 and the matching memory again. Sent to 10.

Through the chain of processing as described above, operations corresponding to all nodes of the data flow graph shown in FIG. 4 are performed, and the execution of the program is completed. At this time, the processes at the nodes where there is a data dependency relationship, for example, node IO and node I2, can only be executed sequentially in this order.
Nodes with no data dependencies, e.g. node l
The processing at IO and node #1 can be executed in parallel as long as the processing vt source allows.

Note that a data dependency relationship here refers to a connection relationship between two nodes in which input data necessary for processing the other node is supplied only when the processing of one node is completed. It refers to something.

The memory configurations of the instruction fetch section 15 and destination designation section 16 are shown in FIGS. 6+a+ and 6, respectively, as described above. The bit width of each piece of information is not clearly described in publicly known materials, so here, the bit width of the instruction code is 4 bits,
It is assumed that the bit width of the destination node number is 16 bits. Furthermore, since the above-mentioned publicly known materials do not have any specific description regarding data copy operations, it was assumed that a widely and generally known method would be used for data copying.

The 7th most significant bit “C” in the memory in the destination designation section 16
0PY" is a copy bit, and when the calculation result at a certain node in the data flow graph shown in Figure 4 is sent to multiple nodes, data is copied and the destination node number is assigned to each data. For example, in response to the operation result at node #2 being sent to both node #7097 and node #5, the copy bit at the second address of the memory is “l”. In this case, the destination node number #7097 is read out, added to the operation result [1) and output, and then the next address (third address) is read out continuously and the destination node Number 1)5 is added to the same calculation result [1) and output.

[Problem to be solved by the invention]

By the way, the conventional data-driven computer as described above has a problem in that the scale of the program memory becomes large.

In the case of the Neumann type computer which is currently widely used, processing is performed sequentially according to the order written in the program, so the execution address is centrally managed by a single register called a program counter. Therefore, except for branch instructions, there is no need to specify the address of the next instruction to be executed (jump address), and programs with the same content can be stored in a smaller program memory than data-driven computers. can. On the other hand, in the case of a data-driven computer, each instruction is processed in parallel, so it is impossible to centrally manage execution addresses. For this reason, in a data-driven computer, in principle, for every instruction, the address of the next instruction to be executed (destination node number)
must be specified, which causes the size of the program memory to expand. Also in the conventional example mentioned above,
The destination node number occupies 16 bits out of the 21-bit bit width per instruction (instruction code 4 bits, 10 rows destination node number 17 bits).

In view of these circumstances, the present invention aims to reduce the hardware scale of a data-driven computer by compressing the program memory scale, and at the same time improves performance by shortening memory access time due to memory scale compression. This is not intended.

[Means to solve the problem]

The data-driven computer of this specification has a configuration in which the destination node number in the program memory is stored, for example, at a relative address from the storage address of the current instruction.

[Effect]

In the data-driven computer according to the present invention, the storage address of the next instruction to be executed is expressed as a relative address to the current instruction, so the storage address of the next instruction is the next one to the address of the current instruction. It is obtained by adding the relative address of the instruction.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on drawings showing embodiments thereof.

FIG. 1 is a block diagram showing the configuration of an embodiment of a data-driven computer according to the present invention.

The data-driven computer of the present invention includes a network interface 14 as an interface with the outside, a matching memory 10 as a match detection unit that detects two pieces of data with matching destination node numbers from each data to be processed, and a node. A program memory 1) that has two functions: extracting the code of an arithmetic instruction based on the number and specifying the next destination node number of the data after the arithmetic processing, as an arithmetic processing unit that executes arithmetic processing according to the instruction code. It is composed of an instruction execution unit 12, an adder 13 as an arithmetic means for updating the destination node number, and a data path connecting these.

The operation of the data-driven computer of the present invention when executing the program (data flow graph) shown in FIG. 3 will be described. The data flow graph shown in FIG. 3 is the same program as the program shown in FIG. 4 described above, but the node numbers are assigned differently for the purpose of explaining the present invention.

This data flow graph connects data A and B to node l.
The resulting data G and another data C are multiplied at node 12 to obtain the resulting data I, and on the other hand, the data D and E are added at node 1) and the resulting data G and another data C to node I
5 to obtain the result data J... Data W and X are multiplied at node #7096, and this result data Y and the previously obtained data ■ are added at node #7097 As a result, data Z is obtained, and so on.

A packet 101 input from the outside via the network interface 14 includes a destination node number 0>, data [A], and an instruction code "10".

In the data-driven computer of the present invention, two-cycle pipeline processing is performed. The first stage is the data waiting for the matching memo January 0. A packet lot input from the outside is sent to the matching memory 10, but at this time, the data [B
] has not arrived, the input packet IOI is temporarily stored in the matching memory and waits for the packet containing data [B] to arrive, or if the packet containing data [B] has already been received When the containing packet arrives and is stored in the matching memory, it is detected that the destination node numbers 0> of these two packets 7) match, and data [B] is stored in the input packet 101. The packet 102 with the added .

Among the information contained in the packet 102, the destination node number <Q> (103) is sent to the program memory 1) and the adder 13, which will be described later, and the remaining data [A].

[B] and the instruction code “+” are sent to the instruction execution unit 12 as a packet 104.

In the instruction execution unit 12, data [A] and [B] are added according to the instruction code "+", and the addition result data [G
] (107) is output.

On the other hand, the processing in the program memory 1) that is executed in parallel with the processing in the instruction execution unit 12 will be described below.

FIG. 2 shows the program memory 1) of the data-driven computer according to the present invention! It shows JI formation.

In the memory of FIG. 2, the most significant bit “E” of each word
XT” is an extended address flag to be described later.

The lower bit “C0PY” is the “C0PY” in the conventional example.
This bit has the same meaning as the "copy" bit.
If the bit is "1", this indicates that there are a plurality of destination nodes for the operation result, and that the instruction code and destination node number information regarding each of these destination nodes are stored at the next address or later.

The lower 4 bits following this “copy” bit contain the instruction code (OPECODE) to be executed in the next cycle.
is stored, and in the lower 6 bits, the destination node number is a relative address (R
NODE).

The specific operation of the data-driven computer of the present invention as described above will be explained.

When packet 101 is detected to match in matching memory IO and packet 102 is output, packet 10
The node number <O> (103) of 2 is input into the program memory 1). Accordingly, address 0 of the memory shown in FIG. 2 is accessed, the instruction code "+" and the relative destination node number 2> are read out, and the instruction code register (OPE-REG) 131 is read out. and destination node number register (DBST-REG) 132, respectively.

The instruction code is output as is from the instruction code register 131. On the other hand, the relative destination node number <2> is sent from the destination node number register 132 to the adder 13, and in the adder 13, the previously input input node number <
0 > (103) is added to obtain the absolute value of the destination node number < 2 > (106).

The instruction code “+” obtained in this way and the destination node number 2〉 and the data output from the instruction execution unit 12 [
The packet 108 composed of [G] is again supplied to the matching memory IO via the network ink face 14, and the entire program is executed by repeating such processing.

However, in the present invention, since the bit width of the program memory 1) that stores the relative destination node number is limited to 6 bits, the actual value of the relative destination node number is 255.
(=26-1), overflow occurs.

For example, this corresponds to the relative destination node number corresponding to the arrow from node #2 to node #7079 in the data flow graph of FIG. In such a case, by setting the most significant bit "EXT" of the program memory corresponding to each node number to "l", the next address can be used as the extended address focus area to store the overflowing digits. The present invention is configured so that this is possible.

Input data necessary for processing at node 2 in FIG.
G] and [C] are matched, the destination node number <2> and instruction code "+" are output from the matching memory 10.

A case where a packet composed of data [G] and [C1 is output will be described.

As described above, the instruction code and data are sent to the instruction execution unit 12, multiplication is executed, and result data [1] is output. In parallel with this, the destination node number <2> is sent to the program memory 1) and the destination node number is read out.

The detailed logical operation of the program memory 1) when the input node number is <N> is shown in the flowchart of FIG.

In this flowchart, rREAD Ml is an operation for reading address M in memory, and bits (6:0), etc. are bit strings consisting of bits 6 to 0, "E
XT” and “C0PY” represent the values of the extended address flag bit and copy flag bit in the program memory, respectively.

When a packet with destination node number <2> is input into the program memory 1), the second
The contents of the address are read (step S4).

Of the successively outputted contents, the instruction code "+" is written to the instruction code register 131, and the relative destination node number <4> is written to the lower 6 bits of the destination node number register 132, that is, bits (6:0). (Step S5
．． S6).

Since the "EXT" bit of the read word is 0m (step S7), adder 1 adds the value <4> of the instruction code and destination node number register and the input node number 2>.
The addition result of 3, <6>, is output as the destination node number (step S8).

At this time, the copy “focus” of the read word is “1”
Therefore, after incrementing the read address <2> (step 510) and clearing the loop count <L> and the contents of the destination node number register 132 (step S2.53), the third address, which is the address after the increment, is Read out (step 54).

As with the first read, the instruction code "+" in successive words and the relative destination node number <55>(="1) 0
1) 1'') are written to the lower 6 bits of the instruction code register 131 and the destination node number register 132, respectively (steps S5 and S6).'EXT of the read word
Since the ``bit is ``l'' (step S7), the read address is incremented (step 5ll), the contents of the fourth address are read, and the lower 10 bits of the read word are transferred to bit 15 of the destination node number register 132. to bit 6 (step 513).

Since the value of the EXT bit of the last read word is "1" (step 515), the current instruction code "+" and the contents of the destination node number register 132 < 7095
>(-"0001)01)101)01)1") and the input node number I2, the addition result <7097> is output (step S8).

Also, the value of the copy bit of the last read word is “
O'' (step 39), the series of processing for the input packet having node number <2> is completed.

As mentioned above, when the destination node number is given as a relative destination node number, even if the relative destination node number overflows beyond the predetermined bit width, the next address in the program memory is set to the extended address of the relative destination node number. Processing is completed by using the area as an area, and the present invention is applicable to programs of any size and to which node numbers are assigned.

Generally, since connections between nodes are local, it is considered that the relative destination node number rarely takes a large value, regardless of the program size.

In fact, for a test program consisting of 3987 nodes, we evaluated the statistical distribution of relative destination node numbers when node numbers were assigned in such a way that nodes closest to the input were given smaller node numbers. . The results are shown in the graph in Figure 8. The horizontal axis of the graph shows the relative destination node number, the vertical axis shows the cumulative frequency percentage, and the numbers for each section indicate the number of nodes included in that section. .

From the graph of FIG. 8, it is easily understood that about 90% (88χ) of the total have relative destination node numbers within address 63. In other words, the bit width of the relative destination node number is set to 6.
In terms of bits, this means that there is approximately a 10% possibility that the above-mentioned extension bits will be necessary.

While the bit width of the program memory in the conventional example is 21 bits (4 bits in the instruction fetch section + 17 bits in the destination specifying section), in the case of this embodiment it is 12 bits, which can be expanded when the present invention is implemented. Even if the number of extra words required to store addresses is about 10% from the above statistics, the memory size is compressed by (12×1.1)/21=40.63 times. In this embodiment, the program memory space is 16 bits, but this compression effect becomes more noticeable as the program memory space becomes larger.

For example, if the program memory space is 32 bits, expand the relative j destination node number space to 8 vias,
Even if we estimate that the proportion of extended address bits required is 20%, the memory size will be (destination node number 10 flag + instruction code), and if we substitute the actual number of bits, it will be multiplied by (32 + 1 + 4), which can be compressed to less than half. be.

Note that in the above embodiment, the relative destination node number is limited to a positive number to simplify the explanation, but by using a signed number (two's complement representation), a node number smaller than the output side node number can be used. It becomes possible to send data to a node with

As a result, the present invention can be applied to programs including repetitive structures.

Furthermore, in this embodiment, the overflow bit of the relative destination node number is assigned to the extension bit, but another method is to divide the program into pages and set the address within the page to, for example, 6.
It is also possible to use a method in which the relative page number is expressed in bits, and when a destination node exists beyond the page, a relative page number is assigned to the extension bit.

In the above embodiment, the instruction fetch section and destination specification section of the data-driven computer shown in the conventional example are integrated into one program memory, and this program memory is arranged in parallel with the instruction execution section, thereby eliminating redundant input. The hardware scale is reduced by omitting address latches, decoders, etc.

In this way, by arranging the program memory and the instruction execution section in parallel, the basic cycle for executing one instruction consists of ■ processing that can go to the matching memory, and ■ processing in the "program memory + instruction execution section". Since it is composed of two vibrating stages, it has a short basic cycle comparable to that of conventional data-driven computers, and can also keep the response time to a single command short.

〔Effect of the invention〕

As explained above, in the data-driven computer of the present invention, the destination node number in the program memory is specified by a relative address from the storage address of the current instruction, so that the destination node number can be stored. It is possible to significantly compress the bit width and reduce the size of program memory.

In general, data-driven computers are built on a computational model based on parallel distributed processing, and have the distinctive feature of autonomously executing multiple tasks in parallel without any special control. It is considered. However, in the case of the current system where the address of the program memory that stores each multitask is fixed,
Other tasks Tb that may share the program memory area with the currently executing task Ta cannot be executed at the same time even if there is free space in the program memory. Therefore, the reality is that current data-driven computers cannot fully utilize their inherent feature of multitasking.

In contrast, in the data-driven pointer of the present invention, the node numbers of all nodes are specified by relative destination node numbers from other nodes, so if there is free space in the program memory, absolute addresses can be used. Regardless, a new task can be externally loaded into any free space and executed in parallel with other tasks.

The above describes multitasking execution on one processor, but as shown in Figure 9, multiple data-driven computers (processors) I
In a configuration in which lO to IN are connected, individual tasks Ta, Tb, and Tc spanning each processor are
If each processor occupies the same program memory area, it is possible to perform multitask execution and task generation even for multiprocessors that communicate with each other in buckets via a network. High-speed parallel distributed processing using data-driven computers can be easily realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a data-driven computer according to the present invention, and FIG. 2 is a memory configuration of a program memory of the data-driven computer according to the present invention, and more specifically, the program shown in FIG. 3 is stored. FIG. 3 is a schematic diagram showing an example of a program (data flow graph) executed by the data-driven computer of the present invention, and FIG. 4 is a diagram of a conventional data-driven computer. Fig. 5 is a schematic diagram showing an example of a program (data flow graph) to be executed in a conventional data-driven computer. 6 (al is a diagram showing the memory configuration of the instruction fetching section in a conventional data-driven computer, and FIG. 6 (bl is a schematic diagram showing the memory configuration of the destination specifying section. FIG. 4 shows the memory contents when the program shown in FIG. The graph showing the distribution, FIG. 9, is a conceptual diagram showing a map of program memory in the execution state of multitask in a multiprocessor configuration. 10...Matching memory 1)...Program memory 12...Instruction execution Section 13... Adder In the figures, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A match detection unit that detects two pieces of data that have matching destination node numbers attached to each data to be processed; An arithmetic processing unit performs arithmetic processing according to the instruction code, and the content is read out using the destination node number attached to the data processed by the arithmetic processing unit as an address, and the data is processed based on the read content. In a data-driven calculator equipped with a program memory that updates a destination node number and an instruction code, the destination node number of the data processed by the arithmetic processing unit and the content read from the program memory using this as an address 1. A data-driven computer comprising: arithmetic means for performing a predetermined arithmetic operation between said arithmetic means, and the result of the arithmetic operation by said arithmetic means is used as an updated destination node number.