JP3015565B2 - Information processing device with parallel execution function for multiple instructions - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a function of executing a plurality of instructions in parallel, and more particularly to a method of executing a plurality of instructions having a register dependency.

[0002]

2. Description of the Related Art As an information processing apparatus for executing existing software at high speed, a plurality of instruction execution units are provided, and a plurality of instructions in an instruction sequence in the software are simultaneously (parallel).
(In the same cycle), and an information processing apparatus represented by a super scalar computer is known which does not shorten the time required for one cycle (ie, does not increase the clock frequency).

In the information processing apparatus having the function of executing a plurality of instructions in parallel, a case where instructions are simultaneously executed from a queue holding instructions equal to or more than the maximum number of instructions that can be executed in one cycle is executed one by one even if they are executed simultaneously. Fetched and executed the same instruction.

[0004] If the queued instructions have a data dependency, they cannot be executed simultaneously. For example, if the output data of a certain instruction # 1 becomes the input data of another instruction # 2, the instructions # 1 and # 2 cannot be executed at the same time. This is different from the case where the instruction # 2 is executed after the execution.

[0005] Even if there is no data dependency, if the registers have a dependency, all of the corresponding instructions cannot usually be executed simultaneously. For example, when instruction # 3 uses data held in one register and another instruction # 4 writes data to the same register, instructions # 3 and # 4 have no dependency on both data. , Cannot be executed simultaneously. This is because the value is written by the instruction # 4 to the register of the data to be used by the instruction # 3.

In order to eliminate such register dependence, different registers may be used. However, when existing software (program) has an instruction sequence that depends on registers, the software must be rewritten, which is extremely complicated. Also, even with newly created software, the number of registers that can be specified is limited by the size of the register specification field in the instruction word. It is likely to be used in the same register. In other words, if the number of registers that can be specified as an access target in an instruction word, in other words, the number of registers that can be recognized from software, is the same, even if the number of execution units is increased, performance degradation due to register dependence cannot be reduced, and registers that can be recognized from software cannot be reduced. If you try to increase the number, you must rewrite existing software.

[0007]

As described above, in a conventional information processing apparatus having a function of executing a plurality of instructions in parallel, instruction sequences having a register dependence cannot be executed simultaneously, and therefore, the instruction sequences are sequentially executed one by one. The problem is that the parallel execution function cannot be used to the fullest.To solve this problem, the software must be remodeled to arrange the instruction sequence so that it does not depend on registers, or it must be rearranged. In addition, there is a problem that a lot of manpower and cost are required.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object the purpose of sufficiently improving the parallel execution capability of a plurality of instructions possessed by a device without modifying the software even for software containing an instruction sequence having a register dependency. It is an object of the present invention to provide an information processing apparatus which can be executed by utilizing the information processing apparatus.

[0009]

SUMMARY OF THE INVENTION The present invention provides an information processing apparatus having a plurality of instruction execution units and capable of executing a plurality of instructions in parallel. Detecting an instruction having a register dependency with respect to the first register from at least one second register temporarily used as a substitute for the first register and an instruction sequence to be executed, and designating the instruction Means for temporarily replacing the first register with the second register, wherein a plurality of instructions having a register dependency are executed in parallel by using the second register. It is a feature.

[0010]

In the above arrangement, for an instruction having a register dependency resulting from the same first register specification, the instruction which is not specified by the instruction is replaced with the first register specified by the instruction. Register 2 (temporary register)
Are temporarily assigned. Since the allocation of the second register cancels the register dependency, if only the first register specified by the instruction word is used, a plurality of instructions cannot be executed in parallel due to the register dependency. Software can be executed by making full use of the parallel execution capability of multiple instructions of the device, and the performance can be improved.

[0011]

FIG. 1 is a block diagram showing a configuration of an information processing apparatus having a function of executing a plurality of instructions in parallel according to an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a memory for storing programs, data, and the like, and reference numeral 2 denotes an instruction queue for holding instructions fetched from the memory 1 in a fetch order. The instruction queue 2 includes a parallel execution unit 4 described later.
And can hold more instructions than the maximum number of instructions that can be executed simultaneously. When executed, the instruction held in the instruction queue 2 is removed from the instruction queue 2.

A cache memory (or an instruction cache) is provided between the memory 1 and the instruction queue 2, and instructions fetched from the cache memory are stored in the instruction queue 2.
May be stored.

Reference numeral 3 denotes a decoder for sequentially taking out instructions from the instruction queue 2 and performing a decoding process. This decoder 3
In order to execute a plurality of instructions in parallel (simultaneously), in addition to the well-known function of examining the data dependence and the register dependence of a target instruction, a register designated by the instruction is described later for an instruction having a register dependence. Control to replace with a temporary register.

Reference numeral 4 denotes a parallel execution unit for receiving a decoding result of a plurality of instructions by the decoder 3 and executing the plurality of instructions in parallel. The parallel execution unit 4 generates a plurality of execution units 4-1, 4-2, 4-3,... For independently executing the corresponding instructions based on the decoding result for each instruction given from the decoder 3. Have.

Reference numeral 5 denotes a parallel execution unit 4 (the execution unit 4-
1, 4-2, 4-3, etc.). The register unit 5 includes a plurality of general registers (registers A, B, C, and C) that are recognized by software running on the apparatus (that is, can be specified by a source or destination register specification field of an instruction word).
D) and a temporary register group 52 composed of a plurality of temporary registers (represented by registers α, β...) Which are not recognized by the software.

Reference numeral 6 denotes a replacement table having a plurality of entries. Each entry of the replacement table 6 includes a register name (register number) of a general register in the register unit 5 to be replaced by the decoder 3 and a temporary register in the register unit 5 used in place of the general register. , And setting fields of a valid flag (V flag) indicating whether or not the information of the corresponding entry is valid.

Reference numeral 7 denotes a data matching assurance circuit. The data consistency assurance circuit 7 guarantees data consistency by writing back the contents of the temporary registers in the register unit 5 to the general registers which are the replacement targets shown in the replacement table 6. Next, the operation of the configuration of FIG. 1 will be described by taking as an example a case where the instruction sequence fetched into the instruction queue 2 is as shown in FIG.

In FIG. 2, "add A, B,
The instruction # 1 indicated by "A" is an instruction to store the sum of the contents of both the register A and the register B in the register A, and the instruction # 2 indicated by "and A, D, D"
Is an instruction to store the result of ANDing the contents of both the registers A and D in the register D. The instruction # 3 indicated by “or C, E, A” is an instruction to store the result obtained by ORing the contents of the registers C and E into the register A, and “sub”
The instruction # 4 indicated by A, C, A "is an instruction to store the difference between the contents of the registers A and C in the register A.

Now, as a result of the instruction sequence being fetched from the memory 1 to the instruction queue 2 by an instruction fetch mechanism (not shown), the contents of the instruction queue 2 at the start of the cycle T0 are as shown in FIG. It is assumed that Here, the order of the instruction sequence in the instruction queue 2 is the order of fetching from the memory 1 and is the order of instructions created to be executed one by one in order.

Now, to execute the instruction sequence in the instruction queue 2 shown in FIG. 2A by the conventional method, four cycles are required as shown in FIG. 3B, and simultaneous execution is impossible. . The reason is as follows.

First, one of the operation data used in the instruction # 2 is stored in the register A, but the value of the register A cannot be determined unless the instruction # 1 (add instruction) is executed. That is, there is a data dependency between the instruction # 1 and the instruction # 2.

Second, since the register A in which the OR result is written by the instruction # 3 (or instruction) contains the operation data used by the instructions # 1 and # 2 (and instruction),
If the instruction # 3 is not executed after the execution of the instruction # 2, the instruction #
This is because the data of the register A used in the instructions # 1 and # 2 may be rewritten by the instruction # 3. That is, there is a register dependency between the instructions # 1 and # 2 and the instruction # 3.

Third, the value of the register A used in the instruction # 4 (sub instruction) cannot be determined unless the instruction # 3 (or instruction) is executed. That is, there is a data dependency between the instruction # 3 and the instruction # 4.

On the other hand, in the present embodiment, the instruction sequence in the instruction queue 2 shown in FIG. 2A is changed as shown in FIG.
It can be executed in two cycles as shown in FIG. This operation will be described in detail with reference to the flowchart of FIG.

In the cycle T 0, the decoder 3 sends the first instruction (# 1) and the second instruction (#
2) is compared to check its dependency, and the subsequent instruction (# 2)
Check whether the instruction has a data-dependent or register-dependent relationship with the previous instruction (# 1) (step S1).
1). If there is no dependency, the decoder 3 decides to execute both instructions simultaneously in the next cycle (first cycle) T1 (step S2).

On the other hand, when there is a dependency (here, data dependency) between the preceding instruction # 1 and the following instruction # 2 as in the example of FIG. Replaces the dependent register (register A in this case) with the subsequent instruction # 2
It is checked whether or not is designated as a source (step S3).

As shown in the example of FIG. 2A, when the source of the register (A) having a dependency relationship with the previous instruction # 1 is designated by the latter instruction # 2, the decoder 3 It is determined that the preceding instruction # 1 is to be executed in the next first cycle T1, and that the subsequent instruction # 2 is to be executed in the next second cycle T2, and that fact is internally stored (step S1).
4). Actually, information indicating the position of the instruction to be executed in the first cycle T1 in the instruction queue 2 is internally stored, or
For example, a flag bit specific to the position in the instruction queue 2 of the instruction executed in the cycle T1 may be turned on.

Next, the decoder 3 executes the above-described step S1 for the third instruction (# 3) and the preceding instruction (# 2) in the instruction queue 2, and the instruction # 3 is Check if there is a dependency or register dependency.

If the instruction # 2 is executed as shown in FIG.
When there is a dependency relationship (here, register dependency relationship) between the instruction and the instruction # 3, and the source of the dependent register (A) is not designated by the subsequent instruction # 3 (when NO is determined in step S3) Means that the decoder 3 sets all the register A designated portions of the instructions in the instruction queue 2 after the instruction # 3 (here, the destination register A designated portion of the instruction # 3,
Source and destination register A of instruction # 4
(Designated portion), and is replaced with the designation of an arbitrary temporary register in the temporary register group 52, for example, the temporary register α (step S5). The contents of the instruction queue 2 at this time are shown in FIG.
Shown in

Next, the decoder 3 sets the first
The instruction # 1 determined to be executed in the cycle T1 is compared with the instruction # 3 (in which the register A has been replaced with the register α) to check the dependency thereof. It is checked whether there is a data-dependent or register-dependent relationship (step S1).

If there is no dependency between the instruction # 1 and the instruction # 3 as in the example of FIG. 2B, the decoder 3 sets the instruction # 3 to the same first cycle as the instruction # 1. At T1, it is decided to execute them at the same time, and the fact is stored internally (step S2).

Next, the decoder 3 compares the instruction # 1 in the instruction queue 2 with the instruction # 4 (the instruction following the instruction # 3, in which the register A is replaced with the register α). Then, the dependence is checked to determine whether the instruction # 4 has a data dependence or a register dependence with respect to the instruction # 1 (step S1).

When there is no dependency between the instruction # 1 and the instruction # 4 as in the example of FIG. 2B, the decoder 3 sets the instruction # 4 to the same first cycle as the instruction # 1. At T1, it is decided to execute them at the same time, and the fact is stored internally (step S2).

Next, the decoder 3 compares the instruction # 3 and the instruction # 4 after the register replacement in the instruction queue 2 and examines the dependency thereof. It is checked whether there is a register-dependent relationship (step S1).

As shown in the example of FIG. 2B, there is a dependency between the instruction # 3 and the instruction # 4, and the source of the register (α) having the dependency is specified by the instruction # 4. If there is (YES determination in step S3), the decoder 3 executes the first instruction T3 in the first cycle T1 and executes the subsequent instruction # 4 in the next second cycle T2. The decision is made and that effect is stored internally (step S4). As a result, the content of the determination that the execution cycle of the instruction # 4 is set to T1 is released.

When the decoder 3 determines the execution cycle by comparing the last instructions # 3 and # 4 in the instruction queue 2, the decoder 3 executes the instruction to be executed in the first cycle T1, ie, the instruction #
1 and # 3 are taken out of the instruction queue 2 and decoded, and the decoding results of the instructions # 1 and # 3 are executed by the execution units 4-i and 4-j (i, j are 1, 2, 3...) In the parallel execution unit 4. ), And the corresponding instruction is executed in the next first cycle T1 (step S6). At the end of the current cycle (T0), the decoder 3 replaces the pair of the register A to be replaced in the above processing with the register name (register number) of the register α used for replacement by an empty entry in the replacement table 6. And turns on the V flag (step S7).

When the decoding results of the instructions # 1 and # 3 are passed from the decoder 3 to the execution units 4-i and 4-j in the parallel execution unit 4, in the first cycle T1, the execution units 4-i An operation is performed in which both contents of the registers A and B specified by the instruction # 1 (add instruction) are added, and the addition result is stored in the register A in the general register group 51. The execution unit 4-j performs an operation of performing an OR operation on the contents of the registers C and E specified by the instruction # 3 (or instruction) and storing the OR result in the register α in the temporary register group 52. Instruction # from instruction queue 3 by decoder 3
When 1 and # 3 are fetched, the subsequent instruction is fetched into the instruction queue 2.

In the cycle T1 in which the instructions # 1 and # 3 are simultaneously executed, the decoder 3
4 (in this case, an instruction sequence including instructions # 2 and # 4), the same operation as described above (for the instructions # 1 to # 4) shown in the flowchart of FIG. Do. However, if the register A specified portion exists in the instruction after the instruction # 4, it is replaced with the register α specified according to 6 in the replacement table.

Here, it is assumed that the register A designation portion does not exist in the instruction after the instruction # 4 and that there is no data or register dependency between the instructions.
Determines that instructions # 2 and # 4 (including an instruction sequence) can be executed simultaneously in the next cycle (second cycle T2). In this case, the decoder 3 outputs instructions # 2 and #
4 (including an instruction sequence) is extracted from the instruction queue 2 and decoded, and the decoded result is passed to the execution unit in the parallel execution unit 4 to execute the corresponding instruction in the next second cycle T2.

As a result, the decoding results of the instructions # 2 and # 4 are passed to the execution units 4-s and 4-t (s and t are different values among 1, 2, 3...). For example, the execution unit 4-s performs an operation of ANDing both contents of the registers A and D specified by the instruction # 2 (and instruction) and storing the AND result in the register D in the general register group 51. In the execution unit 4-t, the instruction # 4 (sub
Instruction), the contents of both registers α and C are subtracted. The result of the subtraction is stored in the register α in the temporary register group 52.
Is performed.

The data matching assurance circuit 7 includes a register unit 5 comprising execution units 4-1, 4-2, 4-3,... In the parallel execution unit 4.
Monitors access to. The data matching assurance circuit 7 registers the register registered in the entry whose V flag is in the on state in the replacement table 6, that is, the register A,
When a cycle in which access to α is not executed (for example, third cycle T3) is detected, the contents of temporary register α are written back to general register A. And the data matching assurance circuit 7
Turns off the V flag in the replacement table 6.

As described above, according to the present embodiment, the instruction sequence of FIG. 2A, which conventionally required four cycles due to the dependence of registers between instructions, is replaced with the instruction sequence of FIG. By performing the register replacement as described above, the execution can be performed in two cycles. That is, according to the present embodiment, the general register designated by the instruction having the register dependence is temporarily replaced (substituted) by the temporary register, so that the instruction by the plurality of execution units 4-i due to the register dependence is obtained. Can be prevented, and the performance can be improved.

It is not always necessary to provide a plurality of temporary registers. When a plurality of temporary registers are provided as in the present embodiment, each temporary register can be substituted for a different general register. It is also possible to substitute the same temporary register for multiple uses.

[0045]

As described in detail above, according to the present invention,
A general register (first register) specified by an instruction having a register dependency is a temporary register (second register)
By temporarily replacing the software, even software containing an instruction sequence that has a register dependency can be executed by making full use of the parallel execution capability of a plurality of instructions of the device without modifying the software, thereby improving performance. be able to.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an information processing apparatus having a function of executing a plurality of instructions in parallel according to an embodiment of the present invention.

FIG. 2 is a diagram showing an instruction sequence stored in an instruction queue 2 in comparison with an instruction sequence after register replacement.

FIG. 3 is a diagram showing the execution sequence of the instruction sequence in FIG. 2 in comparison with the case of the conventional method.

FIG. 4 is a flowchart illustrating an operation.

[Explanation of symbols]

2 ... instruction queue, 3 ... decoder (replacement means), 4 ... parallel execution unit, 4-1, 4-2, 4-3 ... execution unit, 5 ... register unit, 6 ... replacement table, 7 ... data consistency assurance circuit , 51 ... general register group (first register group), 5
2: Temporary register group (second register group)

Continuation of the front page (56) References JP-A-63-167934 (JP, A) JP-A-63-245529 (JP, A) JP-A-61-48037 (JP, A) JP-A-60-129938 (JP, A) , A) Robert. M. Keller, "Look-Ahead Processors", Computing Surves, Vol. 7 No. 4, December 1975 (1975) p. 177-195 (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/38

Claims (1)

(57) [Claims] 1. A data processing apparatus capable of parallel execution of multiple instructions, a plurality of first registers can be specified with the instruction word, it is temporarily used as a substitute for the first register,
At least one second register that cannot be specified by an instruction word and a decoder that sequentially decodes an instruction sequence to be executed.
Therefore, the first register has a register dependency.
And the first register specified by the instruction.
For temporarily replacing only the data with the second register
And a plurality of instructions in parallel based on the decoding result of the decoder.
Parallel execution unit having a plurality of execution units to execute
Therefore, the instruction for register replacement by the decoder
For the instruction, the second register after the replacement is used.
A parallel execution unit for executing the instruction by using the first register which is replaced by the decoder.
The second register used for replacement with the information indicating the
Represented by a replacement table in which pairs of information shown is registered, the information pairs registered in the replacement table
The first and second registers are not accessed.
The contents of the second register corresponding to the second
And a data consistency assurance circuit for writing back to one register.
The information processing apparatus characterized by that.