JPH05173781A - Information processor provided with function for executing plural instructions in parallel - Google Patents

Abstract

PURPOSE:To execute plural instructions by sufficiently effectively utilizing parallel executing ability provided in the device without improving a software containing instruction sequences in register depending relation even in the case of such a software. CONSTITUTION:A decoder 3 is provided to detect instructions in the register depending relation concerning a register in a general register group 51 from the instruction sequences stored in an instruction queue 2 and to change a corresponding register designating part in that instruction so as to designate a temporary register in a temporary register group 52. The information of registers before and after the change due to the decoder 3 are registered on a replacement table 6. The decoder 3 decodes the instruction sequences after the register designating part is changed, and the relevant instruction is executed by activating an execution unit in a parallel execution part 4. According to the replacement table 6, a data matching guarantee circuit 7 writes the contents of the temporary register back to the original general register after the execution due to the parallel execution part 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus having a parallel execution function for a plurality of instructions, and more particularly to a parallel execution system for a plurality of instructions having register dependence.

[0002]

2. Description of the Related Art As an information processing apparatus for executing existing software at high speed, a plurality of instruction execution units are provided, and a plurality of instructions in an instruction sequence in the software are simultaneously (parallel) processed.
There is known an information processing apparatus represented by a superscalar type computer that is executed (in the same cycle) without shortening the time required for one cycle (that is, without increasing the clock frequency).

In the above-described information processing apparatus having a parallel execution function of a plurality of instructions, from the queue holding the maximum number of instructions that can be executed in one cycle, even if they are executed simultaneously, one by one It was supposed to take out the same command and execute it.

If there are data dependencies among the queued instructions, they cannot be executed at the same time. For example, if the output data of a certain instruction # 1 becomes the input data of another instruction # 2, these instructions # 1 and # 2 cannot be executed at the same time, and if they are forcibly executed, the result will be the instruction # 1. It will be different from the case where the instruction # 2 is executed after the execution.

Even if there is no data dependency, if the registers have a dependency, it is normal that all the corresponding instructions cannot be executed at the same time. For example, if the instruction # 3 uses the data held in one register and another instruction # 4 writes the data in the same register, the instructions # 3 and # 4 have no dependency on both data, , Can't run at the same time. This is because the value is written in the register of the data to be used in the instruction # 3 by the instruction # 4.

In order to eliminate such register dependence, different registers may be used. However, if existing software (program) has an instruction sequence that has register dependence, that software must be rewritten, which is extremely complicated. In addition, even with newly created software, the number of registers that can be specified is limited due to the size of the register specification field in the instruction word. It is likely to be used in the same register. In other words, if the number of registers that can be specified as access targets in an instruction word, in other words, the number of registers that can be recognized by software is the same, the performance degradation due to register dependence cannot be reduced even if the number of execution units is increased, and the number of registers that can be recognized by software is increased. To deal with increasing the number of, you have to rewrite the existing software.

[0007]

As described above, in the conventional information processing apparatus having the parallel execution function of a plurality of instructions, the instruction sequences having the register dependency relationship cannot be executed at the same time. There is a problem that the parallel execution function cannot be used to the maximum extent, and in order to solve this problem, software must be modified to arrange the instruction sequence so that it does not depend on registers, or to rearrange the instruction sequence. However, there is a problem that it requires a lot of manpower and cost.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to achieve a sufficient parallel execution capability of a plurality of instructions possessed by a device without modifying the software even if the software includes an instruction sequence having a register dependency relationship. It is to provide an information processing device that can be utilized by being utilized.

[0009]

According to the present invention, in an information processing apparatus having a plurality of instruction execution units and capable of executing a plurality of instructions in parallel, a plurality of first registers which can be designated by an instruction word, and a plurality of first registers. An instruction having a register dependency relationship with respect to the first register is detected from at least one second register temporarily used as a substitute for the one register and an instruction sequence to be executed, and the instruction is designated. Means for temporarily replacing the first register with the second register, and executing a plurality of instructions having register dependence by using the second register in parallel. It is a feature.

[0010]

In the above structure, for instructions having register dependence due to the same first register designation, the first register designated by the instruction is replaced with the instruction not designated by the instruction word. 2nd register (temporary register)
Are temporarily assigned. By allocating the second register, the register dependency is canceled. Therefore, if only the first register designated by the instruction word is used, it is impossible to execute a plurality of instructions in parallel due to the register dependency. Software can be executed by making full use of the parallel execution capability of multiple instructions of the device, and performance can be improved.

..

1 is a block diagram showing the configuration of an information processing apparatus having a parallel execution function of a plurality of instructions according to an embodiment of the present invention.

In FIG. 1, 1 is a memory for storing programs, data and the like, and 2 is an instruction queue for holding the instructions fetched from the memory 1 in the order of the fetch order. The instruction queue 2 includes a parallel execution unit 4 described later.
It has a structure that can hold more than the maximum number of instructions that can be executed simultaneously. The instruction held in the instruction queue 2 is removed from the queue 2 when it is executed.

A cache memory (or an instruction cache) is provided between the memory 1 and the instruction queue 2 so that the instruction fetched from the cache memory can be stored in the instruction queue 2
May be stored in.

Reference numeral 3 is a decoder for sequentially fetching instructions from the instruction queue 2 and performing a decoding process. This decoder 3
For parallel (simultaneous) execution of multiple instructions, in addition to the well-known function of checking the data dependency and register dependency of the target instruction, for the instructions with register dependency, the register specified by the instruction will be described later. Control to replace with a temporary register.

Reference numeral 4 is a parallel execution unit for receiving a decoding result of a plurality of instructions by the decoder 3 and executing the plurality of instructions in parallel. The parallel execution unit 4 has a plurality of execution units 4-1, 4-2, 4-3, ... For independently executing the corresponding instruction based on the decoding result of each instruction given from the decoder 3. To have.

Reference numeral 5 denotes a parallel execution unit 4 (execution unit 4-
1, 4-2, 4-3, etc.) is a register unit for holding data to be operated. The register unit 5 includes a plurality of general registers (registers A, B, C, which can be designated by a source or destination register designation field of an instruction word) recognized by software running on the device.
A general register group 51 composed of D ...) and a temporary register group 52 composed of a plurality of temporary registers (represented by registers .alpha., .Beta.) That are not recognized by the software.

Reference numeral 6 is a replacement table having a plurality of entries. Each entry of the replacement table 6 includes a register name (register number) of a general register in the register unit 5 to be replaced by the decoder 3 and a temporary register in the register unit 5 used in place of the general register. Register name (register number) and a setting field of a valid flag (V flag) indicating whether or not the information of the corresponding entry is valid.

Reference numeral 7 is a data matching guarantee circuit. The data matching guarantee circuit 7 guarantees the data consistency by writing back the contents of the temporary register in the register unit 5 to the general register which is the target of the replacement shown in the replacement table 6. Next, the operation of the configuration of FIG. 1 will be described by taking the case where the instruction string fetched in the instruction queue 2 is as shown in FIG.

In FIG. 2, "add A, B,
The instruction # 1 indicated by "A" is an instruction to store the sum of the contents of both registers A and B in the register A, and the instruction # 2 indicated by "and A, D, D".
Is an instruction to store the result of ANDing the contents of both registers A and D in register D. The instruction # 3 indicated by "or C, E, A" is an instruction to store the result of ORing the contents of both the register C and the register E in the register A, and "sub C".
Instruction # 4 indicated by A, C, A ″ is an instruction to store in register A the difference between the contents of register A and register C.

As a result of fetching an instruction string from the memory 1 to the instruction queue 2 by an instruction fetch mechanism (not shown), the contents of the instruction queue 2 are as shown in FIG. 2 (a) at the start of the cycle T0. It is assumed that Here, the order of the instruction sequence in the instruction queue 2 is the order of fetching from the memory 1, that is, the order of instructions created as being executed one instruction at a time.

Now, in order to execute the instruction sequence in the instruction queue 2 shown in FIG. 2A by the conventional method, it takes four cycles as shown in FIG. 3B, and simultaneous execution is impossible. .. The reason is as follows.

First, one of the operation data used in the instruction # 2 is stored in the register A, but the value of the register A cannot be determined unless the instruction # 1 (add instruction) is executed. That is, there is a data dependency between the instruction # 1 and the instruction # 2.

Secondly, since the register A for writing the OR result by the instruction # 3 (or instruction) contains the operation data used by the instructions # 1 and # 2 (and instruction), the instruction # 1,
If the instruction # 3 is not executed after # 2 is executed, the instruction #
This is because the data of the register A used in 1 and # 2 may be rewritten by the instruction # 3. That is, there is a register dependency between the instructions # 1 and # 2 and the instruction # 3.

Thirdly, the value of the register A used in the instruction # 4 (sub instruction) is not determined unless the instruction # 3 (or instruction) is executed. That is, there is a data dependency between the instruction # 3 and the instruction # 4.

On the other hand, in the present embodiment, the instruction sequence in the instruction queue 2 shown in FIG. 2A is changed by register replacement described later as shown in FIG.
It can be executed in two cycles as shown in (a). This operation will be described in detail with reference to the flowchart of FIG.

In the cycle T0, the decoder 3 has the first instruction (# 1) and the second instruction (# 1) in the instruction queue 2.
2) is compared to check the dependency, and the subsequent instruction (# 2)
Check whether the above instruction (# 1) is data-dependent or register-dependent (step S).
1). If there is no dependency, the decoder 3 determines to execute both instructions simultaneously in the next cycle (first cycle) T1 (step S2).

On the other hand, as in the example of FIG. 2A, when there is a dependency relationship (here, data dependency relationship) between the preceding instruction # 1 and the subsequent instruction # 2, the decoder 3 Sends the dependent instruction (register A in this case) to the subsequent instruction # 2.
It is checked whether or not the source has been designated (step S3).

When the source of the register (A) having a dependency relationship with the preceding instruction # 1 is designated by the succeeding instruction # 2 as in the example of FIG. , The previous instruction # 1 is executed in the next first cycle T1, and the subsequent instruction # 2 is executed in the next second cycle T2, which is internally stored (step S
4). Actually, the information indicating the position in the instruction queue 2 of the instruction to be executed in the first cycle T1 is internally stored, or
For example, a flag bit unique to the position in the instruction queue 2 of the instruction executed in the cycle T1 may be turned on.

Next, the decoder 3 executes the above step S1 for the third instruction (# 3) and the preceding instruction (# 2) in the instruction queue 2, and the instruction # 3 sends data to the instruction # 2. Check if there is a dependency or register dependency relationship.

If, as in the example of FIG. 2A, instruction # 2
And the instruction # 3 have a dependency relationship (here, a register dependency relationship) and the source of the dependent register (A) is not specified in the subsequent instruction # 3 (when NO is determined in step S3). Means that the decoder 3 executes all the register A designated parts of the instructions in the instruction queue 2 after the instruction # 3 (here, the destination register A designated part of the instruction # 3,
Instruction # 4 source and destination register A
The designated portion) is replaced with the designation of an arbitrary temporary register in the temporary register group 52, for example, the temporary register α (step S5). The contents of the instruction queue 2 at this time are shown in FIG.
Shown in.

Next, the decoder 3 operates the first queue in the instruction queue 2.
The instruction # 1 determined to be executed in the cycle T1 is compared with the instruction # 3 (which has been replaced by the register A to the register α) to check the dependency, and the instruction # 3 is compared with the instruction # 1. It is checked whether or not there is a data-dependent or register-dependent relationship (step S1).

When there is no dependency between the instruction # 1 and the instruction # 3 as in the example of FIG. 2B, the decoder 3 sets the instruction # 3 to the same first cycle as the instruction # 1. At T1, it is decided to execute them simultaneously, and that effect is internally stored (step S2).

Next, the decoder 3 compares the instruction # 1 in the instruction queue 2 with the instruction # 4 (the instruction next to the instruction # 3, in which the register A is replaced with the register α). The dependency relationship is checked by checking whether instruction # 4 has a data-dependent or register-dependent relationship with instruction # 1 (step S1).

When there is no dependency between the instruction # 1 and the instruction # 4 as in the example of FIG. 2B, the decoder 3 sets the instruction # 4 to the same first cycle as the instruction # 1. At T1, it is decided to execute them simultaneously, and that effect is internally stored (step S2).

Next, the decoder 3 compares the instruction # 3 after the register replacement in the instruction queue 2 with the instruction # 4 to check the dependency, and the instruction # 4 determines whether the instruction # 3 is data-dependent or not. It is checked whether there is a register-dependent relationship (step S1).

As shown in the example of FIG. 2B, there is a dependency between the instruction # 3 and the instruction # 4, and the source of the dependent register (α) is designated by the subsequent instruction # 4. If YES (determined as YES in step S3), the decoder 3 executes the previous instruction # 3 in the first cycle T1 and the subsequent instruction # 4 in the next second cycle T2. The determination is made and the effect is internally stored (step S4). As a result, the contents of the decision that the execution cycle of the instruction # 4 is T1 are canceled.

When the decoder 3 determines the execution cycle by comparing the last instructions # 3 and # 4 in the instruction queue 2, the instruction to be executed in the first cycle T1, that is, the instruction #
1, # 3 are fetched from the instruction queue 2 and decoded, and the decoding results of the instructions # 1, # 3 are executed by the execution units 4-i, 4-j in the parallel execution unit 4 (i, j are 1, 2, 3 ... , Which are different from each other) to execute the corresponding instruction in the next first cycle T1 (step S6). At the end of the current cycle (T0), the decoder 3 replaces a pair of the register A (register number) used for the replacement and the register name (register number) used for the replacement in the above process with an empty entry in the replacement table 6. And the V flag is turned on (step S7).

Now, when the decoding results of the instructions # 1 and # 3 are passed from the decoder 3 to the execution units 4-i and 4-j in the parallel execution unit 4, in the first cycle T1, the execution unit 4-i An operation is performed in which the contents of both the registers A and B designated by the instruction # 1 (add instruction) are added and the addition result is stored in the register A in the general register group 51. In the execution unit 4-j, the contents of both the registers C and E designated by the instruction # 3 (or instruction) are ORed, and the OR result is stored in the register α in the temporary register group 52. Instruction # from instruction queue 3 by decoder 3
When 1 and # 3 are fetched, subsequent instructions are fetched in the instruction queue 2.

In the cycle T1 in which the instructions # 1 and # 3 are simultaneously executed, the decoder 3 executes the instruction queue 2 at that time.
The same operation as the above (for the executed instructions # 1 to # 4) shown in the flowchart of FIG. 4 is performed on the instruction series stored in (in this case, the instruction series including the instructions # 2 and # 4). To do. However, if the register A designated portion exists in the instruction after the instruction # 4, it is replaced with the register α designated according to 6 in the replacement table.

Here, if it is assumed that there is no register A designated portion in the instructions after the instruction # 4 and there is no data or register dependency between the instructions, the decoder 3
Determines that the instructions # 2 and # 4 (including the instruction sequence) can be simultaneously executed in the next cycle (second cycle T2). In this case, the decoder 3 uses the instructions # 2, #
4 (including the instruction string) is fetched from the instruction queue 2 and decoded, and the decoding result is passed to the execution unit in the parallel execution section 4 to execute the corresponding instruction in the next second cycle T2.

As a result, even if the decoding results of the instructions # 2 and # 4 are passed to the execution units 4-s and 4-t (s and t are different values among 1, 2, 3 ...) For example, the execution unit 4-s performs an operation of ANDing both contents of the registers A and D designated by the instruction # 2 (and instruction) and storing the ANDed result in the register D in the general register group 51. In the execution unit 4-t, the instruction # 4 (sub
The contents of both registers α and C specified by (instruction) are subtracted. The subtraction result is stored in the register α in the temporary register group 52.
The operation of storing in.

The data matching assurance circuit 7 includes a register unit 5 composed of execution units 4-1, 4-2, 4-3 ... In the parallel execution unit 4.
Are watching for access to. The data matching assurance circuit 7 uses the register registered in the entry in which the V flag is ON in the replacement table 6, that is, the register A,
When a cycle in which access to α is not executed (for example, the third cycle T3) is detected, the contents of the temporary register α are written back to the general register A. And the data matching assurance circuit 7
Turns off the V flag in the replacement table 6.

As described above, according to the present embodiment, the instruction sequence of FIG. 2A, which conventionally required four cycles due to register dependence between instructions and the like, is changed from the instruction sequence of FIG. By performing register replacement as described above, it is possible to execute in two cycles. That is, according to the present embodiment, by temporarily replacing (substituting) the general register designated by the instruction having the register dependency with the temporary register, the instructions by the plurality of execution units 4-i due to the register dependency. It is possible to prevent the simultaneous execution of and to improve the performance.

It is not always necessary to provide a plurality of temporary registers. When a plurality of temporary registers are provided as in this embodiment, each temporary register can be used as a substitute for a different general register. It is also possible to use the same temporary register multiple times.

[0045]

As described in detail above, according to the present invention,
A general register (first register) designated by an instruction having a register dependency is a temporary register (second register)
By temporarily substituting in, even software that includes a sequence of instructions that has a register dependency can be executed by fully utilizing the parallel execution capability of multiple instructions of the device without modifying the software, aiming to improve performance. be able to.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an information processing apparatus having a parallel execution function of a plurality of instructions according to an embodiment of the present invention.

FIG. 2 is a diagram showing an instruction sequence stored in an instruction queue 2 in comparison with an instruction sequence after register replacement.

FIG. 3 is a diagram showing the execution order of the instruction sequence in FIG. 2 in comparison with the case of a conventional method.

FIG. 4 is a flowchart for explaining the operation.

[Explanation of symbols]

2 ... Instruction queue, 3 ... Decoder (replacement means), 4 ... Parallel execution unit, 4-1, 4-2, 4-3 ... Execution unit, 5 ... Register unit, 6 ... Replacement table, 7 ... Data matching guarantee circuit , 51 ... General register group (first register group), 5
2 ... Temporary register group (second register group).

Claims (1)

[Claims] 1. An information processing apparatus comprising a plurality of instruction execution units and capable of executing a plurality of instructions in parallel: a plurality of first registers that can be designated by instruction words; and a temporary register as a substitute for the first registers. Detecting at least one second register used for the instruction and an instruction string to be executed for an instruction having a register dependency relationship with respect to the first register, and setting the first register designated by the instruction to the instruction. An information processing apparatus, comprising: means for temporarily replacing the second register, wherein a plurality of instructions having a register dependency are executed in parallel by using the second register.