JP2927102B2 - Instruction string switching method and arithmetic processor using the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for switching an instruction sequence in an arithmetic processor operating in the von Innoman system and an arithmetic processor using the same.

[0002]

2. Description of the Related Art Conventionally, in an arithmetic processor operating according to the von Innoman method, if an instruction for accessing a memory is found in the execution of an instruction sequence, the instruction is executed and the memory access is terminated. Until the operation, the processing operation of the arithmetic unit takes a control method of waiting for the next instruction without proceeding to the processing of the next instruction. In particular, when the access is a memory read operation, such an operation of waiting is indispensable in order to use the read value in subsequent instructions.

[0003]

According to such a control method, when the time required from the start of memory access to the end thereof is longer than the time required to execute one instruction of the arithmetic processor. Causes a cycle in which the arithmetic processor wastes time without executing the arithmetic processing, which causes a reduction in processing performance.

An object of the present invention is to solve such a problem and to provide an instruction sequence switching method for performing processing without deteriorating processing performance and an arithmetic processor using the same.

[0005]

According to a first aspect of the present invention, an instruction sequence switching method includes a token memory which expresses an executable instruction sequence in the form of a token including an address value of an instruction to start execution by the instruction sequence. And executing the instruction sequence fetch operation of selecting one of the tokens in the token memory and loading the execution start instruction address contained in the token into the program counter of the arithmetic unit. To generate a token including the value of the current program counter as the execution start address and a description of the operation to be performed externally during execution of the instruction sequence,
After the token is issued to the outside and the execution of the instruction sequence is interrupted, the execution of another instruction sequence is started by the instruction sequence fetch operation, and the token issued to the outside returns to the arithmetic processor as described above. When the token is selected in the token memory as the target of the next instruction fetch operation, the execution start address held in the token is loaded into the program counter of the arithmetic control unit Then, the instruction sequence processing is restarted.

According to a second aspect of the present invention, there is provided an arithmetic processor for sequentially executing instructions in one instruction sequence, a token memory for holding an externally input token and supplying the token to the arithmetic processor, A register group for holding data accessed from the unit, a token generation unit for generating a token including the value of the program counter at that time in the instruction sequence being executed and a description of the operation to be performed externally, and transmitting the token to the outside; Interrupting execution of the instruction sequence of the arithmetic processing unit, selecting an instruction sequence token to be supplied from the token memory to the arithmetic processing unit,
It is characterized by including an operation of loading a value included in the token into the arithmetic processing unit, and an instruction sequence control unit that controls operations of the token memory and the token generation unit.

In a third aspect, in addition to the first aspect, when the externally issued token returns to the arithmetic processor, if the externally performed operation is a memory read operation, the token After writing the read data in the register in the arithmetic processor, the token is held in the token memory.

According to a fourth aspect of the present invention, in addition to the second aspect, a precedent load unit for writing read data in the token to a register in a register group before holding the token returned from the outside to the arithmetic processor in the token memory. It is characterized by having.

According to a fifth aspect of the present invention, in addition to the first aspect, a number of instruction sequences determined by a predetermined number of register areas can be executed, and a register exclusively used by each of the plurality of executable instruction sequences is provided. A feature is to prepare a register area that can be used from the area and all instruction strings.

According to a sixth aspect, in addition to the second aspect, the executable instruction sequence is divided into a plurality of local register areas exclusively used by each of the executable instruction sequences and a global register region usable from all the instruction sequences. It is characterized by having an operation register group.

[0011]

In the first and second inventions, the value of the program counter during execution of the instruction sequence is held in the token sent to the outside, and when the token returns to the arithmetic processor and is processed again, the value is stored in the program counter. Execution of the instruction sequence can be continued by loading. By processing another instruction sequence while the token is out, it is possible to reduce unnecessary cycles in the arithmetic unit, and to maintain high processing performance.

According to the third and fourth aspects of the present invention, in addition to the operation described above, the writing of the data read from the memory to the register can be completed before the processing of the corresponding instruction sequence is restarted. This enables efficient use of the operation cycle.

According to the fifth and sixth aspects of the present invention, in addition to the above-described operation, different register spaces can be used for each instruction sequence, so that a plurality of different contexts running in the same program portion can coexist, thereby providing more flexibility. Effective processing using a simple program becomes possible.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, an embodiment of an arithmetic processor according to the second invention using the method of the first invention will be described with reference to the drawings.

FIG. 1 is a diagram showing a basic configuration of an embodiment of an arithmetic processor according to the second invention, FIG. 2 is a diagram showing a format of a token used in the arithmetic processor, and FIG. 3 is a diagram showing an instruction format of the arithmetic processor. FIG.

The arithmetic processor 1 shown in FIG. 1 performs an arithmetic operation in accordance with an instruction in an instruction sequence referenced by the instruction sequence while increasing a value of a program counter provided therein when an instruction sequence is given. Unit 10 and arithmetic processing unit 10
A register group 11 which is a set of a plurality of registers referred to and updated from a memory; a token generation unit 12 which generates a token from an instruction in the arithmetic processing unit and a value of a program counter and issues the token to the memory access controller 2; FIF the token input from controller 2
It comprises a token memory 13 for sequentially storing O, an instruction sequence control unit 14 for controlling the operations of the token memory 13, the arithmetic processing unit 10 and the token generation unit 12 and having a memory for storing a program therein.

When the arithmetic processing is performed using such an arithmetic processor 1, the processing proceeds as follows.

First, a program describing the entire operation is given to the instruction sequence control unit 14 from the outside via the signal line 90, and then some tokens each having an execution start address are given. The program in the instruction sequence control unit 14 is a sequence of a series of instructions, and the execution start address is one of them. Hereinafter, a partial sequence from the execution start address to a certain end point in the program is referred to as an instruction sequence. All tokens are stored in the token memory 13. The token in the token memory 13 has a format shown by 50 in FIG. 2 and has a field 51 of an execution start address. Field 60 is not used. Flag 52
Is “0”. In addition, the number of tokens externally provided to the token memory 13 is set in a token number counter in the instruction sequence control unit 14.

When a processing start signal is externally supplied to the instruction sequence control unit 14, the first token in the token memory 13 is sent to the arithmetic processing unit 10, and the token 50
If the value of the flag 52 is “0”, the arithmetic processing unit 1
At 0, the value of the execution start address 51 in the token is set in the program counter. This is hereinafter referred to as an instruction string fetch operation. Thereafter, execution of the instruction sequence is started.

In the arithmetic processing of the arithmetic processing unit 10, first, the value of the program counter is sent to the instruction control unit 14, and the instruction in the program in the instruction sequence control unit 14 indicated by the address is fetched to the arithmetic processing unit 10. . This is called an instruction fetch operation. Then, the arithmetic processing unit 10 performs the operation described in the fetched instruction, increments the value of the program counter by one, and proceeds to the execution of the next instruction. The above is the basic operation of instruction execution.

The types of instructions obtained by the instruction fetch include an ALU operation instruction for performing operations such as addition, subtraction, multiplication, and division by referring to a maximum of two registers in the register group 11 and writing the result to a specified register, and an external memory. A load instruction that reads the above data by specifying its address and loads it into a register, a store instruction that writes data on a register to a specified location in external memory, and an instruction sequence that terminates instruction sequence execution at the end of the instruction sequence There is an end command.

When the instruction obtained by the instruction fetch is an ALU operation instruction, the above-described basic operation is performed. The format of the ALU operation instruction is as shown at 80 in FIG. The read register identifier A and the read register identifier B indicate the register containing the data used for the operation, and the write register identifier indicates the register in which the result is to be stored. The register identifier uniquely identifies one register in the register group 11.

If the instruction obtained by the instruction fetch is a load instruction, the instruction sequence control unit 14
In response to the instruction shown in FIG.
5 is generated. The format of the load instruction is shown at 70 in FIG. 71 is an instruction code indicating a load instruction, 73 is an address at which memory reading is performed,
Reference numeral 72 denotes an identifier of a register in which the read data is written. The token 55 uses the value of the program counter in the arithmetic processing unit 10 at that time as the execution start address 58 and the address 7 to be accessed of the external memory in the load instruction 70.
3 in the field 57 and the memory access controller 2
The operation code 56 has a code for instructing a memory read as an operation performed in. Field 81 is not used. This read request token is generated after the signal line 91
To the memory access controller 2 via Thereafter, the instruction sequence fetch operation is performed under the control of the instruction sequence control unit 14, and the execution of the fetched instruction sequence is started.

If the instruction obtained by the instruction fetch is a store instruction for writing data in a register to a specified location in the external memory, the instruction sequence control unit 14 instructs the token generation unit 12 to Token generator 12
Generates a token in the format indicated by 55 in FIG. The format of the store instruction is shown at 75 in FIG. Reference numeral 76 denotes an instruction code indicating a store instruction, 77 denotes an address for writing to a memory, and 78 denotes an identifier of a register for reading data to be written. The token 55 is the arithmetic processing unit 1 at that time.
Execution start address 58
In the field 57, the address 77 to be written to the external memory in the store instruction 75, the code for instructing the memory write as an operation performed by the memory access controller 2, and the instruction code 7
The data to be written, which is read from the register designated by 8, is stored in the field 59. Field 61 is not used. This write request token is sent to the memory access controller 2 via the signal line 91 after generation. After the token is issued, the arithmetic processing unit 10 increments the value of the program counter by one and then continues the arithmetic processing of the instruction sequence, as in the case of the basic operation of the program counter.

If the instruction obtained by the instruction fetch is an instruction sequence end instruction for terminating the instruction sequence execution at the end of the instruction sequence, the value of the token number counter in the instruction sequence control unit 14 is decremented by one. . After the decrement, the completion of the program execution is notified to the outside via the signal line 90 which has become 0, and the arithmetic processor 1 stops. If it is not 0, then the instruction sequence fetch operation is performed under the control of the instruction sequence control unit 14, and the execution of the fetched instruction sequence is started.
If no token exists in the token memory 13, the arithmetic processing unit 10 keeps waiting until a token is obtained.

When the memory access controller 2 receives the read token 55, it reads data from the address indicated by the access address 57 in accordance with the operation code 56, generates a token in the format 50 of FIG. send. At this time, the value of the field 58 of the token 55 is given to the field 51, the value read from the memory is given to the data 53, and "1" is given to the flag 52. Field 60 is not used.

When the memory access controller 2 receives the write token 55, it stores data 59 according to the operation code 56 in the access address 5.
Write to the address indicated by 7.

The token from the memory access controller 2 is input to the arithmetic processor 1 via a signal line 92. The format of the token is as shown at 55 in FIG.
When a token is input, the token is added to the end of the FIFO in the token memory 13. In the FIFO, every time the first token is fetched from the arithmetic processing unit 10, it is removed, and the second token up to that point becomes first, and the order moves up in the following order.

In the instruction sequence fetch operation, when the value of the flag 52 of the fetched token 50 is "1", the arithmetic processing unit 10 first sets the value of the execution start address 51 in the token to the program counter. I do.
Since the instruction of the program in the instruction sequence control unit 14 addressed by the program counter is the load instruction that the instruction sequence to which it belongs last was executed last, it is specified in the field 72 of the format of the instruction 70 in FIG. After writing the data 53 of the token 50 to the register, the program counter is incremented, and the arithmetic processing of the instruction sequence is restarted from the next instruction.

Next, an embodiment of the arithmetic processor of the fourth invention using the method of the third invention will be described with reference to the basic configuration diagram of one embodiment of the arithmetic processor of the fourth invention in FIG.

The arithmetic processor 20 includes, in addition to the configuration shown in FIG. 1, a preceding load unit 2 for writing data in a token input from the memory access controller 2 into a register.
Have one. The operation of the arithmetic processor 20 for executing processing is the same as that of the arithmetic processor according to the second invention except for the following points.

A token whose flag in the field 52 is "1" from the memory access controller 2 in a format as shown in FIG. 2 is input to the arithmetic processor 20 via the signal line 92. In this case, the following operation is performed in the preceding loading unit 21.

First, using the execution start address 51 in the token 50, the instruction of the program in the instruction sequence controller 14 is referred to via the signal lines 93 and 94. Since this instruction is the load instruction that the instruction sequence to which it belongs last was executed last, the token 5 is added to the register in the register group 11 specified by the field 72 in the format of the instruction 70 in FIG.
The data 53 of 0 is written. In the cycle in which the arithmetic processing unit 10 is writing data to the register, the data cannot be simultaneously written from the preceding load unit 21. At that time, the write request is held in the FIFO in the preceding load unit 21 and the write is performed first. Write when possible. When the instruction sequence is switched by the arithmetic processing unit 10, the effective start of a new instruction sequence is delayed if necessary to
Complete all write requests in O.

When the writing is completed, the value of the effective start address 51 of the token 50 is incremented, and the token is added to the end of the FIFO of the token memory 13 after the flag 52 is set to "0".

When the token is fetched from the beginning of the token memory 13 to the arithmetic processing unit 10 and the instruction sequence is executed, the load operation has been completed in the preceding load unit 21, and the execution continues from the instruction following the load instruction. Is done.

Next, an embodiment of the arithmetic processor of the sixth invention using the method of the fifth invention will be described with reference to the basic configuration diagram of one embodiment of the arithmetic processor of the sixth invention in FIG.

In the arithmetic processor 30, the register group 11 in the configuration of FIG. 1 is divided into a global register frame 31 and N local register frames 32. N is an integer of 2 or more, for example, 1
6 is assumed.

In the arithmetic processor 30, the number of tokens that can be given from the outside at the start of program execution is limited to N or less. As a result, the number of executable instruction sequences simultaneously existing in the system becomes N or less. When N or less tokens are externally given at the time of program startup, the instruction sequence control unit 14 gives a different frame identifier to each token. The frame identifier identifies which of the N local register frames exclusively uses the instruction sequence represented by the token. The token given from the instruction sequence control unit 14 to the token memory 13 at the start of the program execution has the format indicated by 50 in FIG. 2 as described above, and this frame identifier is written in the field 60. The operation when the processing start signal is given is the same as the operation processor of the second invention except for the following points.

When the arithmetic processing unit 10 fetches the token of the format 50 shown in FIG. 2 and starts execution, it stores not only the execution start address 51 in the program counter but also the value of the frame identifier 60 in the arithmetic processing unit 10. In the frame register in

When executing an ALU operation instruction, a load instruction, and a store instruction, the instructions are in the form of 70, 75, and 80 in FIG. 3, but the register identifier in these instructions is not for directly identifying the register. Is used for identification in the frame assigned to the instruction sequence. The register identifier first indicates whether it points to a global frame register or a local frame register, in which case the rest addresses one of them. In the latter case, one frame is determined by the frame identifier held in the frame register in the arithmetic processing unit 10, and one of the registers is addressed by the register identifier in the instruction. The same applies to the case where the token is returned from the memory read and the value read from the memory is written into the register specified in the instruction while referring to the load instruction again in the arithmetic processing unit 10 via the token memory 13.

In the token generated by the token generation unit when executing a load instruction, a store instruction, etc., 55 in FIG.
The frame identifier held in the arithmetic processing unit 10 is written in the field 61 of (1). When the memory access controller 2 that receives the read request token and performs a memory access operation creates a return token to the arithmetic processor, the memory access controller 2 embeds the frame identifier value of the received token as it is in the corresponding field of the return token.

As described above, it is possible to use a different register set for each instruction sequence, but it is also possible to incorporate this mechanism and the mechanism and operation of the preceding load section described in the fourth invention. It is possible.

[0043]

According to the first and second aspects of the present invention, the execution of the instruction sequence can be continued when returning to the arithmetic processor by holding the program counter in the token sent to the outside. By continuing the processing of another instruction sequence while the token is out, the number of cycles wasted in the arithmetic unit can be reduced, and the processing performance can be kept high.

According to the third and fourth aspects of the present invention, in addition to the effects described above, the writing of the data read from the memory to the register can be completed before the processing of the corresponding instruction sequence is restarted. This has the effect of enabling more efficient use of the operation cycle.

According to the fifth and sixth aspects of the present invention, in addition to the above-described effects, different register spaces can be used for each instruction sequence, thereby enabling coexistence of a plurality of different contexts running in the same program part, and thereby providing more flexibility. There is an effect that effective processing of a simple program becomes possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an arithmetic processor according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating a format of a token used in an arithmetic processor according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a format of an instruction used in an arithmetic processor according to an embodiment of the present invention;

FIG. 4 is a block diagram illustrating a configuration of an arithmetic processor according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of an arithmetic processor according to an embodiment of the present invention.

[Explanation of symbols]

 1, 20, 30 Arithmetic processor 10 Arithmetic processing unit 11 Register group 12 Token generation unit 13 Token memory 14 Instruction sequence control unit 21 Preceding load unit 31 Global register frame 32 Local register frame

Claims (6)

(57) [Claims] 1. An instruction sequence switching method for preparing a plurality of instruction sequences that can be executed in parallel by an arithmetic processor that operates by sequentially executing instructions in an instruction sequence, and performing processing while switching the instruction sequences. A possible instruction sequence is expressed in the form of a token including the value of the address of an instruction to start executing in the instruction sequence and is stored in the token memory, and one of the tokens in the token memory is selected. Then, the execution of the instruction sequence is started by an instruction sequence fetch operation of loading the execution start instruction address included in the token into the program counter of the arithmetic unit, and the execution start address as the execution start address during the execution of the instruction sequence Generate a token containing the value of the program counter and a description of the operation to be performed externally, issue the token to the external, and Starting the execution of another instruction sequence by the instruction sequence fetch operation after interrupting the execution of the instruction sequence,
As described above, when the token issued to the outside returns to the arithmetic processor, the token is held in the token memory. An instruction sequence switching method characterized by loading the held execution start address into a program counter of an arithmetic control unit and restarting instruction sequence processing. 2. An arithmetic processor which prepares a plurality of instruction sequences that can be executed in parallel in advance and executes processing by sequentially executing instructions in any one of the instruction sequences.
An arithmetic processing unit that sequentially executes instructions in one instruction sequence, a token memory that holds a token input from the outside and supplies it to the arithmetic processing unit, and a register group that holds data accessed from the arithmetic processing unit. A token generation unit that generates a token including the value of the program counter at that time in the instruction sequence being executed and a description of the operation to be performed externally and sends the token to the outside, and interrupts the execution of the instruction sequence of the arithmetic processing unit; An instruction sequence control unit that controls an operation of selecting an instruction sequence token to be supplied from the token memory to the operation processing unit and loading a value included in the token into the operation processing unit, and controlling the operation of the token memory and the token generation unit; An arithmetic processor comprising: 3. When the externally issued token returns to the arithmetic processor, if the externally performed operation is a memory read operation, the read data in the token is written to a register in the arithmetic processor. 2. The instruction sequence switching method according to claim 1, wherein the token is held in a token memory afterwards. 4. A preload unit for writing memory read data in a token to a register in a group of registers before holding a token returned from an external processor to an arithmetic processor in a token memory.
An arithmetic processor as described. 5. A register area exclusively used by each of a plurality of executable instruction sequences and a register usable from all the instruction sequences, wherein a predetermined number of instruction sequences determined by a predetermined number of register regions are made executable. 2. The method according to claim 1, wherein an area is prepared. 6. An executable instruction sequence having a plurality of local register areas exclusively used and an operation register group divided into global register areas usable from all instruction sequences. Item 3. The arithmetic processor according to item 2.