JPH04127326A - Information processor and instruction generating method - Google Patents

Abstract

PURPOSE:To decrease the number of instructions to be executed and to shorten the execution time by providing an instruction scheduler for detecting a non- execution instruction in the case an instruction in an instruction queue part is the non-execution instruction, eliminating it from the execution object, and replacing it with an instruction continued from this instruction. CONSTITUTION:Before one instruction is executed in its execution preparation stage, that is, in a stage that it goes into an instruction queue 104, an instruction scheduler 105 for eliminating its instruction as a non-execution instruction from the instruction queue 104 and replacing it with an instruction placed subsequently to its instruction is provided. In such a state, when there is designation for converting itself to non-execution in an instruction word, its instruction is detected by a detector 106, and the instruction scheduler 105 eliminates the instruction concerned from an execution object. Also, the instructions after the next instruction of the instruction to be eliminated are shifted successively to the front of the queue by one stage each in the instruction queue part 104. In such a way, it does not occur that the instruction eliminated from the execution object as an ineffective instruction is executed, and it does not occur that a burden is imposed on the execution time of a program.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to instruction execution in an information processing device, and in particular, due to architectural constraints, data is In order to reduce the number of instructions to be executed and shorten the execution time when the number of execution instructions required to refer to the data is different, it is a device that can be widely applied and is targeted at the two locations. The present invention relates to a method for generating instructions.

[Prior Art] In a computer system that divides instruction processing into multiple stages and performs pipeline processing by simultaneously executing different stages of a plurality of consecutively executed instructions, the instruction currently being executed (current instruction) At the time of execution, the instruction following that instruction (
This command will be called the next command. The next instruction (generally there may be a plurality of instructions) is in its interpretation stage in the instruction executor. If the current instruction is a normal instruction that does not cause a branch and does not change control, the execution of the current instruction and the interpretation of the next instruction will overlap and the pipeline will flow smoothly, but if the current instruction is a branch instruction etc. If the instruction changes control, the next instruction, which is already in the interpretation stage, must not be executed. To this end, the following methods may be used: 1) Preemptive control of the next instruction is not performed for an instruction that causes a branch; 2) An invalid instruction (NOP instruction) is inserted immediately after such a branch instruction. However, in the case of method (1) above, the overlapping instructions cannot be executed at that point, and the pipeline becomes disordered. Although the pipeline is not disrupted by inserting a NOP instruction in the case of method (2) above, a problem arises in that the effect of overlap execution is lost because a useless NOP instruction is executed.

An attempt to solve this problem is to make effective use of a delayed branch instruction and the instruction immediately following it in a RISC processor. This means that a branch instruction always executes the next instruction (in this case, the instruction placed immediately after the branch instruction), and the effect of the branch is delayed until the end of execution of the next instruction. The software moves an instruction that is placed to be executed before the current instruction or an instruction that is the target of a branch to the area where the next instruction to be executed is located (called a delay slot) to avoid the above pipeline disturbance. 2 This technology is described in the January 17, 1983 issue of Nikkei Electronics Magazine,
It is described on pages 135-136.

This is fine if the branch instruction is an unconditional branch, but if it is a conditional branch, the bus to be executed differs depending on whether the condition is met or not, so a delay slot placed by software is required to guarantee the execution result. It is necessary to execute or not execute the command.

In the precision architecture of HP (Heuret Barracard), an instruction (current instruction) nullifies the next instruction (next instruction). That is, there is a function for specifying that the effect is N○P in a field in the instruction word of the current instruction. As a result, even in conditional branch instructions, by invalidating the instruction in the delay slot only when necessary, the effect of pipeline execution of instructions can be obtained in one path of the conditional branch. This technique is described in the June 16, 1986 issue of Nikkei Electronics, pages 221-222.

On the other hand, in these RISC architectures, all instruction words are made to have a fixed length in order to reduce the burden of implementing pipeline execution of instructions as described above and to improve processing speed when interpreting instructions. It is designed to. Therefore, a situation arises in which the field of the l instruction is insufficient to address the entire space of the main memory. For example, if the instruction word length is 32 bits and there are 2 addresses in the main memory space where addressing is possible, the field for addressing that is part of the instruction word is less than 32 bits, and this field When specifying an offset from the reference point, an offset of 2 If cannot be fully expressed. Although there is a method to reset the value of the reference point, it is a burden for compiler creation.

To deal with this, computers with such architectures load or add values to the left part of the register (i.e. write a value of less than 32 bits in the instruction word field, and store this value when the instruction is executed). There is an instruction to shift the value to the left by several bits and load or add it to a register as a 32-bit value. After loading the offset of the address or the left part of the immediate value, another instruction is used to load the left part of the immediate value. Just use it.

[Problems to be Solved by the Invention] In the above-mentioned conventional technology, the following problem arises in that the fields of one instruction cannot express all address offsets and immediate values.

To use address values and immediate values that cannot be expressed with one instruction, a combination of two or more instructions is required. This combination of instructions must be determined by the assembly stage, so for example, for external variables whose address values cannot be determined at the compilation or assembly stage, the address value of the external variable will end up being 1. Even if the range can be sufficiently expressed by instructions, it is always necessary to combine two (or more) instructions, such as first loading O as the left part, obtaining the necessary reference point, and then using it. This increases the number of instructions and the execution time. In order to solve this problem with software, Architectural Support for Programming Languages and Operating Systems, 2nd International Conference Preliminary Lectures, 1987, pp. 119-120, has developed a small size that can be expressed in one instruction. A compiling method has been proposed that assumes that the linkage editor is instructed to place external variables separately.

If the above address value or immediate value can be sufficiently expressed with one instruction, it is possible to make the effect of the unnecessary instruction NOP by invalidating the next instruction, but in the above conventional technology, the next instruction is Whether or not to invalidate an instruction cannot be determined until the current instruction is executed, and since an invalidated instruction is executed as a NOP instruction, it is not possible to reduce the number of executed instructions by invalidating it alone. Furthermore, it is necessary to specify invalidation at the assembly stage.
This is an insufficient method to minimize the number of executed instructions during execution.

[Means for solving the problem] In order to solve the above problem, it is necessary to de-execute an instruction when it is in the execution preparation stage and before it is executed, that is, when it is in the instruction queue. Remove it as an instruction from the instruction queue, and delete the instruction placed next to that instruction (
You can replace it with the following command).

For this purpose, an instruction scheduler is provided.

An identification symbol indicating whether or not to execute the instruction word itself is given to the instruction word, thereby making the instruction word itself, rather than the immediately preceding instruction, the control information for executing/not executing the instruction word itself. This identification symbol may be a dedicated field within the instruction word, or it is also possible to use a specific case of an existing field.

If the field is to be dedicated, for example, a linkage editor may be used to generate an instruction therefor. moreover,
A detector is installed in the instruction scheduler to detect that the instruction is not executed based on the value of this identification symbol.

The instruction scheduler also controls the instruction queue section. In the instruction scheduler, according to the instructions of the instruction word, the instruction is deleted from the execution target, and the instruction is replaced with the next instruction without being sent to the instruction executor. Furthermore, the instructions that follow the instruction that is not executed in the instruction queue section are sequentially moved forward in the instruction queue section, and the subsequent instructions are input from the main memory to the instruction queue section. .

The instruction queue section needs to have a stage depth of three entries or more in order to hold at least the current instruction, the next instruction, and the next instruction after the next instruction.

[The operation command words are controlled so that one instruction is executed at timing ℃, and the next instruction is executed at the next timing t+1, and the contents of the instruction queue section are shifted forward one by one at each timing.

If the instruction word specifies that it should not execute itself, the detector detects that instruction. As a result, the instruction scheduler deletes the instruction from the execution targets. If the above deletion instruction is given at the right time, Shirashi +1
When the instruction-queue is shifted, the instruction scheduler obtains the position of the instruction to be deleted in the instruction queue section according to the deletion instruction, and deletes the instruction in the instruction queue section so that the instruction is deleted from the instruction queue section. This is achieved by sequentially shifting the instructions following the instruction to be executed one step at a time to the front of the queue.

As a result of the shift operation, a space is created in the final entry of the queue, so the next placed instruction is read from the main memory and stored as the final entry of the instruction queue section.

Through the above-described operation, as the instruction queue section shifts, an instruction that does not need to be executed is detected in the instruction queue section before the "interpretation" stage, and is deleted from the queue as a non-executable instruction. As a result, this instruction is not sent to the instruction executor and therefore does not need to be executed.

[Example 1] Hereinafter, an example of the present invention will be described in detail using the drawings. FIG. 1 shows the basic configuration of the apparatus of the present invention, which includes an instruction executor 101, a main memory 102, and an instruction advance controller 103. The instruction advance controller further includes an instruction queue section 104 and an instruction scheduler 105. In this embodiment, a device including a so-called cache memory is considered as the main storage device. In addition, in this embodiment, the instruction queue section has a depth of 4 stages (104-1, l04-2, 104-
3.104-・4). The instruction executor is for sequentially executing instructions supplied from the instruction advance controller, and may be a conventional pipeline processing instruction executor.
Detailed drawings and explanations regarding the configuration will be omitted.

The instruction advance controller has a function of reading an instruction word stored in the main memory, sending it to an instruction queue section in the instruction advance controller, and further providing it to the instruction executor. Note that the configuration related to reading instructions from the main memory is the same as that of the conventional system, and therefore a description thereof will be omitted.

The instruction scheduler includes a first selection circuit 107, a second selection circuit 108, an instruction detector 106, and a queue advancer 109.

A sequence of instructions to be executed in a program for this computer is stored in the main storage device 102. When starting a program, the address of the first instruction to be executed is given to the instruction scheduler. After startup, as many instructions as the depth of the queue is read from the main memory into the instruction queue section according to instructions from the instruction scheduler, and instructions are sequentially sent to the instruction executor from the beginning of the instruction queue section for execution. . In this embodiment, the instruction executor executes one instruction in three stages: "interpretation,""operation," and "result storage," and currently executes one instruction ( Assuming that the current instruction (current instruction) is in its "operation j stage," the instruction word at the queue position next to the head is sent to the instruction executor so that it is always executed even if the current instruction is a branch instruction, etc. be at the "interpretation" stage. That is, when the current instruction at the head of the instruction queue section is in the calculation stage at timing t, the next instruction after the head is in the interpretation stage. At the next timing t+1, that is, when the result of the current instruction is stored, the next instruction is sent to the head of the instruction queue section, and is sent as a new current instruction from the beginning of the instruction queue section to the instruction executor, and then enters the "operation" stage. I will make it happen.

This performs pipeline execution of instructions.

When one instruction word is sent from the instruction queue section to the instruction executor, the next instruction is forwarded to the start position, the instruction after the next instruction is forwarded to the next instruction position, and so on in the instruction queue section, and the pipeline progresses. Keep the flow. This is done by performing a cue advance operation by cue advancer 109. When one instruction word is sent to the executor, the instruction queue is advanced by one as described above, and the next instruction word to be sent to the instruction executor is stored in the main memory at the end of the empty instruction queue section. Read from device. It is also possible to advance the instruction queue and read from main memory in parallel.

It is assumed that all executed instructions of this computer have a fixed length of 32 bits. An instruction to read one word (data) in the main memory into a predetermined register in the instruction executor 101 has the following format. (Fig. 2(a)) If this is written in assembly format, it will be as follows.

LD reg breg :o
ffset Here, the instruction code part 201 (here LD) representing the type of instruction has 8 bits, the register specification part 202 (here treg, meaning target) into which the value should be read has 4 bits, and the main Value that should be the standard when specifying an address in memory (value of standard address)
The pace register specification part 203 (here, br
It is assumed that 4 bits are used for each of eg).

The above instruction LD accesses the main memory at the address of the value obtained by adding the offset value to the value of the reference address stored in the pace register specified by breg, and reads from the main memory. This is an instruction to store the specified contents in the register specified by t reg. In this case, only 16 bits can be used in the offset value section 204 (here, the Roffset section) representing the distance from the reference address. If the main memory to be addressed exceeds 65,535 addresses (in this example, it is assumed to be as large as can be expressed in 32 bits), it cannot be referenced by this instruction alone. For this reason, this computer is assumed to have an instruction to substitute the 16 bits of the upper digits that cannot be expressed into a register. (Fig. 2(b)) This is described in assembly format as follows.

AIU treg sreg ti
mm Here, AIU 205 is the instruction code (8 bits) that represents the type of this instruction, reg 206 is the register number (4 bits) for the result value, and Sreg 207 is the register number (4 bits) of the value to be operated. 4 bits) #i of 208
mm is an immediate value (16 bits). This command is
The value expressed in mm is shifted 16 bits to the left to generate a 32-bit value, which is added to the value of the register specified by s reg and assigned to the register specified by t reg. Using this AIU instruction, the above s
The register indicated by reg is set to register R5, and the instruction sequence for referencing a variable located at a point 100,000 addresses away from the reference address indicated by register R5 sets register R1 to the working register indicated by treg, and sets R2 to the above LD.
As a register to which the result of an instruction is assigned, AIU RI R5100000/6553LD
It can be expressed as R2R1100000%65536. Here, / represents integer division, % represents integer remainder bound, and in the above case, 100000/65536=1.1
It is assumed that 00000%65536=34464.

In the A and IU instructions in the above example, the value 1 is shifted to the left by 16 bits, the value of the reference address of register R5 is added to that value, and the resulting address is set as the new reference address (R1) as the main address. The storage device is accessed and the contents read from the main storage device are stored in register R2.

(First example) Now, consider the program piece x=y−z+g+1H. X, y, and Z are local variables that can be expressed using 16-bit offsets, and g is a non-local variable and the offset from pace register R5 is a variable that can be expressed using 16-bit offsets. Assume each. Considering the target code for this, since g is a non-local variable, its offset is not known at compile time.

Therefore, assuming that the offset from R5 can actually be expressed in 16 bits, even in this case, in the objective code, as shown below as the instruction sequence from ■ to ■,
Must be output as a combination of instructions.

■ LD R2y ■ LD R3z ■ SUB R2R3 ■ AIU RI R5g/65536 ■ L
D R3R1g%65536 ■ ADD R2R3 ■ ADI R231 ■ ST R2x Here, the variable name in assembly format is X! Let 3'lZ represent the base value and offset pair in the pace register for each, and let g represent the offset from the base value in pace register R5. In addition, SUB stores the difference between the first and second operands in the first operand, ADD similarly performs the sum, and ADI stores the value obtained by adding the immediate value of the second operand to the first operand in the first operand. , S
T stores the value of the first operand in the second operand,
The command shall be: Further, it is assumed that the register R1 stores a value equal to the value stored in the register R5.

This is currently the instruction queue 301 section (
104) in FIG. 1 and the current instruction is ■.

The depth of the queue is assumed to be 4. Therefore, as shown in FIG. 3(a), ① to ② are in the instruction queue section.

I'll take the timing at this point. The LD (302) of the current instruction ■, which is the head (first entry) of the instruction queue, is currently being executed in the "operation" stage, and at this time, the next position (
The LD (303) of the next instruction ■ in the second entry) is
It is currently in the "interpretation" stage by the instruction executor. If we pay attention to the AIU instruction 305 (■) in the fourth entry, based on the above assumption, the offset of g is within 16 bits from R1, so the offset part of the instruction (■) is ○. This value O is sent in 306-2, and the detector 307 (106 in FIG. 1) detects the value that the main instruction in the fourth entry needs to execute in combination with the instruction code AIU of the instruction word and the value 0 in the offset part. Detects that the instruction does not exist. A circuit for realizing this function can be realized as shown in FIG. 4(a), assuming that the bit pattern of the instruction code of A and IU in this example is '11001100'. In this example, the detector 106 is composed of two circuits (402 and 403 in FIG. 4), one each for the third and fourth entries.

This non-execution command 401 is transmitted to the first selection circuit 107. As shown in FIG. 1, the first selection circuit is configured as shown in FIG.
b) As shown at 404, two consecutive instruction words from the main memory to be held next in the instruction queue unit 104
The data lines (405, 406) for reading instructions and the data line 407 for reading the instruction of the fourth entry of this queue are input, and these inputs are performed depending on the presence or absence of a non-execution command from the non-execution command line 408. 2 out of 3 instructions given
One is sent to the fourth and third entries of the instruction queue section, respectively. In this example, at the current timing t, from 405
, 406 respectively send the command (■). The second selection circuit lO8 shown in FIG. Then, depending on the presence or absence of a non-execution command from the non-execution command line 412, one of these input two commands is sent to the second entry of the command queue section. The combination of each non-execution command and the output to be sent from each selection circuit is shown in FIG. 5(a).
, (b), and when a non-execution command is not detected, the instruction queue is advanced one step and the next instruction is read from the main memory.

In this example, when a non-executable instruction is detected in the fourth entry, the case shown in the lower row (*) of FIG. 5(a) is selected. When transitioning to timing +1, the fourth entry contains the instruction from the main memory (from 406), the third entry
Instructions from the main memory (from 405) are also sent to each entry. That is, so as to delete the instruction that was in the fourth entry at time t, subsequent instructions are sequentially advanced to the instruction queue section one by one.

(As shown in FIG. 3(b)) The above operations are performed by the instruction scheduler. At this point, the instruction marked ■ in the instruction queue section was not yet to be executed, so it was not sent to the instruction executor, and this unnecessary AIU instruction was deleted.

If a non-executable instruction is detected in the third entry of the queue, the second selection circuit selects the instruction in the fourth entry to the second entry, and from the main memory to the fourth and third entries, respectively, from L to t+1. The contents of the queue are shifted with the timing shift of , and the third entry instruction is deleted from the instruction queue.

(Second example) The above is an example of using a specific value of a specific field of an instruction word, called the offset field of an AIU instruction, to detect a non-executable instruction. It is also conceivable to provide an independent field that instructs non-execution of the program and set this field. A
Regarding the IU instruction, the instruction code 601, t as shown in FIG.
reg register specification section 602, s reg register specification section 603, :E im m immediate value specification section 604, and non-execution specification section 605 determine the format of the instruction word, and the execution/non-execution of this instruction is determined by the non-execution specification section 605. It is assumed that the field value is specified using 1 bit, and the value of this field is set by the linkage editor. That is, the one-cage editor is assumed to perform execution/non-execution designation in addition to relocation and the like. In the same situation as in the first example, the linkage editor that rearranged the external variable g shows that the offset of g is within 16 bits.

In the process of the linkage editor, this instruction word, which is the object of relocation, is also the object of execution/non-execution designation. The linkage editor has a function that recognizes that the immediate value specification section 604 has O in this instruction (AIU instruction) that is the target of execution/non-execution, and a function that recognizes that the immediate value specification section 604 has the value ○, a non-execution specification bit. 605 is newly retained. This process flow is explained in the seventh section.
As shown in the figure. In this example, in the relocation process of g in the AIU instruction (■), the offset of the second g is within 16 bits, that is, the immediate value specification part 604 of this AIU instruction is found to be the value O, as shown in FIG. 7 701. Therefore, at 702 in FIG. 7, the non-execution designation bit 605 is set to ON, and g is 16 bits, which designates the designated time. Further, the linkage editor has a function of changing the pace register field breg of the operand of the LD instruction following this AIU instruction to the value of the register s reg field which is the source operand of this AIU instruction (703 in FIG. 7). In this example, in the LD instruction ■ following the AIt, 'instruction in ■, R1
The value register R5 of the sreg field of the AIU instruction (2) is assigned to the breg field, which is a register. That is, in the LD instruction ■, register R5 is designated as the pace register instead of register R1.

With respect to the instruction in the instruction queue, the detector detects that the instruction does not need to be executed based on this non-execution designation bit. This detector is similar to that shown in FIG. 3 307, but is implemented with a detection device activated by a 1-bit ON-OFF. After this, as in the first example, the output from the selection circuit is determined and the queue advance operation is performed, so that the instruction ■ is deleted from the instruction queue section and the instruction ■ in the main memory is moved to the fourth loaded into the entry.

In this example, the base register field breg of the LD instruction ■ following the ATU instruction that was determined to be non-executable is
Since it is replaced with register R5, which is the correct base when the instruction is not executed, R1
There is no need to maintain the same contents in R5 and R5.

[Effects of the Invention] An instruction deleted from the execution target as an invalid instruction in the instruction queue is not executed even as a NOP instruction, so there is no burden on the program execution time. In addition, even if the address cannot be determined at the time of assembly, such as a reference to an external variable, it can be expressed by multiple instruction sequences, and once the actual address is determined during execution, the range By non-executing unnecessary load instructions in the upper part according to the number of instructions, reference can be made with a minimum number of instructions, and high-speed execution is possible.

Furthermore, since instruction words are not deleted at the target code level, there is no need to recalculate addresses, and there is no need for the linkage editor to separately place only small external variables, so there are no restrictions on data placement. This makes the process easier, and there is no need to put a burden on the compiler.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the basic configuration of an information processing apparatus according to the present invention. FIG. 2 is a diagram showing the format of a command word. FIG. 3 is a diagram showing the relationship between an instruction queue and a non-executable instruction detector. FIG. 4(a) is a diagram showing an example of the configuration of a detector, and FIG. 4(b) is a block diagram showing a specific configuration of the information processing apparatus of the present invention. FIG. 5 is a diagram showing a table of input/output relationships of the selection circuit. FIG. 6 is a diagram showing an instruction format with a non-execution designation bit generated by the linkage editor. FIG. 7 is a flow chart of generation processing for generating an instruction having a non-execution designation bit by the linkage editor. Ol...Instruction executor o2...Main memory 03...Instruction advance controller 04.301...Instruction queue section 05...
-Instruction scheduler 06.307...Instruction detector 07.404...First selection circuit 08.409-
...Second selection circuit 09...Cue advance device

Claims (1)

[Scope of Claims] 1. A main memory device, an instruction queue section, and an instruction advance controller that reads instructions from the main memory device, stores them in the instruction queue section, and controls the order of the contents of the instruction queue section. and an instruction executor that interprets and executes the contents stored in the instruction queue section as an instruction word, and executes the instructions in the instruction queue section in a pipeline with the instruction executor, the instruction advance control as described above. an instruction scheduler comprising a detection means for detecting that an instruction in the instruction queue section is a non-executable instruction; and a control means for deleting the detected non-executable instruction from the execution target and replacing it with an instruction following the instruction. An information processing device comprising: 2. The detection means is configured to detect a specific pattern in an instruction word consisting of a plurality of fields, and when the specific pattern is detected, it is determined that the instruction is a non-executable instruction. The information processing device according to item 1. 3. A field independent from other fields is provided in the instruction word to indicate whether or not it is a non-executable instruction, and the detection means is configured to detect the contents of the independent field. The information processing device according to item 2. 4. The information processing apparatus according to claim 1, further comprising a plurality of the detection means according to the number of stages of the instruction queue section. 5. Check whether the instruction generated by the external variable relocation process is an instruction to be determined as execution/non-execution, and if it is an instruction to be determined, determine whether to execute or not to execute, and check the determination result. An instruction generation method that generates an instruction by setting the field in a field independent of other fields in the instruction. 6. The instruction generation method according to claim 5, wherein the instruction is generated by a linkage editor.