JPS60241136A - Data processor - Google Patents

Abstract

PURPOSE:To improve both the versatility and the processing speed of a data processor by holding the upper and lower addresses of an instruction remaining within an instruction buffer and using the remaining instruction for processing as long as a branching destination address exists within said upper and lower addresses. CONSTITUTION:A data processor 2 connected to a main memory 1 includes upper and lower limit address registers 8 and 9 of a remaining instruction within an instruction buffer 4, a lower limit address incrementer 10, an address comparator 11 and a control circuit 12 in addition to the instruction buffers 3 and 4, an address register 5, an address adder 6 and an address incrementer 7. The branching destination address calculated by the adder 6 is compared with the addresses of registers 8 and 9 respectively. Then the presence or absence of the branching is checked for a remaining instruction within the buffer 4. If the branching is possible, the circuit 12 controls the suppression of an instruction read request given to the main memory 1.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a data processing device having an instruction prefetch control function when repeatedly executing the same instruction sequence using a branch instruction.

[Prior art]

FIG. 1 shows a conventional data processing device having an instruction buffer for performing prefetch control of instructions. In the figure, l is a main memory device in which instructions and data are stored. A data processing device is connected to the main memory. 3 is an instruction register, and DA is an instruction buffer, which is configured to be able to store a plurality of instructions. S is an instruction address register that holds the address of the instruction to be read. 6 is an address adder used to calculate a branch destination instruction address or operand address. 7 is an address incrementer used to increment the instruction address. The data processing device is started by setting a start address in the instruction address register 5. The activated data processing device λ stores an instruction address register 5 in the main memory l.
Send the address to request reading of the command. Instructions read from the main memory l are passed through the instruction buffer ψ'
C It is read out to the f6 instruction register 3 and processed. The instruction buffer adder is provided for the purpose of efficiently supplying instructions to the instruction register 3 even when the reading of instructions from the main memory device 1 is delayed due to a conflict with another device or the like. When the branch instruction is decoded by the instruction register 3, the branch destination address is calculated by the address adder 6, the branch destination instruction address is set in the instruction address register 5, and the branch destination address is stored in the main memory @i.
The branch destination instruction is read from the main memory 1 into the instruction register 3 via the instruction buffer adder, but it usually takes a long time to read it from the main memory 1. If the supply of the branch destination instruction to the instruction register 3 is delayed, the data processing device will have to wait for the instruction processing, which will impede the efficient operation of the data processing device. When the same instruction sequence is repeatedly executed, it is usually done by creating a loop using a branch instruction to return one branch destination address to the previously executed predetermined instruction address, as shown in FIG. When executing a series of instructions looped by such a branch instruction, the data processing device λ described above must read all the looped instructions, delay the readout time of the branch destination instruction, and read the operands. There is a drawback that the waiting time during instruction processing increases due to competition with instruction reading, resulting in a decrease in performance. In order to improve this drawback, the following countermeasures have been taken. As shown in Figure 3, when a loop is specified in a program, the compiler checks whether a loop exists or not when compiling this program. Type 1 of instructions included in the loop
This is a method of converting and executing new instruction codes by combining and ordering them. Note that this figure 3 is similar to the figure 2.
The sequence of instructions l to m shown in the figure is converted into new instructions l to new instructions t with different new instruction codes depending on the combination and order of the instructions. This shows that.

However, even in this method, there are disadvantages in that the program targets that can be processed are limited, and the combinations and orders of instructions included in the loop are limited, resulting in a lack of versatility.

In order to make it possible to execute any kind of loops including any two combinations and orders of instructions in the above method.

It is necessary to allocate a huge number of new instruction codes, and it is also necessary to build firmware or hardware that can process and execute each instruction code.Currently, only the most frequently used instruction types in a limited number of programming languages are used. Only combinations and orders can be selectively processed.

[Summary of the invention]

The present invention has been made to eliminate the drawbacks of the prior art devices and methods described above.

Its purpose is to provide versatility and improve processing speed when repeatedly executing the same instruction sequence in a loop, without depending on the combination or order of the two types of instructions included in the loop. The object of the present invention is to provide a data processing device with improved performance.

[Embodiments of the invention]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The configuration and operation of a data processing apparatus according to an embodiment of the present invention will be described below with reference to the drawings. In this figure, / to 7 are respectively the same as or equivalent to those shown with the same reference numerals in FIG. 1, so a detailed explanation thereof will be omitted. The upper limit address register indicates the upper limit address of instructions remaining in the buffer adder. Upper limit address register t is an instruction address register! When the requested instruction is read into the instruction buffer, the address of that instruction is stored in the instruction address register! The address is then transferred to the upper limit address register S and becomes the address of the most preceding instruction remaining in the buffer at that time. A lower limit address register 9 holds the lower limit address of the instructions remaining in the instruction buffer adder.

io is a lower limit address incrementer, and the instruction read into the instruction buffer t wraps the instruction buffer adder,
Each time it is overwritten and stored, the lower limit address register 10
, and generates the lower limit address of the instructions remaining in the instruction buffer adder. // is an address comparison circuit, and when a branch instruction is read into the instruction register 3, the branch destination address calculated by the address adder 6 is equal to the upper limit address of the instruction remaining in the instruction buffer adder held by the upper limit address register S. is smaller than the lower limit address and is larger than or equal to the lower limit address of the instruction remaining in the instruction buffer adder held by the lower limit address register 9 to detect whether there is a branch between the instructions remaining in the instruction buffer adder of the branch instruction. 12 is a control circuit, and when a branch instruction is read into the instruction register 3 and the address comparison circuit 1/ detects that the branch destination address calculated by the address adder 6 branches between the instructions remaining in the instruction buffer. , performs instruction read request suppression control to the main memory device 1, state control of the instruction buffer adder, instruction read control to the instruction register 7, and the like.

In the data processing device shown in FIG. V, m=3. As an example, assume that the capacity of the instruction buffer is 6 instructions.

Let's explain its operation. Now, if we assume that program processing is started by specifying address k in the instruction address register 3, the started data processing device is the instruction address register! sends the address k to the main memory device l, sends a request to read the command, and stores the read instruction O in the instruction no.
At the timing when the instruction address register S is stored in the rough adder, the address of the instruction address register S is transferred from the upper limit address register to the lower limit address register 9, and these are initialized. At the same time, instruction address register j is requested to read the next instruction.
Sends the address of 1 to the address incrementer 7, returns the result to the left of the instruction address register, and sends an instruction read request to the main memory l. The next read instruction l is stored in l of the instruction buffer adder. Timing instruction address register where instruction / is stored in instruction buffer adder! The address of is transferred only to the upper limit address register g. At the same time, a request is sent to the instruction address register 3, and this operation is repeated as long as there is space in the instruction address register 3.

Further, when instructions are stored in the instruction buffer adder, the instructions are sequentially read out from the instruction register 3 in a first-in first-out manner. The operation of increasing the lower limit address register 9 by 7 starts from the time when the instruction has made one cycle through the instruction buffer and a new instruction is stored above the 1st instruction.

Now, if the capacity of the instruction buffer Hiroshi is set to Am instructions, and up to instruction 6 is read to the instruction buffer adder and the branch instruction of instruction 3 is decoded in the instruction register 3, the calculated address value of address adder 6 is + /, upper limit The address value of the address register S is +4, and the address value of the left side of the lower limit address register is +/. At this time, the address comparator //
A branch condition between the remaining instructions in the instruction buffer adder is detected, and the instruction request to the main memory 1 is suppressed and the instruction register 3 of the branch target instruction remaining in the instruction buffer is
Control is performed such that instructions are supplied to the main memory 1 without reading them from the main memory 1. This state continues as long as the branch condition of the branch instruction is satisfied and the loop continues.

In this way, read delays for branch destination instructions are eliminated, and there is no longer a need to send read requests for instructions forming the loop to the main memory L, and operand read delays due to contention for accessing the operands to the main memory L are eliminated. It is possible to solve this problem and achieve high-speed operation of the instruction sequences that make up the loop. It is also clear that this operation does not depend on any particular combination or order of the instructions in the instruction sequence forming the loop. In this embodiment, the capacity of the instruction (rough adder) is set to 6 instructions, but by increasing this capacity, the same effect can be obtained even when there are many instructions forming a loop.Also, in this embodiment, the instruction number IJ -mu is 1
Although one case has been described, a similar effect can be expected even when there are multiple instruction streams.

〔Effect of the invention〕

As explained above, according to the present invention, a plurality of instructions fetched in advance from the main memory are held in an instruction buffer, and upper and lower limit addresses of remaining instructions are held in the instruction buffer. and while a predetermined relationship is maintained between the address of the branch instruction remaining in the instruction buffer and the upper and lower limit addresses, no instruction is fetched from the main memory. Furthermore, there is provided a data processing device that is highly versatile and has improved processing speed without depending on a single combination of instruction types or order.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example of the configuration of a data processing device having a conventional instruction buffer, FIG. A flowchart diagram illustrating a conventional high-speed processing method for an instruction sequence constituting a loop. FIG. , ? is the instruction register, ≠ is the instruction buffer, j is the instruction address register, 6 is the address adder, ri is the address incrementer, za is the upper limit address register, 9 is the lower limit address register, and lO is the data processing device. Lower limit address incrementer, /
/ is an address comparison circuit, and /λ is a control circuit. In each figure, the same reference numerals indicate the same or corresponding parts.兇11 Atsushi 2 and 3

Claims (1)

[Claims] In a data processing device having an instruction buffer capable of holding a plurality of instructions for fetching preceding instructions, an upper limit for holding the upper and lower limit addresses of the instructions remaining in the instruction buffer, respectively. It has an address register, a lower limit address register, and a comparison circuit that checks whether the branch destination address of the 1-branch instruction matches the address of the instruction remaining in the instruction buffer, and when the match is established, the main As long as reading of instructions from the storage device is inhibited and branching between remaining instructions is possible, instructions are read using the remaining instructions in the instruction buffer without fetching instructions from the main storage device. A data processing device that enables the execution of