JPS6349844A - Instruction prefetching device - Google Patents

Abstract

PURPOSE:To carry out an instruction with no delay by extracting a branching destination instruction after producing an instruction buffer address from the difference between a branching destination address and an instruction prefetching address as long as said difference is kept under the capacity of an instruction buffer. CONSTITUTION:A subtractor 8 obtains a difference between the branching destination address of the branch instruction estimated by a branch estimating buffer 6 and a prefetching instruction address. When said difference is smaller than the capacity of an instruction buffer 18, an instruction differential buffer 19 produces the read address of the buffer 18 based on said difference and then reads it out of the buffer 18 since this buffer 18 contains a branching destination instruction. Then an instruction is carried out with no delay.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction prefetching device, and more particularly to a prefetching device for a branch destination instruction when the branch destination instruction of a branch instruction is in a branch buffer.

[Conventional technology]

Conventionally, this type of instruction prefetching device uses, when there is a branch destination instruction in the instruction buffer, the branch destination address at the time of execution of the instruction to store the branch destination instruction in the instruction buffer as shown in the correspondence table between one branch destination address and the instruction buffer address. A certain branch destination instruction was being retrieved. Devices with a branch prediction buffer preempt the branch destination instruction even if there is a branch destination instruction in the instruction buffer. A representative example of such a prediction method is Japanese Patent Application Laid-Open No. 57-2015.
It is shown in Publication No. 55.

[Problem that the invention seeks to solve]

The above-mentioned conventional instruction prefetching device does not know the branch destination address until the branch instruction is executed, so it has the disadvantage that in the case of a pipeline computer, it is difficult to fetch two branch destination instructions without delay.

Furthermore, in the case of a prefetching device having a branch prediction buffer, the instruction is prefetched even though the branch destination is already in the instruction buffer, so there is a drawback that the branch must wait until the instruction is supplied.

FIG. 4 corresponds to a group of instructions as shown in FIG.

The operation of prefetching and executing instructions in a device having a branch prediction buffer is shown. Preemption of command D -) A→P
-) C-) The command is fetched in the T stage and the instruction is executed in the D-+A→P-+C-+'r-+E→W stage.

If there is a branch instruction TNZ, execution of the instruction will be delayed because one branch destination instruction = LD instruction is fetched.

[Means for solving problems]

The device of the present invention is an instruction prefetching device equipped with a branch prediction buffer that predicts the branch destination address of one branch instruction, and the instruction prefetching device is configured to combine the branch destination address of the branch instruction predicted by the branch prediction buffer and the preemption instruction address. The present invention is characterized by comprising means for determining the difference, and means for generating a read address of the instruction buffer using the difference when the difference is smaller than the capacity of the instruction buffer to output the branch destination instruction from the instruction buffer. do.

〔Example〕 Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In Figure 1, 1 is the instruction decoding stage (D stage)
instruction prefetch instruction counter (DFIC).

2 is a selector that switches between the DFIC 1 and the instruction counter 4 for instruction prefetching; 3 is an adder that increases the output of the ri selector 2 by 1; 4 is an adder; 4 is an adder; instruction counter (A
EIC), 5 is an instruction counter (PFIC) for instruction preemption of the P stage, 6 is a branch prediction buffer that outputs a hit signal and a branch destination address when a hit occurs due to the output of PFIC 5, and holds the branch address of the ljD stage. Branch destination address register (DBIC), 8 is PFICs
1tH-j which calculates the difference between the contents of the branch prediction buffer 6 and the branch destination address of the branch prediction buffer 6, and outputs the difference if it is within the capacity of the instruction buffer, and outputs +1 in other cases.
A selector that switches between the output of the subtracter 8 and +1 according to the hit signal, 9 is the virtual address (PVA) of the P stage, 1
A register that holds the address difference of 1riP stage (P
D), a register (CD) that holds the address difference of the 12riC stage, and a register (TD) that holds the address difference of the 13riT stage.

14 is an address translation buffer that inputs the output of register 9 and outputs a real address, and 15 is a register (CR) that holds the real address of the ric stage.

16 is a cache that outputs instructions by manually inputting the output of the register 15, a register z (TIR) that holds instructions at the -17riT stage, an instruction buffer (IB) that holds 18ri4 instructions, and 19 corresponding to the instruction buffer 18. Instruction Difference Buffer (IBD) to hold differences.

20 is a manual pointer (IPNT) that provides the write address of the instruction buffer 18 and instruction difference buffer 19;

21 is an adder that adds 1 to the contents of the input pointer 20; 22
is an output pointer (LOPNT), 23r, which provides the read address of the instruction buffer 18 and instruction difference buffer 19.
The output pointer 22 is set by the output of the i-instruction difference buffer 19.
24 is a register (DIR) that holds D stage instructions.

Next, the operation of this embodiment will be described.

Now, as shown in Figure 2, the contents of the memory are stored in the A register (
LDA instruction to load into AREG), memory and ARE
and an ADA instruction that adds each content of G.

A case will be described in which the TNZ instruction, which branches to the above-mentioned LDA instruction when the indicator does not become O, and the LDA instruction are executed.

The contents of DPICI are incremented by 1 in adder 3 and sent to AFIC4.
Enter. The contents of AFIC4 are PFIC5 and PDA
Further, the contents of PVA9 are converted into addresses by the address conversion buffer 14, and are held in the CRA 15 as real addresses.

Next, the command is retrieved from the cache 16 by the CRA 15, and sent to the IBI 8's PNT 20 via the TIR, 15.
Store at the address indicated by . Next, 0 of lB18
The instruction is taken out from the address indicated by PNT22, set in DIR24 at the first stage of instruction execution, and executed.

In the case of a branch instruction, the minute M is specified at the address of PF'IC5.
The prediction buffer 6 is accessed to fetch the branch destination address to the DBIC 7 and set in AFIC,i, thereby prefetching the branch destination instruction.

In FIG. 2, when the TNZ instruction branches to I and DA instructions and loops, the LDA instruction has already been taken out in IB18. Therefore, the subtracter 8 calculates the address difference (-2) between the JTND instruction and the LDA instruction, and
Store in BD19.

Next, when the TNZ instruction is executed, when the TNZ instruction enters DIR24, -2 is subtracted from 0PNT22 (OPNT
=2-2=0) Allows the branch destination LDA instruction to be retrieved next.

Therefore, as shown in FIG. 3, it is not necessary to take out one branch destination instruction, so the instruction can be executed without delay.

〔Effect of the invention〕

As explained above, the present invention calculates the difference between the branch destination address and the instruction preemption address, and if it is within the instruction buffer capacity, there is a branch destination instruction in the instruction buffer, so the instruction buffer address is calculated from the difference. By creating and fetching the branch destination instruction, there is no need to prefetch the branch destination instruction, which has the effect of improving performance.

[Brief explanation of the drawing]

Fig. 1 shows one embodiment of the present invention, Fig. 2 shows an example of a group of instructions,
FIG. 3 shows an operational diagram of instruction prefetching and instruction execution according to the present invention, and FIG. 4 shows an operational diagram of conventional instruction prefetching and instruction execution. 1.4.5... Instruction counter for instruction prefetching, 2
゜10... Selector, 3.21... Adder, 6... Branch prediction buffer %7...
・Branch destination address register, 8...Subtractor, 9
,11,12,13,15゜17.24...Register, 14...Address translation buffer, 16
... Cache, 18 ... Instruction buffer, 19 ... Instruction difference buffer, 20 ...
・Input pointer, 22...Output pointer, 23
・・・・・・Adjustment 1st concave 2 figimaqshimagyogu 3rgJ 4th flash

Claims (1)

[Scope of Claims] In an instruction prefetching device equipped with a branch prediction buffer for predicting an instruction destination address of a branch instruction, a difference between a branch destination address of a branch instruction predicted by the branch prediction buffer and a prefetching instruction address is determined. An instruction prefetching device comprising: means for creating a read address of the instruction buffer using the difference when the difference is smaller than the capacity of the instruction buffer, and reading a branch destination instruction from the instruction buffer. .