JPS59223850A - Pre-read control system of instruction - Google Patents

Abstract

PURPOSE:To increase the processing speed for a pre-read control system for instructions by storing the instructions forming a program in the order of addresses, recognizing the storage of an instruction corresponding to the address of a branching destination when a branch instruction is detected, and designating the storing area through an instruction reading means. CONSTITUTION:A common memory 1 stores the instruction groups forming a program, and an address counter 2 indicates the address of an instruction related to the pre-read on the memory 1. A pre-read memory 3 stores a pre-read instruction and serves as a first-n/first-out memory which stores the instructions with which the reading is through excepting for a prescribed number K of instructions. A write counter 4 indicates a store area on the memory 3 which should store the pre-read instructions. While a read counter 5 indicates the store area on the memory 3 corresponding to an instruction when said instruction is fetched out of K units of instruction groups which are stored in the memory 3. An instruction read register 6 stores an operation code OP and an operand OPR which are extracted out of the memory 3.

Description

[Detailed Description of the Invention] (Technical field to which the invention pertains) The present invention relates to an instruction prefetch control force formula, and is intended to improve the efficiency of the entire instruction prefetch process that is executed in the process of program processing by an electronic computer. (Prior art and its problems) As a conventional example of this type of instruction prefetch control system, in the process of program processing, the next instruction is prefetched in the order of the program, and the prefetched instruction is stored in a register, buffer, etc. Therefore, there is an instruction prefetch control method that aims to speed up program processing. In such conventional examples, if a branch instruction exists in a program and it becomes necessary to rewrite the program address according to the branch instruction, the look-ahead of the next instruction executed when interpreting the branch instruction becomes invalid, and the branch The address of the new branch destination instruction (branch destination address) specified by the instruction must be calculated, and the instruction specified by that address must be read. Therefore, in this type of conventional instruction prefetch control system, the flow of instruction prefetch control is interrupted by the presence of a branch instruction, and there is a problem in that the effect of saving program processing time by prefetching instructions cannot be realized.

On the other hand, if a branch instruction whose branch destination address can be calculated at the time of prefetching the instruction, that is, an unconditional branch instruction or a conditional branch instruction with an absolute or relative address specified, is #;a <In look-ahead processing, the instructions that follow the branch instruction in the program and the instructions at the branch destination are read-ahead, these instructions are stored in a separate buffer, and then the branch instruction is processed. An instruction prefetch control system that immediately retrieves the corresponding instruction from one of the buffers when the branch destination becomes clear during the process was published in Japanese Patent Laid-Open No. 57.
-3142.

Generally, the instruction prefetch control method is based on the program flow.
For example, as shown in Figure i1, instructions A to F
A small loop (near & +4
1 loop) exists, and its short distance N1. This is particularly effective for processing that passes through branch instructions that form a loop many times.

However, according to the conventional example of '('y 2), when a short-distance loop as shown in the first figure is processed many times and branch instructions are frequently processed, the memory for reading the instruction is Since the frequency of access inevitably increases, there is a problem that the common path becomes congested.Furthermore, in the process of branch instruction processing, instructions read ahead, that is, two instructions E and B in the example shown in the first figure, are stored. When the breadthreader is composed of several stages, such as a so-called first-in first-out memory, a problem arises in that control after the branch destination is determined is complicated.

(Object of the Invention) An object of the present invention is to eliminate such conventional problems and reduce the number of memory accesses associated with branch instructions without interrupting the flow of instruction prefetch control within a short distance loop. The object of the present invention is to provide an instruction prefetch control method that can increase the program processing speed of a computer.

(Summary of the Invention) In order to achieve the above object, the present invention provides a storage means for storing a plurality of instructions constituting a program in the order of addresses corresponding to the IQ difference of the program, and a storage means for storing a plurality of instructions constituting a program in the order of addresses corresponding to the IQ difference of the program, and a storage means for storing the instructions stored in the recording means. Addressing means specifies an address to the storage means and causes the instruction specified by the address to be outputted from the storage means; an instruction storing means for storing in a storage area provided for each separate instruction in the order of address; an instruction for specifying a storage area and reading out an instruction stored in the designated storage area; a +2°C output means; an instruction processing means for processing the read instruction and controlling the address specification by the address specifying means; a branch instruction detection means for detecting that the read instruction is a branch instruction; A recognition means for recognizing that an instruction corresponding to a branch destination address indicated by the branch instruction is stored in the instruction storage means when the branch instruction is detected; and an instruction storage means for recognizing whether the instruction corresponds to the branch destination address indicated by the branch instruction. an instruction that causes the instruction reading means to specify a storage area for the instruction corresponding to the branch destination address if the branch destination address is determined when the branch instruction is processed by the instruction processing means; The present invention is characterized by comprising a readout control means.

(Example of the invention) Hereinafter, the present invention will be described in detail with reference to the drawings.

FIG. 2 shows an example of the configuration of a control device according to the command prefetch control system of the present invention. Here, 1 is a common memory that stores a group of instructions constituting a program, and 2 is an address counter that indicates an address on the common memory l of an instruction related to prefetching. Reference numeral 3 denotes a prefetch memory for storing prefetched instructions, and is used as a first-in/first-out memory that always stores only a predetermined number of instructions that have been read out. 4 is a write I counter that indicates the storage area on the lookahead memory 3 where the prefetched instruction is to be stored; This is a read counter that indicates the storage area of memory 3. Reference numeral 6 denotes an instruction read register in which the operation code (opcode) OP and operand OPR of the instruction taken out from the preread memory 3 are stored.

7 is an operation code determination circuit that determines the operation code OP of the instruction stored in the instruction read register 6; 8 is an addition η circuit;
9 is a comparison circuit, 10 and 11 are AND gates, 12 is a gate, and 13 is an instruction execution control section for controlling instruction processing and each section.

Next, the operation of the control device shown in the second diagram will be explained.

In response to a command from the instruction execution control unit 13, the address counter 2
The instruction in the common memory 1 whose address is specified by is allocated to the storage area on the look-ahead memory 3 indicated by the write counter 4, and the write counter 4 and the address counter 2 are updated. When reading an instruction from the pre-read memory 3, the instruction addressed by the read counter 5 or the instruction read register 6 is read from the pre-read memory 3.
is set, and the read counter 5 is updated.

Here, the content of the instruction read register 6 is an instruction to branch to an instruction allocated to an address indicated by a relative value from the address of the branch instruction, and is often used when forming a short-distance loop. The processing in the case of a relative branch instruction will be explained.

The operation code determination circuit 7 determines whether or not the operation code OP of the instruction stored in the instruction 1 extraction register 6 is a relative branch instruction, and outputs a signal JMP when determining that it is a relative branch instruction. . Further, the comparison circuit 8 calculates that the operand 1) PR of the relative branch instruction stored in the instruction read register 6, that is, the relative value indicating the relative address is K<I)PR<Q (1)
If it is within the range of , it is determined that the instruction corresponding to the branch destination address indicated by the relative address remains in the look-ahead memory 3, and the signal FE is output as 1'').

On the other hand, the instruction execution control unit 13 processes the relative branch instruction,
When a branch is established, a signal S1 is output, and
Address 1 [No. 1 S2 indicating the address in the common memory l where the branch destination instruction is stored is output to the address counter 2. At this time, if the 4''+ numbers JMP and FE are both at active level, the gates 11 and 12 supply the voltage to the load terminal L2 of the address counter 2, the clear terminal C4 of the write counter 4, and the clear terminal C5 of the read counter 5. The signal S3 is activated, and the values stored in the respective counters are held. Also, the signal S4 supplied to the load terminal L5 of the read counter 5 by the gate 10 becomes active level. The circuit 8 performs an operation of adding the value indicated by the operand 1) PR stored in the instruction read register 6 to the value of the read counter 5, and loads the result into the read counter 5.

When condition (1) is not satisfied or when processing a branch instruction other than a relative branch instruction, the address counter 2 is loaded with the branch destination address, and the write counter 4 and read counter 5 are cleared or initialized. ,
Prefetch processing is newly performed for the instruction stored at the address indicated by address counter 2.

Branch instruction processing corresponding to the program flow shown in FIG. 1 will be explained using FIGS. 3A and 3B. here,
It is assumed that the instructions A to E shown in FIG. 1 are stored in the preread memory 3 in address order as shown in FIGS. 3A and 3B. First, as shown in FIG. 3A, the instruction execution control unit 1
When No. 3 attempts to execute a relative branch instruction, read counter 5 and write counter 4 indicate the address of one instruction and the next address of instruction F, respectively.

Then, when the relative branch instruction is executed and it is found that the branch is taken, the read counter 5 indicates the address of the instruction B, as shown in FIG. 3B.

(Effects of the Invention) As described above, according to the present invention, a read-ahead memory is provided that stores a pre-read instruction group over a predetermined range, and when a branch instruction is satisfied, the branch destination address is If the indicated branch destination instruction remains in the read-ahead memory, the read counter indicates and reads that branch destination instruction, so that the flow of control is not interrupted for branches within a predetermined range and is common. Since there is no need to repeatedly read the branch destination instruction from memory and the number of memory accesses is reduced, the program processing speed of the computer can be increased.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of an example of a program flow, FIG. 2 is a program diagram showing an example of the configuration of a control device according to the command prefetch control force type of the present invention, and FIGS. 3A and 3B are diagrams similar to those shown in FIG. FIG. 2 is an explanatory diagram of branch instruction processing corresponding to the program flow of FIG. l...Common memory, 2...Address counter, 3...Read ahead memory, 4...Write counter, 5...Read counter, 6...Instruction read register, 7...Op code judgment circuit , 8... Addition circuit, 9... Comparison circuit, 10.11... Ant gate. X2...Nant gate, 13...Instruction execution control unit, 14...Common bus, St, S2. S3. S4. FE, JMP...Signal, C
;4, C:5...Clear terminal, L2, L5...Load terminal, A, B,..., F...Instruction. Patent applicant: Fuji Electric Manufacturing Co., Ltd. Applicant: Fuji F7COM Control Co., Ltd. Figure 3A 3 Figure 3B

Claims (1)

[Scope of Claim] A storage means for storing a plurality of instructions constituting a program in the order of addresses corresponding to the flow of the program. Addressing means for specifying the address of the instruction stored in the storage means to the storage means and outputting the instruction with the specified address from the storage means; and the instruction including the outputted instruction. an instruction storage means for storing a predetermined number of instructions previously output in succession in a storage area provided for each separate instruction in the order of the addresses; an instruction reading means for reading a stored instruction; an instruction processing means for processing the read instruction and controlling address specification by the addressing means; and the read instruction is a branch instruction. branch instruction detection means for detecting a branch instruction; and when the branch instruction detection means detects a branch instruction, the branch instruction detection means recognizes that an instruction corresponding to a branch destination address indicated by the branch instruction is stored in the instruction storage means. and a recognition means that recognizes that the instruction sent to the branch destination address is stored in the instruction storage means, and when the instruction processing means processes the branch instruction, the instruction processing means executes the branch instruction. When the destination address is confirmed,
An instruction prefetch control system comprising: instruction read control means for causing the instruction read means to specify a storage area for an instruction corresponding to the branch destination address.