JPS63178335A - Microprocessor - Google Patents

Abstract

PURPOSE:To properly use a branch instruction in accordance with the flow of a program and to attain a rapid processing by preparing two kinds of conditioned branch instructions, using one branch instruction for prefetching the contents of branched address and using the other for prefetching the contents obtained by increasing '1' to the contents of a program counter. CONSTITUTION:When an instruction is inputted to a queue buffer 4 through an I/O control circuit 3, a predecoder 7 decides whether the instruction is a branch instruction or not. When the instruction is a branch instruction 1, data inputted to the succeeding queue buffer are added to the contents of a program counter 5 by a branched address control circuit 8, the added result is inputted to a program counter 5 and the contents of the program counter are entered to the queue buffer 4 until the succeeding prefetch. When the instruction decoded by the predecoder is a branch instruction 2, the contents of an address obtained by increasing '1' to the contents of the program counter are entered into the queue buffer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprocessor that employs a proactive control method, and particularly relates to improvements in its high-speed processing.

[Conventional technology]

FIG. 3 is a block diagram of a conventional microprocessor that employs a proactive control method. In the figure, 1 is the execution unit (ELI), 2 is the bus interface unit)
(BIU), 3 is an input/output control circuit, 4 is a queue buffer, 5 is a program counter, and 6 is an EU control circuit.

Note that the EUI includes ALtJ, etc., which are not shown. The BIUZ also includes a BIU control circuit (not shown), and the BIU control circuit controls the queue buffers 4.
Program counter5. It exchanges signals with the input/output control circuit 3 to control the B1U2. Further, the BIU control circuit is the execution unit control circuit 6 in EUl.
Signals are also exchanged between the two.

Next, the operation will be explained. The microprocessor is 2
Consists of two units, namely EUI and BIU2,
Each circuit operates independently by exchanging signals between the EUIIIJW11 circuit and the BIU control circuit.

In the BIU 2, when the queue buffer 4 is empty, an instruction is prefetched through the input/output control circuit 3, stored in the queue buffer 4, and the contents of the program counter are incremented by 1. The above operation is repeated until the Cuban sofa is full. In EUl, each byte is fetched from the queue buffer into the execution unit control circuit 6, the instruction is decoded, and processing is performed according to the contents of the instruction.

In this way, in the advance control method, since the instructions are prefetched, there is no idle time between executing the instruction and fetching the next instruction, thereby increasing the processing speed.

However, if the prefetched instruction is a branch instruction, the next data is prefetched to the Cuban sofa while the branch instruction is moved from the Cuban sofa to the EU, decoded, and the branch destination is set in the program counter. , In order to fetch the contents of the address of the program counter by the branch instruction, all the contents of the Cuban sofa that had been prefetched up to that point are cleared.
This will result in waste.

[Problem that the invention seeks to solve]

Conventional anticipatory control type microprocessors are configured as described above, so when executing a branch instruction, unnecessary data is prefetched due to anticipatory control, and the execution unit is idle while fetching the branch destination data. There was a problem that the condition

The present invention was made to solve the above-mentioned problems, and it is an object of the present invention to provide a microprocessor that can eliminate the idle state of the execution unit due to branch instructions.

[Means for solving problems]

The microprocessor according to the present invention provides two types of instructions as branch instructions, and when a prefetched instruction is determined to be a branch instruction, the microprocessor prefetches the data at the branch destination or the next one depending on the type of the branch instruction. The configuration is such that it is decoded to determine whether data at the address is to be prefetched.

[Effect]

In this invention, since two types of branch instructions are prepared, the branch instructions can be used selectively depending on the flow of the program to speed up execution.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a microprocessor according to an embodiment of the present invention, in which 1 is EU and 2 is B I U.

3 is an input/output control circuit, 4 is a queue buffer, 5 is a program counter (PC), 6 is an execution unit control circuit, 7
8 is a predecoder, and 8 is a branch destination control circuit. 20 again
A prefetch control means is composed of the predecoder 7 and the branch destination control circuit 8.

FIG. 2 illustrates the control operation of a microprocessor according to an embodiment of the present invention.

In this example, two types of instructions that branch under certain conditions are prepared, one instruction is set as the first branch instruction (hereinafter referred to as branch instruction l), and the content of the branch destination address is given priority and fetched into the Cuban sofa. The other instruction is set to be a second branch instruction (hereinafter referred to as branch instruction 2), and the other instruction is set to execute the same operation as a conventional branch instruction.

Next, the operation will be explained using FIG. 2. When an instruction is fetched into the Cuban couch 4 via the input/output control circuit 3 (step Sl), the predecoder 7 determines whether it is a branch instruction (step 32), and if the instruction is branch instruction 1 (step 33° S5), the data taken into the next Cuban sofa (data specifying the address of the branch destination) and the contents of the program counter 5 are added in the branch destination control circuit 8 (step S6), and the result is added to the program. The contents of the program counter are entered into the counter 5, and in the next prefetch, the contents of the program counter are taken into the queue buffer (step Sl). When the instruction decoded by the pre-decoder is branch instruction 2 (step S5), the data at the address where the program counter is incremented by one is taken into the queue buffer (step S4.Sl), as in the prior art.

With this kind of operation, when executing a program with the flow shown in Figure 4, the conditions are satisfied as follows.
If this occurs more frequently than when the branch is not established, you can use branch instruction 1 as the branch instruction when creating the program, thereby eliminating the idle time between fetching the branch destination data after determining the condition. , high-speed processing becomes possible. Furthermore, if the probability that the condition is not met is greater, branch instruction 2 may be used.

〔Effect of the invention〕

As described above, according to the microprocessor of the present invention, two types of conditional branch instructions are prepared, one for prefetching the contents of the branch destination address, and the other for prefetching the contents of the program counter by one. Since the setting is made to perform prefetching, high-speed processing is possible by using different branch instructions depending on the flow of the program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a microprocessor according to an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the microprocessor of FIG. 1, FIG. 3 is a block diagram of a conventional microprocessor, and FIG. FIG. 3 is a diagram showing the flow of a conditional branch instruction. In the figure, 1 is an execution unit, 2 is a bus interface unit, 3 is an input/output control circuit, 4 is a Cuban sofa, 5 is a program counter, 6 is an execution unit control circuit, 7 is a predecoder, 8 is a branch destination control circuit, 20 is a prefetch control means.

Claims (2)

[Claims] (1) A microprocessor that uses a proactive control method has two types of instructions that perform the same conditional branch, and when the first branch instruction is prefetched, the prefetch of instructions after that branch instruction is Starting from the address number, the second
1. A microprocessor comprising prefetch control means for controlling prefetch so that when a branch instruction is prefetched, an instruction at an address following the branch instruction is prefetched. (2) The prefetch control means includes a predecoder for determining whether a prefetched instruction is a branch instruction, and a predecoder for determining whether the prefetched instruction is a branch instruction; 2. The microprocessor according to claim 1, further comprising a branch destination control circuit for setting either the address address of the branch instruction or the address address following the branch instruction.