JPH04145531A - Microprogram controller - Google Patents

Abstract

PURPOSE:To make the processing speed of the title controller faster by providing an address code conversion table which stores branched instruction codes by the amount of a prefetch queue. CONSTITUTION:An address code conversion table 2 is composed of a code section having a width equal to the maximum number of bytes contained in a prefetch queue and an address section for storing addresses of branch instructions. When coincidence is found between the content of a program counter register 8 and one of the addresses stored in the address section of the table 2 as a result of comparison, the branched instruction codes stored in the code section of the table 2 is transferred to prefetch registers 4-6. When the address of a branch instruction hit the table 2 in such way, the prefetch queue becomes ready without fetching operations. Therefore, the time loss required for making prefetch queue correcting work at the time of executing branch can be minimized and the execution performance of the system can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram control device, and more particularly to a microprogram control device that has an instruction code prefetch queue and performs pipeline control.

[Conventional technology]

Conventionally, in a microprogram control device that performs briefetch control, when a branch operation is performed, the brief is fetched and all pre-instructions are invalidated. was common.

[Problem to be solved by the invention]

In the microprogram control device described above, which requires re-fetching the instruction code set in the prefetch queue every time a branch operation is performed, the overhead during branching is large. There was a problem in that the processing speed slowed down when running a program that frequently performed .

[Means to solve the problem]

The microprogram control device of the present invention has an instruction code grid, a microprogram control device K> that performs pipeline control, a code portion having a width corresponding to the maximum number of bytes that can be put in the prefetch queue, and a branch. A branch address-code conversion table consisting of an address field that stores the address of an instruction;
When a branch instruction appears and the branch is executed, the address part of the above address-code conversion table is searched to see if there is an address that matches the address of the branch instruction, and if there is no match, proceed as usual. The branch destination instruction is fetched seven times and set back into the prefetch queue.At the same time, one entry is taken from this address-code conversion table and the address of this branch instruction is written in the address field.

The code section stores each instruction code of the branch destination to be Seratosed in its prefetch queue, and if a match is found as a result of the search, extracts the code section from the address-code conversion table mentioned above, and stores it in the fetch queue. By setting this to , the 7-step time required for the prefetch queue is omitted and the branch operation can be performed quickly.

[Effect]

In the present invention, with respect to the execution speed of branch instructions, which greatly affects the execution performance of the system, by having an address-code conversion table that stores the code of the branch destination instruction for the number of prefetch queues, it is possible to To minimize time loss during prefetch queue correction work.

〔Example〕

Embodiments of the present invention will be described in detail below based on the drawings.

The figure is a block diagram showing one embodiment of the present invention.

In the figure, 1a is a microprogram control device to which the present invention is applied, 1b is an input terminal to which data from the outside is applied, and 2 is a code section that has the maximum number of bytes that can be placed in the prefetch queue.

A branch address-code conversion table consisting of an address section that stores the address of a branch instruction, 3 a conversion table management block that manages this address-code conversion table 2, 4, 5.6 a prefetch register for instruction codes, and T a The current instruction register contains the currently executing instruction. 8 is the program counter register that stores the program counter indicating the address of the currently executing instruction. 9 is the program counter register that stores the program counter indicating the address of the currently executing instruction. 9 determines the condition when a branch instruction is issued and executes the branch. A branch condition determination block 10 is used to determine whether or not to execute a branch, and 10 is an instruction code bus that transmits an externally applied instruction code to a prefetch register 4 and an address-code conversion table 2.

Note that the prefetch registers 4, 5, and 6 form a three-stage prefetch queue.

When a branch instruction appears and the branch is executed, the address part of the address-code conversion table 2 is searched to see if there is an address that matches the address of the branch instruction, and if there is no match, The branch destination instruction is fetched and set in the prefetch queue as usual, and at the same time, one entry is taken in the address-code conversion table 20, and the address of this branch instruction is written in the address field. The code section stores each branch destination instruction code to be set in the prefetch queue, and if a match is found as a result of the search, the code section of address-code conversion table 2 is extracted and the prefetch queue is By setting this, the configuration is such that the seven processing time required for the prefetch queue is omitted and the branch operation is performed quickly.

Next, the entire operation of the embodiment shown in this figure will be explained.

First, when a normal instruction other than a branch instruction is being executed, the prefetched instruction is first set in prefetch register 4, and then set in current instruction register γ. 4→prefetch register 5→prefetch register 6→current instruction register γ, and when set in current instruction register 7, execution of the instruction starts.

ffK, the case where the instruction set in the current instruction register T is a conditional branch instruction will be explained. First, the branch condition judgment block 9 judges whether the condition is satisfied or not, and if the condition is not satisfied, the prefetch register 6
The next instruction is transferred to the current instruction register 7, and execution of that instruction begins. On the other hand, if the condition is met, this is communicated to the conversion master management block 3, which reads the contents of the program counter register 8 in which the address of the branch instruction is set and converts it into the address part of the address-code conversion table 2. Let's compare. If there is no match, the address of the branch destination is calculated, the instruction is fetched, and the instruction is set in the prefetch register 4, as in conventional devices.At this time, one entry in the address-code conversion table 2 is Also set it in the (A) field of the code section. Here, when the address code conversion table 2 is full, the oldest entry is removed and used. Then, the following two instructions are fetched 7 times, and the fetched instructions are set in prefetch register 4 while transferring from prefetch register 4 to prefetch register 5 to prefetch register 6, but at the same time. Code part of address-code conversion table 2 (
Also set in the B) field and the (C) field. Further, the address of the branch instruction is set in the address field of the entry.

The preparation of the prefetch queue is thus completed, and the instruction in the prefetch register 6 is transferred to the current instruction register 7 to resume execution.

On the other hand, if there is a match between the address part of the program counter register 8 and the address-code conversion table 2, the instruction code of the branch destination is stored in the entry code part for three instructions, so it is prefetched. Transfer to queue. That is, the contents of the (A) field of the code section are sent to the prefetch register 6, (B)
Field contents to prefetch register 5, (C)
By simultaneously transferring the contents of the fields to the prefetch register 4, one step of preparing the prefetch queue is completed.

In this way, when the address of a branch instruction hits the translation table, the fetch operation, that is, the preparation of the prefetch queue is immediately completed without memory access, so that losses during branch execution can be minimized. This method is especially effective in cases where the branch instruction at the same location branches many times, such as in a loop operation, where the hit rate is very high.

〔Effect of the invention〕

As explained above, the original E! Regarding the execution speed of branch instructions, which greatly affects the execution performance of the system, A has an address code conversion table that stores the code of the branch destination instruction by 7 times.
This has the effect of minimizing time loss in prefetch queue correction work during branch execution, and greatly improving system execution performance.

[Brief explanation of the drawing]

The figure is a block diagram showing one embodiment of the present invention. 2...Branch address-code conversion chifur,
3... φ Conversion table management block, 4 to 6... Fist prefetch register, 7... Current instruction register, 8... Program counter register, 9...
- Branch condition judgment block, 10... instruction code bus. Special applicant: NEC Corporation

Claims (1)

[Claims] In a microprogram control device that has a prefetch queue for instruction codes and performs pipeline control, the code portion has a width corresponding to the maximum number of bytes that can be placed in the prefetch queue, and the address portion stores the address of a branch instruction. When a branch instruction appears and the branch is executed, the address part of the address-code conversion table is searched to see if there is an address that matches the address of the branch instruction. If there is no match, the instruction at the branch destination is fetched and set in the prefetch queue as usual.At the same time, one entry of this address-code conversion table is taken. The address field stores the address of this branch instruction, and the code field stores the instruction code of the branch destination to be set in the prefetch queue. If a match is found as a result of the search, the address-code conversion is performed. A microprogram control device characterized in that a code section of a table is taken out and set in the prefetch queue, thereby omitting the fetch time corresponding to the prefetch queue and quickly performing a branch operation.