JPH04253239A - Virtual memory system - Google Patents

Abstract

PURPOSE:To improve the processing performance of a CPU by executing the input/output of segmentation information without performing access to a main memory. CONSTITUTION:The segmentation information is stored in a segment information RAM 17 in the CPU and when updating the segmentation information, the input/output of the segmentation information is executed by performing access to the segment information RAM 17 in place of a main memory 23. Therefore, it is not necessary to perform access to the main memory 23 each time the segmentation information so as to execute the update processing of the segmentation information at high speed. As the result, the processing performance of the CPU can be improved.

Description

[Detailed description of the invention]

0001

[Industrial Application Field] This invention relates to a virtual storage system,
In particular, the present invention relates to a virtual memory system for a computer system that converts a virtual address output from a CPU into a real address in main memory using segmentation information.

0002

2. Description of the Related Art Generally, in virtual memory computer systems, a technique called segmentation is used to convert virtual addresses to real addresses in main memory.

[0003] This segmentation is a method of managing a logically significant program or data by dividing it into variable length fragments called segments, and uses a segment table for the management. The segment table has a correspondence table between the segment number assigned to each segment and the starting address in physical space for that segment, and by referring to this segment table, the real address of segmented data can be determined. can be recognized.

[0004] Information for dividing information in the main memory into specific segment units and converting virtual addresses into real addresses in the main memory is called segmentation information.

Conventionally, this segmentation information has been stored in main memory, and therefore, access to the main memory has been required to update the segmentation information, that is, to change, add, or delete its entries. The conventional system configuration is shown in Figure 2.

In the system shown in FIG. 2, the CPU section is composed of an address calculator 1, registers 2, 4, and 8, and an instruction register 9, and the main memory section is composed of an address converter 3, main memory 6, and registers 5, 7. has been done.

Address calculator 1 calculates a virtual address in main memory 6 according to an instruction code given by instruction register 9. The virtual address calculated by the address calculator 1 is latched by the register 2.

The address converter 3 converts a virtual address into a physical address of the main memory 6 using the segment table described above, and supplies the same to the main memory 6.

The main memory 6 also includes registers 4 and 5.
The write data latched by the main memory 6 is supplied, and the read data from the main memory 6 is latched by the registers 7 and 8.

In this system, when writing segment information to the main memory 6 for example to change the segment table, the address calculator 1 determines a virtual address for writing the segment information according to the instruction code indicated by the instruction register 9. and set it in register 2. Subsequently, the address converter 3
The virtual address is converted into a physical address to generate an address for the main memory 6.

Next, the contents of the segment information are once latched in the register 4 of the CPU section, and then sent to the register 5 of the main storage section and latched therein. In this way, the data is latched in each of the CPU section and main memory section.
This is because the PU section and the main storage section are physically separated, so that normal data transfer must go through the respective registers 4 and 5.

In the main memory 6, the contents of the register 5 are written to the physical address given by the address converter 3.

[0013] Segmentation information is read out in a similar manner. In other words, a physical address is given to the main memory 6, and the data at that address is stored in the main memory 6.
After being read out from the register 7, it is taken into the register 8 of the CPU section.

[0014] Conventionally, segmentation information is stored in the main memory 6 located physically away from the CPU, so data is stored in the CPU and main memory via registers respectively. There was a problem that a lot of time was spent updating the segmentation information. This is a major factor in reducing the operational processing performance of the CPU.

[0015]

[Problem to be Solved by the Invention] Conventionally, segmentation information is stored in the main memory that is physically located away from the CPU, so a large amount of time is spent updating the segmentation information. was there.

The present invention has been made in view of the above points, and provides a virtual memory that can improve the processing performance of a CPU by making it possible to input and output segmentation information without accessing the main memory. The purpose is to provide a method.

[0017]

[Means and Operations for Solving the Problems] The virtual storage system according to the present invention provides a computer system that converts a virtual address output from a CPU into a real address of a main memory using segmentation information.
an internal storage means for storing the segmentation information; a determination means for determining whether input/output processing is to be performed on the segmentation information; and means for accessing the storage means, and the internal storage means is accessed instead of the main memory to input and output segmentation information.

In this virtual storage system, segmentation information is stored in the internal storage means of the CPU, and when updating the segmentation information, the internal storage means is accessed instead of the main memory to store the segmentation information. Input/output is performed. Therefore, it is not necessary to access the main memory each time segmentation information is updated, and the segmentation information update process can be executed at a correspondingly high speed, thereby improving the processing performance of the CPU.

[0019]

Embodiments Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows the configuration of a computer system according to an embodiment of the present invention.

This computer system is a virtual memory system that converts virtual addresses into real addresses in main memory using segmentation information, and the CPU section includes an address calculator 11, a register 12, a judgment section 13,
RAM address generation unit 14, map 15, register 16
, 18, segment information RAM 17, instruction register 19
It is equipped with

The main storage section also includes an address converter 21,
It includes registers 22 and 24 and a main memory 23.

The address arithmetic unit 11 has an instruction register 19
main memory 2 according to the instruction code given by
Calculate the virtual address of 3. This address calculator 11
The virtual address calculated in is latched in the register 12.

[0024] The determining unit 13 is for determining whether input/output processing (creation, updating, reference) of segmentation information is to be performed. is held.

In other words, the determining unit 13 selects the instruction register 19
Based on the instruction code, virtual address, and held segmentation information, it is determined whether the processing target is segmentation information, and based on the determination result, the RAM address generation unit 14 and the segment information RAM
17.

The RAM address generation section 14 refers to the virtual memory address and the map 15 under the control of the determination section 13 to generate read/write addresses for the segment information RAM 17.

The map 15 stores a correspondence table between virtual memory addresses and addresses of the segment information RAM 17. In this case, since the storage space of the segment information RAM 17 is smaller than that of the main memory 23, the contents of the target table of the map 15 are set to be allocated to the segment information RAM 17 with the virtual addresses of the segmentation information compressed. .

Segmentation information is stored in the segment information RAM 17. This segment information RAM
The input/output operations of 17 are controlled by the determination unit 13.

The register 16 contains segment information RAM1.
Data to be written to segment information RAM 17 is latched into register 18, and data read from segment information RAM 17 is latched into register 18.

The address converter 21 converts a virtual address into a physical address of the main memory 23 using a segment table, and supplies it to the main memory 23.

The main memory 23 also has a register 16.
, 22 are supplied, and read data from the main memory 23 is supplied to registers 24, 1.
It is latched at 8.

In this system, when changing segmentation information, for example, instruction register 1
According to the instruction code indicated by 9, the address calculator 11 generates a virtual address for writing segment information and sets it in the register 12.

[0033] Next, the determining unit 13 selects the instruction register 19.
Based on the instruction code, virtual address, and held segmentation information, it is determined whether the processing target is segmentation information, and based on the determination result, the RAM address generation unit 14 and the segment information RAM
17. That is, when the processing target is segmentation information, the RAM address generation unit 14 and the segment information RAM 17 are set to the activated state by the determination unit 13.

In this case, the RAM address generation unit 14 refers to the map 15 according to the virtual address, and writes (or reads) the segment information RAM 17.
An address is generated.

In the segment information RAM 17, the write data, that is, segmentation information latched in the register 16, is written to a given address. Further, the segmentation information read from the segment information RAM 17 is latched into the register 8.

As described above, in the virtual storage system of this embodiment, segmentation information is stored in the segment information RAM 17 in the CPU, and when updating the segmentation information, the main memory 23
Instead, the segment information RAM 17 is accessed to input and output segmentation information.

Therefore, it is no longer necessary to access the main memory 23 every time the segmentation information is updated, and the segmentation information update process can be executed at a correspondingly high speed.

Furthermore, since the segment information RAM 17 only needs to store segmentation information, its storage space is much smaller than that of the main memory 23. Therefore, the segment information RAM 17 can be accessed faster than when accessing the main memory 23, which has a large storage space.

In this way, in this embodiment, it is possible to input and output segmentation information without accessing the main memory, thereby speeding up the input and output of segmentation information, and as a result, improving the processing performance of the CPU. has been realized.

[0040]

[Effects of the Invention] As detailed above, according to the present invention,
It becomes possible to input and output segmentation information without accessing the main memory, and it becomes possible to improve the processing performance of the CPU.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a system configuration according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a conventional system configuration.

[Explanation of symbols]

11... Address calculator, 12, 16, 18... Register,
13... Judgment unit, 14... RAM address generation unit, 15... Map, 17... Segment information RAM, 23... Main memory.

Claims (1)

[Claims] 1. In a computer system that converts a virtual address output from a CPU into a real address in a main memory using segmentation information, the CPU includes an internal storage means in which the segmentation information is stored, and a computer system that stores the segmentation information. The apparatus includes a determining means for determining whether input/output processing is being performed, and means for accessing the internal storage means when the determining means determines whether input/output processing is to be performed on the segmentation information. A virtual storage method characterized by inputting and outputting segmentation information by accessing storage means.