JPH0373031A - Memory access control system - Google Patents

Abstract

PURPOSE:To execute an instruction for directly accessing a guest space, which is issued by a host, at high speed by executing access control to a memory address, to which the guest is correspondent, according to selected key information and address mode information when the guest access instruction is executed. CONSTITUTION:While the guest is traveled, a selecting means 8 selects the key information in the PSW of a PSW register 1 and the address mode information in the modified PSW of a real PSW register 3. Accordingly, an effective address adder 10 can calculate the memory address for accessing the guest space under traveling. At such a time, a storing means 7 is set to an enable state according to the travel information of the guest and stores the same key information and address mode information as the key information and address mode information to be stored in an operational AM/KEY register 9 while updating the information. Thus, the instruction to directly access the guest space to be issued by the host can be executed at high speed.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory access control method in a virtual computer system, the purpose of this invention is to enable high-speed execution of instructions issued by a host to directly access a guest space, is set to the enabled state and the PSW
It updates and stores the key information inside and the address mode information in the modified PSW, and when control is transferred to the host via firmware, it is set to a disabled state and retains that information. and a PSW modified with the key information in the P'SW set corresponding to the host when a guest access command for direct access from the host to the guest is issued.
a selection means for selecting key information and address mode information of the storage means in place of the address mode information in the storage means; Configure to perform access control.

[Industrial Application Field] The present invention relates to a memory access control method in a virtual computer system, and particularly to a memory access control method that enables high-speed execution of instructions issued by a host to directly access a guest space. It is.

[Conventional technology]

In a virtual computer system in which a plurality of virtual needles Xm are operated under one real computer, an instruction for directly accessing the guest space from the host is defined. This instruction is used when the host virtually executes the instructions of the guest that ran just before using software simulation.
This is an instruction used to transfer data between guests.

Conventionally, instructions for transferring data between a host and a guest have been configured to be executed by firmware.

Next, according to FIG. 3, the prior art will be explained in detail.In the diagram, A shows the host, guest, and firmware areas on the memory, and B shows the management of guest resources taken on the host area. It shows the data (PSW/control register information, etc. and the upper and lower limit addresses of the guest space), and C shows the host resource management data (PSW/control register information, etc. and the upper and lower limit addresses of the host space) stored in the firmware area. (lower limit address) and guest resource management data (PSW/control register information, etc. and upper and lower limit addresses of the guest space). In the figure, the upper limit address of the guest space is described as GABR information, the lower limit address of the guest space as GALR information, the upper limit address of the host space as HABR information, and the lower limit address of the host space as HALR information.

First, when a boot command is issued from the host to the guest 1, the host notifies the firmware of the boot command via a program interrupt. Upon receiving this notification, the firmware saves the PSW/control register information, etc. of the host that was running to the corresponding area in the firmware. Next, the guest resource of the guest to be started is transferred from the host area. It is read out and stored in the corresponding area in the firmware, and as shown in Figure 4,
The PSW, GABR information, and GALR information of the guest ga 1 read from the host area are set in the real PSW register 3, guest space upper limit address register 42, and guest space lower limit address register 43 on the actual hardware, respectively, and the guest ga 1 Start. In addition, in Fig. 4, 40 is H
A host space upper limit address register 41 stores ABR information, and a host space lower limit address register 41 stores HALR information.

After that, when guest #1 issues a command to perform software simulation on the host, the firmware saves the PSW/control register information, etc. of guest #1 that was running in the corresponding area in the firmware, and then The PSW of the host resource in the firmware area is set in the actual PSW register 3, and the host is activated.

When executing a software simulation in this way, if the host issues a guest access command to directly access the guest space, the hardware on the actual computer does not even have the host's PSWL, so the guest 1's address mode information (information about what address format the virtual machine has) and key information (control bits provided for each page to manage main memory), the host will be unable to do so from now on. , the program interrupt was notified to the firmware, and the firmware was processed to execute this data transfer instruction between the host and the guest. In other words, the firmware is installed in the guest file 1 in the firmware area.
According to the address mode information and key information of the guest
By obtaining the address to access the guest space of the host, data transfer between the host and the guest was performed.

[Problem to be solved by the invention]

However, in such conventional technology, since the firmware executes instructions issued by the host to directly access the guest space, the software simulation executed by the host requires a large amount of processing time. There was a problem with it being put away.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a new memory access control method that enables high-speed execution of instructions issued by a host to directly access a guest space. It is.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, numeral is the PSW register, and P in the space in which it is running.
2 is an extension control register that stores the SW,
PSW register 1 stores modification data for modifying the PSW, 3 is a real PSW register that stores PSW modified by the modification data of extended control register 2, and 4 is a state control section. 5 outputs "1" while the host and guest are running, and outputs 0" while the firmware is running; 5 is a microprogram that executes command control; 6 is an AND game.
7, which outputs 1'' when a guest access command is sent from the microprogram 5 while the host is running; 7 is a storage means that is set to an enabled state while the guest is running; The key information in the PSW of PSW register 1 and the address mode information in the modified PSW of real PSW register 3 are sequentially updated and stored, and are disabled when control is transferred to the host via firmware. 8 is a selection means that processes to hold the key information and address mode information at the time when the AND gate 6 outputs "O". When the key information in the PSW of the PSW register 1 and the address mode information in the modified PSW of the real PSW register 3 are selected and 1' is output from the AND gate 6, the key information held in the storage means 7 is selected. information and address mode information selection, 9 is operation AM/K
EY register, which stores the key information and address mode information selected and output by the selection means 8; 10 is an effective address adder, which inputs the base address and the address mode information according to the specification of the address mode information of the operation AM/KEY register 9; A memory address is calculated from an index and displacement.

[Effect]

In the present invention, while the guest is running, the AND gate 6 is
0'', the selection means 8 selects the key information in the PSW of the PSW register 1 and the address mode information in the modified 13w of the real PSW register 3 to select the operation AM/KEY register. 9, the key information of the current PSW of the running guest and the address mode information being used are input.As a result,
The effective address adder 10 can calculate a memory address for accessing the running guest space. At this time, the storage means 7 is set to an enabled state according to the traveling information of the guest, and updates and stores the same key information and address mode information as the key information and address mode information stored in the operation AM/KEY register 9. We will process it accordingly.

A running guest sends software assistance to the host.
When a command is issued to request execution of replication, control is transferred to the host via firmware. At this time, the storage means 7 processes to hold the key information and address mode information at the time when control is transferred to the firmware by being set to the disabled state.

Then, when the host starts executing the software migration and issues a guest access command to directly access the guest space because it requires data in the guest space, it receives an output of 1'' from the microprogram 5. The AND gate 6 outputs "1", and the selection means 8
Upon receiving the output of the AND gate 6, the key information and address mode information held in the storage means 7 are selected,
Operation: Process to input to AM/KEY register 9. In this way, the address mode information and key information of the guest that has issued the software registration ID are set in the operation AM/KEY register 9, so that the valid address adder 10 is set to The memory address for accessing the guest space can now be calculated, and the data in the guest space will be read out according to this calculation process.

Subsequently, when the host executes the software simulation according to the read guest space data, the selection means 8 selects O'' from the microprogram 5.
By receiving the output and selecting the key information in the PSW of PSW register 1 and the address mode information in the modified PSW of real PSW register 3, the running host The key information of the current PSW and the address mode information being used are input.

As described above, according to the present invention, it becomes possible to execute instructions issued by the host to directly access the guest space without going through firmware, so data transfer between the host and the guest is significantly faster than in the past. will be able to execute.

〔Example〕

Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 illustrates an embodiment of the present invention. In the figure, the same parts as those explained in FIGS. 1 and 4 are indicated by the same symbols. 2a is a first extension control register, which corresponds to extension control register 2 in FIG. 1;
8 is an AND gate with negation, which corresponds to the AND gate 6 in FIG. 1; 7a is a guest access control register, which corresponds to the storage means 7 in FIG. 1;
a is the first gate constituting the selection means 8, and when the negative output of the AND gate 6a with negation is "1", the PS
The key information of the W register 1 and the address mode information of the real PSW register 3 are input to the operation AM/KEY register 9. 8b is a second gate constituting the selection means 8, and is an AND gate with negation) 6a. 11 is a first selection circuit that inputs the key information and address mode information of the guest access control register 7a to the operation AM/KEY register 9 when the positive output is "1"; 12 is a second selection circuit that stores the modified PSW in the real PSW register 3 by selecting the extended control register 2a of the circuit;
The key information of PSW register l and the address mode information of real PSW register 3 are transferred to guest access control register 7a.
or input data from the write bus to the guest access control register 7a; 13 is the second
14 is an extended control register that manages the host bit that is set to 1" when the host is running. 14 is a buffer with negation, which uses the value of the host bit of the second extended control register 13 as an AND game with negation) What to enter in 6a,
Reference numeral 15 denotes a first AND gate, which calculates and outputs the logical product of the negative output of the buffer with negation 14 and the output of the state control unit 4; and 16, a first OR gate; When 1'' is output from the AND gate 15 of 1" or when there is a write instruction, the guest access control register 7a is set to an enabled state by sending a clock to the guest access control register 7a. 17 is a second 18 is a second OR gate that calculates and outputs the logical product of the NOT output of the NOT buffer 14 and the output of the state control unit 4. A gate 19 calculates the logical sum of the positive output and the output of the second AND gate 17 and outputs the result, and when there is a write instruction, the data on the write bus is sent to the first extended control register 2a. 20 is a gate that inputs the data of the write bus to the PSW register 1 when there is a write instruction; 21 is a gate that receives "l" from the first AND gate 15; A gate 22 inputs the key information of the PSW register 1 and the address mode information of the real PSW register 3 to the second selection circuit 12 when they are output, and when a write instruction is issued, the key information of the PSW register 1 and the address mode information of the real PSW register 3 are input to the second selection circuit 12. 30 is a memory access unit that controls access to a memory (not shown).This memory access unit 30 inputs data to the second selection circuit 12. Check the memory access processing according to the information, or add the GABR information held by the guest space upper limit address register 42 to the memory address output from the effective address adder 10 while the guest is running to check the actual memory address. In addition to obtaining the address, address over-check processing and the like are executed in accordance with the GALR information held in the guest space lower limit address register 43.

Next, the operation processing of the embodiment of the present invention configured as described above will be explained.

While the guest is running, the negation output of the negation buffer 14 outputs ``1'' in response to the host bit 0°'' of the second extended control register 13, and the state control unit 4 outputs ``1''.
outputs °1”, the first AND gate 15
outputs "1", and as a result, the guest access control register 7a stores the key information of PSW register 1 and the actual PSW.
It operates so that the address mode information in the register 3 is sequentially updated and stored. During this operation, the negative output of the AND gate 6a outputs "1" in response to the positive output of the negative buffer 14, and as a result, the first gate 8a opens and the operation AM starts. /KE
The key information of psw register 1 and the actual PSW are stored in Y register 9.
As the address mode information of Regisc 3 is input, the negative output of A and the positive output of ND Age-6a are input.
The second OR gate 18 receives the "1" output from the second AND gate 17 and operates to close the second gate 8b. An access instruction signal is sent.In this way, the current PS of the guest is stored in the operation AM/KEY register 9.
Since the key information of W and the address mode information being used are set, running in the guest space will be executed.

When a running guest issues a command to the host to request execution of a software simulation, control is transferred to the host via firmware. When passing through this firmware, the state control unit 4
is outputting “0°°, so the first AND gate 1
5 outputs 0'' and 1. When the host starts running again, the negative output of the negative buffer 14 outputs °゛O'' in response to the host bit being 1, and the first AND gate 15 operates to output “O”. Therefore, when a command is issued to the host to request execution of software migration, the guest access control register 7
a will operate to hold the key information and address mode information, which is the last guest state of the guest that has been operating up to that point.

When the host starts executing software simulation, the PSW of the host is stored in the PSW register 1, and the modified PSW of the host is stored in the real PSW register 3. Then, when the host issues a guest access command to directly access the guest space because it needs data in the guest space to execute a software simulation, it receives the "1°" output from the microprogram 5 and negates it. AND game)
When the negative output of 6a outputs 0'', the first gate 8a closes, and when the positive output of the AND gate 6a with negation outputs uln, the second gate 8b opens. Due to the operation, the key information and address mode information held in the guest access control register 7a are input to the operation AM/KEY register 9, and the effective address adder 10 inputs the space of the guest that was running immediately before. You will be able to calculate the memory address to access.

At this time, the second OR gate 18 receives the positive output "1" from the AND gate 6a and outputs "1" representing an instruction to access the guest space to the memory access unit 30. Therefore, the memory access unit 30 performs additional processing using GABR information and GAL according to the input guest space memory address and key information.
Address overcheck processing is executed using the R information to execute data continuation processing in the guest space.

Subsequently, when the host executes a software simulation according to the read guest space data, the first gate 8a opens in response to the "O" output from the microprogram 5, and the second gate 8b opens. Operates to close.

Through this operation, the key information of the current PSW of the running host and the address mode information being used are input to the operation AM/KEY register 9. At this time, the second AND gate 17
In response to the negative output of 0'' output, it outputs "O", and the positive output of (AND game with negation) 6a is the microprogram 5.
Since it receives the “0′” output and outputs “0”, the second
The OR gate 18 outputs 0'' representing an instruction to access the host space.As a result, the host accesses data in the host space and executes software simulation processing.

In this way, the guest access control register 7a newly provided in the present invention operates to hold the key information and address mode information of the guest that was running immediately before, but apart from this, In order to facilitate data processing, the configuration is such that arbitrary key information and address information can be set from the write bus by opening the gate 22 in accordance with a write instruction.

FIG. 2 is an embodiment of the present invention, and FIGS. 3 and 4 are explanatory diagrams for explaining the prior art.

In the figure, 1 is the PSW register, 2 is the expansion control register, and 3 is the PSW register.
4 is a real PSW register, 4 is a state control section, 5 is a microprogram, 6 is an AND gate, 7 is a storage means, 8 is a selection means, 9 is an operation AM/KEY register, and 10 is an effective address adder.

〔Effect of the invention〕

As explained above, according to the present invention, instructions issued by the host to directly access the guest space can be executed without going through firmware. This allows data transfer to be performed.

Claims (1)

[Claims] In a virtual computer system that has three states: host, guest, and firmware, and in which multiple virtual computers operate under one real computer system, an enabled state is provided while the guest is running. set, PSW
The key information inside and the address mode information in the modified PSW are stored while being updated sequentially, and when control is transferred to the host via firmware, it is set to the disable state, and the disable state is set to the disable state. storage means (7) for processing to hold the key information and address mode information at the time when the host is set to the host; Selection means for processing to select the key information and address mode information of the storage means in place of the key information in the PSW and the address mode information in the modified PSW (
8), and is configured to control access to the corresponding memory address of the guest according to the key information and address mode information selected by the selection means (8). control method.