JPS60215250A - Data processor - Google Patents

Abstract

PURPOSE:To improve the data processing performance by using a means to decides whether an interruption factor if produced is equal to an interruption to be processed by a VMCP or an interruption to be processed by an operating system of a virtual computer. CONSTITUTION:In case an instruction which is interpreted by a processing part 10 is equal to a state control instruction, the information on designation of an action to be executed and the desired data are delivered to a data line 32. When the value of an FF30 is set at ''0'', i.e., the relevant computer is not set under a virtual computer mode, the data on the line 32 is applied to a state control part 11 of a CPU via an AND gate 33. Then access is given to a state register part 12 from the part 11 to execute a desired action. While the data on the line 32 is given to a state control part 21 of a virtual computer via an AND gate 34 in case the FF30 is set at ''1'', i.e., the relevant computer is set under a virtual computer mode. Then access is given to a state register part 22 of the virtual computer from the part 21, and a desired action is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device that implements a virtual computer system.

[Background of the invention]

The virtual computer method uses real computers for time division, and sets virtual hardware information (control registers, calculation registers, psw, etc.) in each time slot, so that one real computer can handle each time slot. Each computer operates as if it were a separate computer. Therefore, a single computer can apparently run multiple different operating systems at the same time.

By the way, software in a virtual computer system generally has a three-layer structure of levels 0° and 1.2, as described below. Level O is VMCP (Virtua
l Machine ContrOI Program
), which is the operating system of the real computer and performs control to realize the virtual computer. Level l is a virtual needle computer operating system that is executed in each time slot. Hardware information 1 handled by a level 1 operating system, for example, PSW (program state word), is not an actual PSW of a computer, but a virtual PSW held as data in a main storage device, for example. therefore,
An instruction issued by a level 1 operating system to rewrite the PSW is reinterpreted by the level 0 VMCP and results in rewriting the virtual PSW in main storage rather than the actual PSW. Level 2 is a user program on a virtual machine and is processed by a level 1 operating system.

Let us consider the processing when one interrupt occurs in such a virtual computer system.

FIG. 2 shows an example of transfer of control rights in a program when the interrupt occurs. For example, if a program interrupt occurs during the execution of a level 2 user program, the virtual computer that is executing it will have to manage the user program as shown in Figure 2 (a'). It is desirable to immediately interrupt the level I operating system that is currently running the process. However, since interrupts are recognized by the hardware of the real computer, in reality, as shown in Figure 2 (b), they are first processed by the level 0 VMCP, and then the operating system of the level 1 virtual machine The method used is to return the processing to in this case,
The issues that must be handled by the VMCP interrupt handling routine are: 1. Should this interrupt be handled by VMCP, or should it be returned to the operating system of the virtual machine that generated the interrupt? (It belongs to the former, and calculation overflow interrupts, etc. belong to the latter).

2. If you want to restore it, which virtual computer should you restore it to? 3. Will that virtual computer accept this interrupt? 4. If it accepts it, should you store the old PSW, retrieve the new PSW, etc.

and so on.

As mentioned above, when an interrupt occurs in the virtual y machine, it is always processed by VMCP, so
- It has the disadvantage that a very large amount of overhead time is required for interrupt processing.

For example, for interrupts that are masked off and cannot be accepted in a virtual computer, if the interrupt is performed on a real computer rather than on a virtual computer, the overhead time will be zero or very short after the occurrence of one interrupt factor. After that, the process returns to the original process, but when it is performed on a virtual machine, the processes 1 to 3 above are always performed regardless of whether the mask is on or off, so the original process cannot be resumed. It will take a lot of time to recover.

[Purpose of the invention]

The present invention aims to improve the drawbacks of the virtual computer system described above.

[Summary of the invention]

For example, when an interrupt factor occurs in a virtual machine, the present invention determines whether it is an interrupt that should be handled by the VMCP or an interrupt that should be handled by the operating system of the virtual machine.

In the latter case, without entering VMCP processing,
Immediately refers to the mask of the relevant virtual machine to determine whether or not to accept interrupts, and if the mask is on and interrupts can be accepted, interrupts directly to the operating system of the relevant virtual machine, and if the mask is turned off. If the interrupt cannot be accepted, the original processing is resumed, thereby minimizing the overhead time related to interrupt processing and improving the performance of the virtual computer system.

[Embodiments of the invention]

Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram showing an example of the configuration of a central processing unit (CPU) in a computer system in which the present invention is implemented. In the figure, IO is a processing unit that performs necessary instruction processing and arithmetic processing in the CPU, and 11 changes the state of the CPU such as interrupts and control instructions. 2 is a state control section that operates when necessary, and 12 is a state register section that stores CPU state information such as a program status word (PSW) and a control register. The above three parts are also provided in conventional computers; on the other hand, in Fig. 1, the parts other than the above three parts are newly added by implementing the present invention. . That is, in FIG. 2, 21 is a state control unit that controls the state of CPtJ as a virtual machine;
Reference numeral 22 denotes a status register unit that stores status information of the CPU of the virtual machine. Further, 30 is a flip-flop indicating that this CPU is currently operating in virtual machine mode, and 33 and 34 are AND gates.

The CPU state control section 11 and the virtual machine state control section 21 may be a logic circuit configured by a combination of logic elements, or may include a storage device that stores a microprogram. When the state control section 11 or 21 includes a microprogram storage device, these may be all physically integrated storage devices including the microprogram storage device of the processing section. . Further, the virtual machine mode designation flip-flop 30 may be one bit in a control register (ie, included in the status register section 12) as in a conventional CPU that realizes a virtual machine. This flip-flop 30 is set to "1" by the VMCP when the virtual machine starts operating.
It is set to 0'' when the operation as a virtual machine is interrupted and the VMCP is interrupted. This control is performed by the state control unit 11 via the signal line 36.

In the configuration example shown in FIG. 1, the operation when a virtual machine is realized will be described below.

First, at the beginning of a time slot in which processing is assigned to each virtual machine, the state of the virtual machine is set by the level 1 program (the operating system of the virtual machine). In this case, in the implementation of a virtual machine according to the prior art, the state control instructions from the level 1 program are not executed as they are as instructions.

Each time, the VMCP was interrupted and executed in a simulated manner by the VMCP program. For example, at level 1, PS
When an instruction to set data in W is issued, the instruction is not executed but interrupts the VMCP, and the VMCP stores the PSW data in a predetermined area in the main memory, for example. In contrast, according to the present invention, level 1 state control instructions can be directly executed without interrupting the VMCP.

That is, in FIG. 1, when the command newly interpreted to be executed by the processing unit 10 is a state control command, information specifying the operation to be executed and necessary data are output to the data line 32. Here, when the value of the flip-flop 30 is 0'', that is, when this computer is not in virtual computer mode, the data on the data line 32 is given to the state control unit 11 of the CPU via the AND gate 33. From there, the status register section 12 is accessed to perform the necessary operations.The value of the flip-flop 30 is
11, that is, when this computer is in the virtual machine mode, the data on the data line 32 is given to the state control section 21 of the virtual machine via the AND gate 34, and from there the state register section 22 of the virtual machine is sent. access and perform necessary operations.

As described above, each virtual machine stores the state information of its own computer in the state register section 2 without the intervention of the VMCP.
This means that it can be set to 2. This itself means that the processing speed has been increased and the program (VMCP) has been simplified.

Once the state of the virtual machine is set, the level 2 program is processed under the operating system of the level 1 virtual machine. The most important feature of the present invention is that the CP running in virtual machine mode
This is how to handle tJ interrupts.

In FIG. 1, when an interrupt request is generated in a program being processed by the processing section 10, an interrupt request signal and related necessary data are output to the data line 32. Note that the data line 32 is composed of a plurality of signal lines, and the signal line used in the case of executing the state control instruction mentioned above and the signal line used in the case of an interrupt request are physically different. They do not necessarily match. The interrupt request signal and data output to the data line 32 are sent to the state control unit 21 of the virtual machine when running in the virtual machine mode, according to the value indicated by the flip-flop 30, as in the case of the state control command. If not, the state control unit 11 of the CPU obtains the result.

When the interrupt request signal and data are given to the state control unit 21 of the virtual machine, the state control unit 21 performs the following control. First, examine the contents of this interrupt request,
Is this what should interrupt level O (VMCP')?
Determine whether the level (virtual machine operating system) should be interrupted. Interrupt to level 0? If it is determined that the interrupt request signal and related data are appropriate, the interrupt request signal and related data are sent to the state control section 11 of the CPU via the data line 35, and subsequent processing is transferred to the control section 11. On the other hand, if it is determined that the 1 interrupt request should be interrupted to level 1, the state control unit 21 performs the necessary interrupt control while accessing the virtual machine state information set in the state register unit 22. conduct. The main purpose is to refer to the interrupt mask information of this virtual machine and decide whether or not to accept the interrupt request, and if it is accepted, to exchange the PSW. When this interrupt control is finished, the state control unit 2
1 notifies the processing section 10 of the end of interrupt control via the data line 23, and the processing section 10 executes the processing after the interrupt.

In the explanation so far, as an example of an interrupt that occurs while a program is running on a virtual machine, we have considered an interrupt from level 2 to level 0 or level 1, but of course there are also interrupts from level l to level O or level 1. 1 itself may be interrupted. Obviously, the present invention can be applied to these cases as well, with no change from the case from level 2 onwards.

Also, as for the operation in the embodiment shown in FIG.

Case of state control instruction for setting the state of virtual machine and 1
Although the case where an interrupt occurs has been described, the same argument holds true for all other cases in which a state control instruction for writing/reading to/from the state register section is generated.

〔Effect of the invention〕

As described above, according to the present invention, when an interrupt occurs or a state control instruction is issued while the CPU is executing a program as a virtual machine, the j'cPU immediately processes this without intervention from the VMCP. 1: I can do it.

This dramatically increases the processing performance of the CPU'U as a virtual computer, and therefore the effects of the present invention are significant. Furthermore, according to the present invention, a considerable part of the functions of the VMCP can be deleted, which greatly contributes to reducing the program capacity and the number of man-hours for creating the program, and the effectiveness of the present invention is clear from this aspect as well. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device showing one embodiment of the present invention. Figure 2 is a conceptual diagram showing an example of transfer of control rights in a program when an interrupt occurs in a data processing device operating as a virtual machine. shows the case according to the prior art. 10... Processing unit, 11... CPU state control unit, 1
2...CPU status register unit, 21...Virtual machine status control unit, 22...Virtual machine status register unit, 30...Virtual machine mode specification flip-flop.

Claims (1)

[Claims] (1) In a data processing device that uses a virtual computer method,
an identification means for indicating that the data processing device is operating as a virtual machine; a state register section for storing state information of the virtual machine; when the identification means indicates that the data processing apparatus is operating as a virtual machine; a state control unit that controls the state of the virtual machine by accessing the state register unit;
The state control unit determines whether or not the state control unit should process a state control command issued or an interrupt request that occurs when the identification means instructs an operation as a virtual machine. A data processing device characterized in that, when it is determined that the issued state control command or the generated interrupt request should be processed, the issued state control command or the generated interrupt request is processed without intervention of a control program as a virtual machine.