JPS6212555B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a data processing device that implements a virtual computer system.

[Background of the invention]

The virtual computer method uses a real computer for time division, and sets virtual hardware information (control registers, calculation registers, PSW, etc.) for each time slot, so that one real computer can control each time slot. Each computer operates as if it were a separate computer. Therefore, a single computer can apparently run multiple different operating systems at the same time.

By the way, software in a virtual computer system is generally level 0, as described below.
It has a three-layer structure of 1 and 2. Level 0 is
It is called VMCP (Virtual Machine Control Program), and is an operating system for real computers that performs control to realize virtual computers. Level 1 is the virtual machine operating system running in each time slot. Hardware information handled by a level 1 operating system, e.g. PSW
(Program state word) is not the actual PSW of the computer, but a virtual PSW held as data in the main memory, for example. Therefore, an instruction to rewrite a PSW issued by a level 1 operating system is a level 0 VMCP.
The virtual PSW in main storage is rewritten instead of the actual PSW. Level 2 is a user program on a virtual machine and is processed by a level 1 operating system.

Let us consider the processing when an interrupt occurs in such a virtual computer system.
FIG. 2 shows the sequence of movement of control rights in the program when the interrupt occurs. For example, if a program interrupt occurs during the execution of a level 2 user program, the virtual machine that is executing it will manage the user program as shown in Figure 2a. However, it is desirable to immediately interrupt the level 1 operating system and perform processing. However, since interrupts are recognized by the hardware by the real computer, in reality they are first processed by the level 0 VMCP as shown in Figure 2b, and then processed by the level 1 virtual computer. The method used is to return the processing to the operating system. In this case, the issues that must be handled by the VMCP interrupt handling routine are: 1. Should this interrupt be handled by VMCP, or should it be returned to the operating system of the virtual machine that generated the interrupt (for example, a machine failure interrupt)? (belongs to the former, and calculation overflow interrupts, etc. belong to the latter), 2. Which virtual computer should I restore it to? 3. Will that virtual computer accept this interrupt? 4. If so, should I store the old PSW and store the new PSW? There are things like taking out, etc.

As described above, when an interrupt occurs in a virtual machine, it is always processed by VMCP, which has the disadvantage that a very large amount of overhead time is required for one interrupt processing. For example, for interrupts that are masked off and cannot be accepted in a virtual computer, if the interrupt is performed on a real computer rather than on a virtual computer, the overhead time will be zero or very short after the occurrence of the interrupt factor. After that, the process returns to the original process, but when it is performed on a virtual machine, the processes 1 to 3 above are always performed regardless of whether the mask is on or off, so the original process cannot be resumed. It will take a lot of time to recover.

[Purpose of the invention]

The present invention aims to improve the drawbacks of the virtual computer system described above.

[Summary of the invention]

For example, when an interrupt factor occurs in a virtual machine, the present invention determines whether it is an interrupt that should be handled by VMCP or an interrupt that should be handled by the operating system of the virtual machine,
If the latter is the case, without entering VMCP processing, immediately refer to the mask of the virtual machine to determine whether interrupts can be accepted, and if the mask is on and interrupts can be accepted, directly interrupt the virtual machine. If the mask is turned off and cannot be accepted, interrupt the operating system of
This minimizes the overhead time related to interrupt processing, thereby improving the performance of the virtual computer system.

[Embodiments of the invention]

Hereinafter, the content of the present invention will be explained in detail with reference to Examples.

FIG. 1 is a block diagram showing an example of the configuration of a central processing unit (CPU) in a computer system in which the present invention is implemented. In the diagram, 10 is the CPU
11 is a state control unit that operates when it is necessary to change the state of the CPU such as an interrupt or a control instruction, and 12 is a program status word (PSW). This is a status register section that stores CPU status information such as CPU and control registers. The above three parts are also provided in conventional computers; on the other hand, in Fig. 1, the parts other than the above three parts are newly added by implementing the present invention. It is. That is, the second
In the figure, 21 is a state control section that controls the state of the CPU as a virtual machine, and 22 is a state register section that stores state information of the CPU of the virtual machine. Further, 30 is a flip-flop indicating that this CPU is currently operating in virtual machine mode, and 33 and 34 are AND gates.

The CPU state control unit 11 and the virtual machine state control unit 21 may be a logic circuit configured by a combination of logic elements, or may include a storage device that stores a microprogram. These state control units 11 or 21
contains a microprogram storage device,
Physically, these may be all integrated storage devices including the microprogram storage device of the processing section. In addition, the virtual machine mode designation flip-flop 30 is configured to use one bit in the control register (i.e., the one included in the status register section 12) as in a conventional CPU that realizes a virtual machine.
It may be. This flip-flop 30
It is set to "1" by VMCP when the virtual machine starts operating, and is set to "0" when the virtual machine operation is interrupted and VMCP interrupts. This control is performed by the state control section 11 via the signal line 36.

In the configuration example shown in FIG. 1, the operation when a virtual machine is realized will be described below.
First, at the beginning of a time slot in which processing is assigned to each virtual machine, the state of the virtual machine is set by the level 1 program (the operating system of the virtual machine). In this case, in the realization of a virtual machine according to the conventional technology, the state control instructions by the level 1 program are not executed as instructions as they are;
Each time, it interrupted VMCP and was executed in a simulated manner by the VMCP program. For example, when an instruction to set data in PSW is issued at level 1, the instruction is not executed but interrupts VMCP, and VMCP stores the PSW data in a predetermined area in the main storage, for example. In contrast, according to the present invention, level 1 state control instructions can be executed directly without interrupting VMCP.

That is, in FIG. 1, when the command newly interpreted to be executed by the processing unit 10 is a state control command, information specifying the operation to be executed and necessary data are output to the data line 32. here,
When the value of flip-flop 30 is "0",
That is, when this computer is not in the virtual machine mode, the data on the data line 32 is applied to the CPU state control section 11 via the AND gate 33, and the state register section 12 is accessed from there to perform necessary operations. Further, when the value of the flip-flop 30 is "1", that is, when this computer is in the virtual machine mode, the data on the data line 32 is given to the state control unit 21 of the virtual machine via the AND gate 34, and from there. Necessary operations are performed by accessing the state register section 22 of the virtual machine.

In the manner described above, each virtual machine is able to set its own computer status information in the status register section 22 without intervention from the VMCP. This itself means that processing speed has been increased and the program (VMCP) has been simplified.

When the state of the virtual machine is set, level 1
The level 2 program is processed under the operating system of the virtual machine. The most distinctive feature of the present invention lies in the way interrupts are handled by the CPU running in virtual machine mode.

In FIG. 1, when an interrupt request is generated in a program being processed by the processing section 10, an interrupt request signal and related necessary data are output to the data line 32. Note that the data line 32
consists of multiple signal lines, and the signal lines used for executing the state control instructions mentioned above and the signal lines used for interrupt requests are not necessarily the same physically. do not have. As in the case of state control instructions, the interrupt request signal and data output to the data line 32 are sent to the state control unit of the virtual machine when running in the virtual machine mode, according to the value indicated by the flip-flop 30.
1, otherwise the CPU state control unit 1
1 is given.

When the interrupt request signal and data are given to the state control unit 21 of the virtual machine, the state control unit 21 performs the following control. First, carefully examine the contents of this interrupt request and confirm that it is level 0 (VMCP).
Determine whether to interrupt the level (virtual machine operating system). If it is determined that the interrupt should go to level 0, this interrupt request signal and related data are sent to the CPU state control section 11 via the data line 35, and the subsequent processing is carried out by the control section 11.
Transfer to. On the other hand, if it is determined that the interrupt request should be interrupted to level 1, the state control unit 21 performs necessary interrupt control while accessing the virtual machine state information set in the state register unit 22. . The main thing is to refer to the interrupt mask information of this virtual machine and decide whether or not to accept the interrupt request.
If accepted, the PSW will be replaced. When this interrupt control is completed, the state control unit 21 sends the data to the processing unit 10 via the data line 23.
The processing unit 10 notifies the user of the end of the interrupt control, and executes the processing after the interrupt.

In addition, in the explanation so far, as an example of an interrupt that occurs while a program is running on a virtual machine, we have considered an interrupt from level 2 to level 0 or level 1. 1 itself may be interrupted. Obviously, the present invention is applicable to these cases as well, with no change from the case from level 2 onwards.

Furthermore, the operation in the embodiment shown in FIG. 1 is as follows:
We have described the case of a state control instruction for setting the state of a virtual machine and the case of an interrupt, but in addition to that, we have also described all cases in which a state control instruction for writing/reading to the state register section is generated. , a similar argument holds.

[Effects of the Invention] As described above, according to the present invention, if an interrupt occurs or a state control instruction is issued while the CPU is executing a program as a virtual machine, the CPU can handle this without the intervention of the VMCP. Can be processed immediately. This dramatically increases the processing performance of the CPU as a virtual machine.
Therefore, the effects of the present invention are significant. Furthermore, the present invention makes it possible to delete a considerable part of the functions of VMCP, which greatly contributes to reducing program capacity and creation man-hours, and the effectiveness of the present invention is clear from this aspect as well. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a data processing device showing one embodiment of the present invention. FIG. 2 is a conceptual diagram showing an example of transfer of control rights in a program when an interrupt occurs in a data processing device operating as a virtual machine. This shows the case. 10...processing section, 11...CPU state control section, 12...CPU state register section, 21...
Virtual machine state control unit, 22...virtual machine state register unit, 30...virtual machine mode specification flip-flop.

Claims (1)

[Claims] 1. In a data processing device that employs a virtual machine method, an identification means for indicating that the data processing device is operating as a virtual computer, a status register section for storing state information of the virtual machine, and an identification means for indicating that the data processing device is operating as a virtual computer; When indicating that it is working,
The state control unit includes a state control unit that controls the state of the virtual machine by accessing the state register unit, and the state control unit receives a state control command issued when the identification means instructs operation as a virtual machine. Alternatively, it is determined whether the generated interrupt request should be processed by the state control unit, and if it is determined that the generated interrupt request should be processed, the issued state control instruction or the generated interrupt request is processed by the control program as a virtual machine. A data processing device characterized in that it performs processing without causing any interference.