JPS60105052A - Virtual computer system - Google Patents

Abstract

PURPOSE:To improve the performance of a virtual computer system by executing directly a privilege instruction for control of the working state control register of an operating system, and decreasing the simulation overheads of the control program of a virtual computer. CONSTITUTION:When a privilege instruction is outputted from a virtual computer VM3, a real computer 1 decides the presence or absence of a direct execution mode by an instruction 10. In a direct execution mode, the privilege instruction is directly executed by a microprogram 12 for real computer. In other modes, the privilege instruction is processed by a microprogram 13 for firmware assist VMA and sent to the VM3. When the program 12 is used for processing, the need for interruption is decided by a deciding hardware 14 for a virtual computer control program VMCP. The decision processing is carried out at a high speed. When the conditions are satisfied, an interruption (21) is fed to the VMCP. While the control is immediately transferred to the VM3 in case the conditions are not satisfied.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a virtual computer system, and particularly to a virtual computer system that can reduce the overhead of privileged instruction simulation.

[Background of the Invention] In recent years, as the applications of digital computers have expanded, addressing methods (
virtual memory method) is used, and furthermore, using this method, 1
A system (virtual computer system) is used in which one real computer can be used by multiple operating systems (hereinafter referred to as O8) at the same time.

A virtual subtraction system is a computer system that controls the resources of one real computer (processing unit, real storage device, channels, input/output devices, etc.) as if there were multiple computers. Yes, there is a virtual computer system (hereinafter referred to as V
In MS), all resources including main memory and input/output devices as well as processing units can be shared between O8s, and many O8s can run simultaneously on one real computer. It can be so. For this purpose, two operating modes in the nine commercial machines, namely privileged mode and non-privileged mode, are utilized. In other words, the privileged mode is generally used as the operating mode of O8, but in VMS, the privileged mode is the operating mode of a special control program (this is called the virtual computing control program (hereinafter referred to as VMCP)). , the O8 operates in non-privileged mode.

A plurality of virtual machines (hereinafter referred to as VMs) are simulated by VMCP so as to be functionally equivalent to real computers.

FIG. 1 is a conceptual diagram of a normal VMS. The real computer 1 has a real computer interface VMCP4 that can handle processing requests (machine instructions) in privileged or non-privileged mode.
VMCP cow uses this to operate,
In order to enable the operation of 08311 and 08321 of each VM31.32, another real computer interface is provided to them.

Although two VMLs are not shown in FIG. 1, it is the same even if there are many VMs, 0831F, 321
will operate using the real computer interface provided by VM31.32, as if the real computer 1, h
It looks like it's working.

Also, 08311.321 is the user program 51
1,521.5'31.541. Here, expansion machines 51, 52
, 53, and 54 are functions for executing processing in each O8 in response to a request for a certain group of functional processing (supervisor call) from a user program, machine instructions in a non-privileged mode, and the like.

In this way, the relationship between VMCP4 and VM31, 32 is as follows:
This is similar to the relationship between the control program and processing program in general O8. That is, the VMCP4 corresponds to a control program, and the VMs 31 and 32 correspond to processing programs. Since VMs 31 and 32 generated by VM CP 4 execute in non-privileged mode,
Privileged instructions on VMs 31 and 32 are marked V as privileged instruction exceptions.
It is reported to MCP4, and VMCP4 executes the simulation.

FIG. 2 is a conceptual diagram of a conventional privileged instruction simulation of V1.

In FIG. 2, reference numeral 1 represents the hardware of the actual computer, which includes an arithmetic function and a VMA (firmware assist). 2 is a real storage device V M Cl) in which an interrupt processing program 21, a privileged instruction simulation program 22, and a VM startup processing program 23 are stored. 31, 32, and 33 are virtual storage VMs, respectively, which operate in a non-privileged mode.

Next, among the privileged instruction simulations by VMCP, PSW (Program 5tatus Wo
An overview of the simulation process for privileged instructions that control ra) will be described.

Generally, PSW uses asynchronous interrupts (input/output interrupts,
An interrupt mask is provided to control external interrupts, etc.), and resources such as these input/output devices and external devices are
Shared by M.

If an asynchronous interrupt occurs to a certain VM (VMl in FIG. 2) and the VM cannot handle the interrupt, the VMCP suspends the interrupt. In other words, the VMCP side performs processing to memorize the interrupt cause, and reflects the actual interrupt to the VM when control is transferred to the corresponding VM and the interrupt mask of the VM's PSW becomes interrupt-enabled. I have to. Therefore, the VMCP needs to provide means for storing the pending (bending) state of interrupts for the corresponding VM.

As shown by the arrow in Figure 2, when a privileged instruction is issued from a certain VM, processing requires V
There are two methods: simulating privileged instructions using an MCP, and simulating privileged instructions using a firmware assist (VMA) 44 structure from an arithmetic function. First, simulation in vMCP will be described.

FIG. 3 is a flowchart of a conventional simulation system for privileged instructions that control Psw.

Here, simulation is a method of interpreting and executing the operation of a privileged instruction of vN4 (for example, a PSw change operation) using a program of a real computer. Convert to address. It also contains the address of a routine programmed to process the instruction's opcode and perform the operation on the vM's opcode. By executing this routine, the previously fetched instruction is manipulated, and upon completion, the next instruction is fetched.

In FIG. 3, when the simulation is started, the VMCP first simulates a privileged instruction to the Psw of the VM (step 3o1).

If the PSW interrupt mask is set to °°1'' as a result of the privileged instruction simulation (when interrupts are enabled), check whether or not the asynchronous interrupt for that VM is bending (steps 302, 303). .

In step 303, if the asynchronous interrupt to the VM is bending, the interrupt cause is processed (
Step 304). Further, if the interrupt mask of the PSW is "°°0" in step 302, and if the asynchronous interrupt is not bending in step 303, it is checked whether the PSW has entered the wait state as a result of the privileged instruction simulation (step 305). ).In step 305, the PSW
When the VM is in a waiting state or after the interrupt processing is completed in step 304, the VM schedule and startup processing are performed (step 306).

This completes the operation of the simulation method.

Step 302 in FIG. 3 examines the interrupt mask, which is the interrupt mask in psw. In normal computer systems, ps is used as a mask for interrupts.
There are submasks separate from the interrupt mask in w. If an interrupt occurs when this submask is ++ O++, the interrupt will be a bending even if the PSW interrupt mask is NII II, and the submask will be "
It is necessary to reflect the bending interrupt only when it becomes I++. In the case of VMS, when the submask becomes I11, processing is entrusted to VMCP.

Next, the VMAM structure shown in FIG. 2 will be described.

In the VMS shown in FIG. 2, when the privileged instruction simulation is processed by the VMCP of the real storage device 2, the performance deteriorates considerably compared to when it is executed on the O8 under the real computer. That is, since simulation is a method of processing a program completely using software, it has advantages such as high flexibility, but the biggest drawback of Practical-L is that the execution speed is extremely slow.

Therefore, firmware assist (VMA) has been used to support the execution of privileged instructions on the VM. This VMA performs simulation on behalf of the VMCP, but since the interrupt processing and startup processing of the VMCP can be omitted, speeding up can be achieved.

However, this VMA processing is performed in steps 302, 303, . and 305 are performed, and if the conditions are met and if it is impossible for VMA to perform 1r rule j in the VMAM theory, then number J entrusts the processing to VMCP. Therefore, when a dispute is established, the process will be slow.

Furthermore, this VMA selects only single-line processing for the M sub-control block and performs the VMCP processing on behalf of it, so basically there is no difference in ψ5 from simulation. Therefore, compared to processing on a real computer,
It takes 2.3 times as much execution time for each special instruction.

Therefore, (1) V M &, -PS of the actual bell machine
By adopting a method such as making W exclusive or (ill V It is conceivable to directly execute instructions, that is, without VMCP and VMA intervention, and to provide almost the same performance as a real computer.

However, in the - direct execution method, if the conditions of steps 302, 303 and 305 in the flow of Fig. 3 are satisfied, interrupt hold/release processing and ■M startup processing are
It needs to be done in MCP.

Figure 4 shows a VM that directly executes privileged instructions on the VM.
FIG.

In FIG. 4, as in FIG. 2, a real computer microprogram 12 and a VMA microprogram 13 are provided in the real computer l, and a new determination microprogram 11 is provided.

When a privileged instruction is issued on the VM 3, the judgment microprogram 11 executes the third instruction before directly executing the privileged instruction.
Steps 302, 303 and 30 of the flow in the diagram
A determination process for δ is performed, and when the condition is satisfied, control is entrusted to the VMCP without directly executing it. The VMCP performs interrupt hold/release processing and VM startup processing in the same manner as described above, and transfers control to VM3. On the other hand, if the condition is not satisfied in the determination process, the real computer microprogram 12 uses the method described above (1) to make the βSW of the real computer old in VM or (II) VM
After directly executing the privileged instruction using a method of preparing a dedicated PSW for the VM, control is passed to the VM3.

According to this method, in the case of direct execution, the intervention of vMCP and VMA is not required, but the process of determining whether direct execution is possible is always necessary, and even if it is performed by a microprogram, it is still difficult to execute. The effect of direct execution is low because of the overhead for calculation i.

[Purpose of the invention]

The purpose of the present invention is to eliminate the need for the determination processing by the microprogram and to solve the problem described above.
By directly executing a privileged instruction that controls SW, V
MCP simulation.

An object of the present invention is to provide a virtual computer system that can reduce overhead and improve VMS performance.

[Summary of the invention]

In order to achieve the above object, the virtual machine system of the present invention includes an identification means for indicating that the contents of a PSW register that controls the operating state of an operating system is interruptible, and an identification means for indicating an interrupt pending factor for the operating system. and a means for interrupting the management program when the bending register indicates that there is an interrupt pending cause and the identifying means of the PSW register indicates that the interrupt is enabled, The feature is that each of the above means is operated after directly executing a privileged instruction on the system.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 5 is a block diagram of a VMS showing an embodiment of the present invention.

In the actual W1 calculation 1ml shown in FIG. 5, as in the case of FIG. 4, a real computer microprogram 12 for direct execution and a VMA microprogram 13 are provided, and A judgment hardware 14 is provided in place of the computer microprogram 11, but this is placed after the actual computer microprogram 12. In addition, a microprogram instruction 10 for determining whether or not the direct execution mode is in the preceding stage 1c of the above-mentioned microprograms 12 and 13 is arranged.

When a privileged instruction is issued from the VM 3, the actual computer 1 determines whether it is in the direct execution mode using the instruction IO, and if it is in the direct execution mode, the actual computer microprogram 12 executes the above-mentioned (1). PS of real computer in VM
Privileged instructions are directly executed either by occupying W or (II) by preparing a dedicated PSW for VM. In other cases, processing is performed by the VMA microprogram 13.

However, even in this VMA processing, if the conditions are satisfied in the processing of steps 302, 303 and 305 in the flow of FIG. 3, or if the processing cannot be performed by the VMA, it is necessary to entrust the processing to the VMCP. In other cases, control is immediately passed to the VM 3 when the VMA microphone 4 program 13 processes it.

On the other hand, in case number J processed by the real computer microprogram 12, the determination hardware 14 determines whether or not an interrupt to the VMCP is necessary. Here, steps 302 and 303 of the flow in FIG.
and 3050 determination processing is performed at high speed by hardware,
If the condition is met, an interrupt is made to VMCP, and if the condition is not met, control is immediately passed to VM3.

Among the processes described above, determining whether or not the direct execution mode is selected takes only a small amount of time by the microprogram and has almost no effect on performance. Furthermore, since the determination processing by the determination hardware 14 is performed at high speed as described above, this also requires only a short amount of time. Therefore, the processing of the VM privileged instruction in FIG. 5 can be made much faster than in FIG. 10.

Further, the VM of the main storage device 2 from the determination hardware 14
An interrupt to Cl) first breaks into the interrupt processing microprogram, and then interrupts the VMCP by hardware or microprogram. VM CP c, main memory 22 &:, VM CP specific (0 interrupt information storage area (i.e., prefix area)
Since this area is held, the L hardware or microprogram specifies an address to select this area.

FIG. 6 is a configuration diagram of the determination hardware in the fifth IIXl.

As shown in FIG. 6, the determination hardware 14 is in a program form? BM (PSW register) 101.1/O
1i11 included bending register (IOPNDR)
102, Bending register including external nBWJJ (F
XPNDR) 103, AN l) Circuits 104, 105
107 and an OR circuit 106.

In the psw register 101, when the I10 mask and EXT mask are 1'', it indicates that 110 interrupts and external interrupts are possible, respectively.In other words, by referring to these I10 mask and EXT mask, the flow of FIG. The judgment process in step 302 becomes possible.Also, p
When W in the sw register 101 is 1, it indicates that the PSw is in a waiting state. That is, by referring to this W bit, the determination process in step 305 of the flowchart in FIG. 3 can be performed.

Also, from VMCPM) / When the OQll interrupt is a bending CηC and the submask is interruptible, but there is one that cannot be interrupted because the PSW I/Q mask is °°0''. , "1" is cassetted in the bending register 102.Furthermore, VMCPc: external interrupts are bending, and interrupts are possible for submasks;
When there is a Psw that cannot be interrupted because the EXT mask of Psw is °'0'', II I 11 is set in the bending register 103. G;i is set in these bending registers 102 and 103. , When the VMCI (VMCI) issues a dedicated 1M startup instruction, the processing by the hardware of that instruction causes
The vending area in the control block of that VM is loaded. By referring to both of these vending registers 102 and 103, the judgment process in step 303 of the flow of FIG. 3 becomes possible.

First, the I10 mask of the ps, w register 101 and the bending register 102 become inputs to an AND circuit 104. ], ”, that is, when 110 interrupts are possible and 110 interrupts are bending, A
"1" is output from the ND circuit 104. In the same way, the EXT mask of the PSW register 101 and the bending register 103 become inputs to the AND circuit 105, and when both are "1", external interrupts are possible. If the external interrupt is bending, then
I11 is output from the D circuit 105. When either the output of the AND circuit 104- or the output of the AND circuit 105 is ++ I ++, or when the content of the W field of the PSW register 1 is II I ++, Of("l'" is output from the circuit 106. Then, when the output of the OR circuit 106 is 1'' and a psw change request is issued, the AND circuit 107 outputs 1''.

A, N', 1) When the output of the circuit 107 is "l"°, break into the interrupt processing microprogram. Nowadays, hardware or microprograms
Interrupt information storage area (prefix area) from ζ
is determined. In this case, since a VMCP-specific prefix area is held, by selecting that prefix, the VMCP is interrupted.

In this way, in this example, after executing the privileged command 10 times,
If necessary, control is passed to the V M CP by hardware, so the determination process by the microprogram before i11 implementation can be omitted, and high-speed processing becomes possible.

As a result, the effect of direct execution of a privileged instruction is greatly increased, and the performance can be almost the same as that of execution of a privileged instruction by an actual nl'j'A machine.

[Effects of the Invention] As explained above, according to the present invention, the privileged instruction that controls the PSW is directly executed and the interrupt determination from V to ICP is performed by hardware, so the VMCP simulation and overdrive are significantly reduced. (1) It becomes possible to improve the performance of the MS.

[Brief explanation of the drawings] Figure 1 is a conceptual diagram of the virtual n1 arithmetic system of curves;
The figure is a conceptual diagram of the simulation of privileged commands in a conventional virtual computer garden, Figure 3 is a flowchart of the conventional simulation method for PSW control ffi W privilege commands, and Figure 4 is a diagram of a system that directly executes privileged commands in virtual machine 1. Block diagram, FIG. 5 is a block diagram of a virtual computer system showing an embodiment of the present invention, and FIG. 6 is a block diagram of the hardware for determining φ (in FIG. 15. 1: Actual total number 1b'if, 2: Main memory, 3=virtual calculation + uL l O: Microprogram for determining whether to execute iIi conciliatory line, 12: Microprogram for practical computer, 1
3: VMA microprogram, 14: Judgment hardware, 21: Interrupt processing program, 22: Special Wa
Instruction simulation program, 23: vM startup processing program, 101: PSW register, 102'
, 103: Pending register, 104, 105,
107: AND circuit, 106: OR circuit. Fig. 1 5 soil 1 521 531 541 Fig. 2 Fig. 3 Fig. 5 Fig. 3 Fig. 6 Control block of Fig. ■゛, 1

Claims (1)

[Claims] (1) In a virtual computer system equipped with a management program that allows W number of operating systems to operate simultaneously on one real machine, a register (called psw) that controls the operating state of L number of operating systems.
an identification means for indicating that the content of the content is interruptible;
a bending register indicating the presence or absence of an interrupt pending factor for the operating system; means for setting the presence or absence of the interrupt pending factor in the bending register by the management program when starting the operating system; A virtual computer system comprising: means for interrupting the management program when the bending register indicates an interrupt pending cause and the identifying means of the PSW register indicates that interrupts are enabled. G2) The virtual machine according to claim 1, wherein the means for interrupting the management program interrupts the management program unconditionally when the operating system puts the contents of the PSW in a waiting state.