JPH07134658A - Address translation buffer control system for virtual machine system - Google Patents

Abstract

PURPOSE:To eliminate the overhead of the using rate decline of a translation lookaside buffer (TLB) and to improve performance by constituting a function for selectively purging an address conversion buffer entry using a virtual machine (VM) ID. CONSTITUTION:At the time of executing the selective purging of the address conversion buffer 710 issued by the VM, the function for selectively purging the address conversion buffer entry provided with the entry coincident to the VMID and the address conversion buffer entry provided with the entry 712 subordinate to the value of the VMID respectively is provided and the operations of the selective purging of both address conversion buffer entries are simultaneously and parallelly executed. Thus, at the time of executing an instruction for purging the TLB issued by a level 20S, execution is directly performed on the level 20S and an TLB purging operation to the entire TLB entries performed by the level 10S is eliminated.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus such as a virtual computer system, and more particularly to an address translation buffer of a virtual computer system suitable for address translation when the virtual computer of the virtual computer system operates. Regarding control method.

[0002]

2. Description of the Related Art Generally, in an information processing device using a virtual memory system, it is necessary to convert a virtual address into an absolute address in the main memory when the information processing device accesses data and command words in the main memory. is there. As a conventional technique relating to such general specifications and means for converting a virtual address into an absolute address on a main memory, for example, IBM
"Enterprise System Architectu", a publication issued by the company
re / 390 Principles of Operation ”(SA22-720
The techniques described in 1-00) and the like are known.

In recent years, an information processing apparatus called a virtual computer system has been realized, and its usage pattern is becoming generalized. The virtual computer system is to create a plurality of virtual computers under a single real computer to construct an information processing system. A virtual computer control program (hereinafter referred to as VMCP) is run on the real computer, Operating system (hereinafter referred to as OS) under the control of VMCP
Is configured to operate.

Generally, as a usage pattern of a computer constituting an information processing system, a method of operating a single OS on a real computer and a virtual computer (hereinafter, VM) operating a plurality of OSs on a single real computer are used. There is a method called. A mode in which a single OS operates on a real computer is called a basic mode, and the hardware resources of the real computer in that method are one or more central processing units (hereinafter, CPU or IP) and one unit. Shared main memory (hereinafter referred to as MS) and one or more channel paths (hereinafter referred to as CHP). The hardware resources of these real computers are treated as a single resource. In addition, a mode in which multiple VMs are built on a single real computer and multiple OSs operate is set to L
This is called PAR mode.

In order to realize a plurality of VMs on a single real computer, the virtual computer system operates a program called VMCP on the real computer and, under the control of this VMCP, the VMs which are the plurality of virtual computers. To generate
It is configured to operate an independent OS on each of these VMs. Therefore, the VMCP is added with a function of allowing each VM to share and use the hardware resources of a single real computer.

The hardware resources of a single real computer are assigned to each V
As a method of sharing with M, a method of allocating hardware resources by time division under the control of VMCP, a method of logically dividing hardware resources and allocating them exclusively to each VM, or the above-mentioned 2 There is a method of allocating the two methods in a mixed manner. As a conventional technique relating to the method of allocating the hardware resource of this single real computer to each VM, for example, a publication "Enterpri" issued by IBM Corporation is used.
se System / 9000 Enterprise System / 3090 Processor Re
source / System Manager Planning Guide ”(GA22-
7123-08) and the like are known.

The prior art introduced in this publication is
As a method of sharing the real CPU, the former one of the two methods described above, that is, the real CPU is time-divided into each VM
In addition, the latter method of the above-mentioned two methods, that is, the real CHP and the real MS, is used as a method of sharing the I / O channel and the MS by the VM.
Is logically divided and exclusively allocated to each VM.

In this prior art, when constructing a virtual computer system, an OS operating on a real computer (so-called VMCP, hereinafter referred to as level 1 OS or level 1V).
In the MCP, the level 1 OS creates the address translation table by itself, and operates the OS as a VM (hereinafter referred to as the level 2 OS or the level 2 VMCP) on the virtual address space on the level 1 OS. Furthermore, this level 2 OS also creates an address translation table to create a virtual address space.

Further, as one application of construction of a virtual computer system, VMCP is used as a level 1 OS operating on a real computer, and VMCP is also used as a level 2 OS operating on a virtual address space on the level 1 OS. A method of operating an OS (hereinafter, referred to as a level 3 OS) operating on a virtual address space of 2OS is also used as a very general method.

The above-mentioned prior art adopts a method of allocating real CPUs to each VM in a time-sharing manner as a method of sharing real CPUs of VMs. A conventional art of this kind will be described below with reference to the drawings.

FIG. 6 shows a real CP for a VM according to the prior art.
FIG. 3 is a block diagram showing a configuration of a virtual computer system for explaining U sharing. In FIG. 6, 101 is an MS, 102
Is a real CPU, 111 is a VMCP, and 121 to 123 are logical CPUs.

In FIG. 6, an actual CPU (hereinafter referred to as PIP) 102 is composed of one PIP 102.
The IP 102 is connected to the MS 101. PIP1
02, the VMCP 111 capable of controlling the VM is operating. Under control of this VMCP111, multiple VMs
Are generated, and each of the plurality of VMs is called a logical CPU (hereinafter, referred to as LIP) here. Then, the VMCP 111 is the LIPA 12 in FIG.
1, LIPB 122 and LIPX 123 are generated, and LIPA 121, LIPB 122 and L are generated.
On the IPX 123, independent OSs run.

The example shown in FIG. 6 has VMC on PIP 102.
This is an example of a virtual computer system in which one P11 is run, a plurality of VMs are created under the control of the P11, and a guest OS is run on each of the created VMs. is there.

Recently, in addition to the usage pattern illustrated in FIG. 6, P
A VMCP (hereinafter, referred to as level 1 VMCP) is run on the IP, a plurality of VMs are generated under the control of the VM, and a VMCP (hereinafter, referred to as level 2 VMCP) is further run on each of the generated VMs. A virtual computer system that creates a plurality of VMs under the control of 2VMCP and runs a guest OS on each of the created VMs has been realized and is becoming popular.

FIG. 7 is a block diagram showing a general configuration of the above virtual computer system. 7, 211 is a level 1 VMCP, 221 is a level 1 logical CPU, 231 is a level 2 VMCP, 241, 242 are level 2 logical CPUs, 251 and 252 are guest OSs, and other symbols are the same as those in FIG. is there. The example shown in FIG. 7 is a virtual computer system in which a level 1 VMCP 211 and a level 2 VMCP 231 are mounted on the PIP 102 according to the conventional technique shown in FIG. 6 and a VM is generated thereon.

In FIG. 7, PIP is one PIP1.
It consists of 02. The PIP 102 is connected to the MS 101. On the PIP 102, the level 1 VMCP 211 capable of controlling the VM is operating. This level 1VM
Under the control of the CP 211, a level 1 logical CPU (hereinafter, referred to as level 1 LIP) 221 which is a plurality of VMs is generated. On the level 1 LIP, the level 2 VMCP 231 capable of controlling the VM is operating. Under the control of the level 2 VMCP 231, a plurality of VMs are level 2 logical CPUs (hereinafter referred to as level 2 LIPs).
Is being generated. That is, level 2 VMCP 231
In FIG. 7, a plurality of VMs of the level 2 LIPA 241 and the level 2 LIPB 242 are generated, and the guest OS 251 and the guest OS 252 that are independent OSs run on the level 2 LIPA 241 and the level 2 LIPB 242, respectively.

FIG. 8 is a flow chart showing the control flow of the level 1 VMCP, level 2 VMCP, and level 3 guest OS when the virtual computer system configured as shown in FIG. 7 operates. The control flow when operating the virtual machine system configured as shown in FIG. 7 will be described with reference to FIG.

In FIG. 7, initially, level 1 VMCP2
11 operates with the value of the virtual computer ID (hereinafter referred to as VMID) set to "A". The VMID is a value automatically assigned to the VM operating on the real computer by the hardware and unique to each level 1 VMCP 211, and at the same time when the address translation pair of the logical address and the absolute address is registered in the TLB. It is registered in a part of the TLB entry and regulates the VM to which this address translation pair belongs.

When the level 1 VMCP 211 activates the level 2 VMCP 231 as a VM, a Start Interpretive Execution instruction (hereinafter, S) which is an instruction to activate the VM.
IE command) is used. The SIE instruction is a part of the IE function, and its general specification is, for example, the publication "IBM System / 370 Extended Architecture" issued by IBM Corporation.
The details are described in "Interpretive Execution" (SA22-7095). The operand address of the SIE instruction points to the area holding the register and other states of the VM to be activated, and this is the state description. (State Description: hereinafter referred to as SD) The general specifications of SD are described in detail, for example, in the above-mentioned publication issued by IBM Corporation.

That is, the level 1 VMCP is first activated by the SD (L1S) in order to activate the level 2 VMCP.
Set D) and issue the SIE command (steps 301, 302).

Level 2V activated by SIE instruction
The MCP 231 executes the instruction process as a VM.
At that time, the level 2 VMCP 231 operates with the value of the VMID set to “B”. The level 2 VMCP 231 issues an SIE instruction (hereinafter referred to as a virtual SIE instruction) after preparing an SD (L2SD) in order to start a level 3 guest OS operating under the control of the level 2 VMCP (step 303, 304).

The level 2 VMCP 231 is the virtual SI described above.
When the E instruction is issued, this virtual SIE instruction is intercepted and control is returned to the level 1 VMCP 211.

Here, the reason why the level 2 VMCP 211 is intercepted is that the level 2 VMCP 231 is:
This is because there is no means for managing real hardware resources.
When control returns to level 1 VMCP 211, level 1
The VMCP 211 is switched to operate with the value of VMID set to “A”. Level 1 VMCP211 is
Investigate the cause of interception and find the cause is Level 2
When the virtual SIE instruction issued by the VMCP 231 is found, the virtual SIE instruction is simulated.

Level 1 VMCP 211 is the virtual SI
Guest O of level 3 in E instruction simulation
Based on both the virtual SD prepared by the level 2 VMCP and the real hardware resource allocation state running by the level 1 VMCP that has accepted the interception, another SD (hereinafter, shadow SD) for starting the S Prepare and use this shadow SD as an operand
The command is issued (steps 305 and 306).

When the SIE instruction is issued using the shadow SD as an operand, control is transferred to the level 3 guest OS, and the guest OS is switched to operate with the VMID value of "C". The operation of issuing an SIE instruction using this shadow SD as an operand is as if the level 2 VMCP uses a virtual SD as an operand and a virtual SI.
E instructions are executed.

Thereafter, the guest OS of level 3 runs (step 307).

FIG. 9 is a block diagram showing the structure of a TLB provided with a VMID. Next, referring to FIG.
The control of the TLB provided with the MID will be described. In FIG. 9, reference numeral 410 is an address translation buffer, and 420 and 47.
0 is a selector, 430 is an output register, 440 is a VMI
D register, 450 to 452 are comparators, 460 is AND
Gates 480 are address translation control units.

In the TLB configuration shown in FIG. 9, the address translation buffer 410 is a hardware mechanism for rapidly converting a logical address when an IP accesses data and a command word into an absolute address, and an entry valid flag. 411 (hereinafter, referred to as V flag), and an entry 412 (hereinafter, VM) that holds a VMID to which the entry belongs.
An entry 413 (hereinafter referred to as an STO) that holds the segment table origin and address.
Entry 4), which holds a logical address
14 (hereinafter referred to as a logical address entry), an entry 415 that holds an absolute address corresponding to the logical address
(Hereinafter referred to as absolute address entry) and entry 4 that holds the main memory key assigned to the absolute address
16 (hereinafter referred to as main memory key entry). The address translation buffer 410 is made up of a plurality of groups of entries, with the above-mentioned related entry as one group.

The selector A 420 is a selector that receives a logical address when the IP accesses data and a command word and selects one set of related entries from a plurality of sets of entries in the address translation buffer 410. The output register 430 is a register that temporarily holds the contents of a set of related entries selected from a plurality of sets of entries in the address translation buffer 410.

Further, the VMID register 440 has an entry 441 (hereinafter referred to as a VMID entry) holding a VMID when the IP accesses data and a command word, and an entry 442 (hereinafter referred to as an SD absolute address corresponding to the VMID). , SD address entry). The VMID register 440 is made up of a plurality of sets of entries, with the related entry as one set.

This VMID register 440 is an operand of the SIE instruction, SD, when the VM runs on the IP.
SD address entry 442 corresponding to the address of the VMID entry 442 is selected, and the VMID entry 441 in the entry is selected as the VMID entry 412 in the address translation buffer 410
Compared to.

The comparator A450, the comparator B451 and the comparator C452 respectively have the contents of the VMID entry 412, the STO entry 413 and the logical address entry 414 which are temporarily held in the output register 430, and the V
This is a data comparator that compares the contents of the VMID entry 441 of the MID register 440, the segment table starting point used in main memory access, and the logical address associated with main memory access.

The AND gate 460 is connected to the comparator A450,
The AND gate is a logical product of the comparison results of the comparator B451 and the comparator C452. Further, the selector B470 selects the contents of the absolute address entry 415 and the main memory key entry 416 temporarily held in the output register 430 by the hit signal indicating the comparison match of the data sent from the AND gate 460 and sends them. The address translation control unit 480 is a selector that controls the entire operation of the TLB shown as a block diagram in FIG.

Next, the address conversion operation using the TLB configured as described above will be described.

In FIG. 9, when an access request to the main memory is issued from the PIP, the main memory access request and the logical address are sent from the PIP to the address translation buffer 410 via the signal line 4A0. When the address translation buffer 410 receives the main memory access request and the logical address from the PIP via the signal line 4A0,
The logical address is transferred to the selector A420 and the comparator C452.

Selector A42 which received the logical address
0 is the logical address value from the address translation buffer 41
Select one entry from multiple entry groups in 0,
A request to read this is issued. Upon receiving the entry read request, the address translation buffer 410 reads the corresponding one entry and sets the read data in the output register 430 via the signal line 4C0.

The breakdown of one entry that is read out and set in the output register 430 is the V flag 41.
1, VMID entry 412, STO entry 413,
Logical address entry 414, absolute address entry 4
15 and a main memory key entry 416. Also, VM
The ID register 440 selects the VMID entry 441 corresponding to the SD address entry 442 that holds the absolute address of the SD at the time when the access request to the main memory is issued, and the content of this VMID entry 441 is set on the signal line 4
Input to the comparator A450 via D0.

On the other hand, the address translation buffer 410 receives the entry read request, reads the corresponding one entry, sets the read data in the output register 430, and then compares whether or not the TLB entry is hit. Is done. This comparison is performed by the procedure described below.

First, the contents of the V flag 411 set in the output register 430 are ANDed via the signal line 4E0.
It is sent to the gate 460. Next, the content of the VMID entry 412 set in the output register 430 is sent to and input to the comparator A450 via the signal line 4E1.
The content of the VMID entry 441 of the MID register 440 is input to the comparator A450 via the signal line 4D0, and the comparator A450 compares both input data.
Then, a match or mismatch signal of the result of this comparison is sent to the AND gate 460 via the signal line 4E4.

Further, the content of the STO entry 413 set in the output register 430 is sent to and input to the comparator B451 via the signal line 4E2, and the logic when the access request to the main memory is issued from the PIP is issued. The segment table designation (hereinafter referred to as STD) corresponding to the address is input to the comparator B451 via the signal line 4A1, and both input data are compared in the comparator B451. Then, a match or mismatch signal of the result of this comparison is sent to the AND gate 460 via the signal line 4E5.

Further, the content of the STO entry 413 set in the output register 430 is sent to the comparator B451 via the signal line 4E2 and input, and the logic when the access request to the main memory is issued from the PIP is issued. The segment table designation (hereinafter referred to as STD) corresponding to the address is input to the comparator B451 via the signal line 4A1, and both input data are compared in the comparator B451. Then, a match or mismatch signal of the result of this comparison is sent to the AND gate 460 via the signal line 4E5.

Further, the contents of the logical address entry 414 set in the output register 430 is the same as the signal line 4E3.
The logical address when the PIP issues an access request to the main memory is input to the comparator C452 via the signal line 4A0, and is input to the comparator C452 via the signal line 4A0. The input data are compared. A match or mismatch signal of the result of this comparison is sent to the AND gate 460 via the signal line 4E6.

The AND gate 460 is connected to the signal line 4 described above.
EOL, signal line 4E4, signal line 4E5, and the logical product of the respective coincidence signals or non-coincidence signals input via signal line 4E6, and if all the signals are "1" (or coincidence), the TLB hit signal Is set to "1" and the signal line 4G
Send to 0. The TLB hit signal sent to the signal line 4G0 is the address translation control unit 480 and the selector B47.
Input to 0.

Upon receiving the TLB hit signal having the value “1” via the signal line 4G0, the selector B470 receives the absolute address entry 4 set in the output register 430.
15 and the signal line 4F0 and the signal line 4F1 sending out the contents of the main memory key entry 416 are selected, and the absolute address corresponding to the logical address output from the address conversion buffer 410 and the main address assigned to the absolute address are selected. The storage key is sent back to the requesting PIP.

Upon receiving the absolute address corresponding to the logical address and the main memory key assigned to the absolute address, the PIP issues an access request to the MS using the absolute address, and at the same time the key in the program state word (hereinafter, PS
The key control protection is checked using the W key) and the main memory key.

Further, the address conversion control unit 480 is
When the TLB hit signal of "1" is received through the signal line 4G0, the PIP is notified that the activation of the dynamic address translation process is unnecessary, and the TLB hit signal of "0" is received through the signal line 4G0. If it is received, P indicating that it is necessary to activate the dynamic address translation (hereinafter referred to as DAT) process.
Notify the IP and activate the DAT operation. The general specifications for this DAT are described in detail, for example, in the aforementioned publications.

Address information such as an absolute address obtained as a result of the DAT operation is obtained through the signal line 4B0 and registered in the address conversion buffer 410. That is, the logical address accompanying the access request to the main memory, the S at that time
Absolute address obtained as a result of TD, VMID, DAT,
And, the main memory key is a TLB entry determined by the logical address of the address translation buffer 410,
The V flag 411, the VMID entry 412, the STO entry 413, the logical address entry 414, the absolute address entry 415, and the main memory key entry 416 are registered via the signal line 4B0.

Then, this registered TLB entry is used for subsequent MS access. The TLB entry registration at this time is mainly performed by a hardware logic or a microprogram. Also, DAT
Registration of the content of the VMID entry 441 and the content of the SD address entry 442 of the VMID register 440 by the operation is performed mainly by the microprogram via the signal lines 4H0 and 4H1.

Next, the purging operation of the address translation buffer in the TLB shown in FIG. 9 will be described.

In FIG. 9, when a TLB purge request is issued from the PIP, the TLB entry number is changed to the signal line 4A.
It is sent from the PIP to the address translation buffer 410 via 0. The address translation buffer 410 sends the TLB purge request from the PIP and the T request via the signal line 4A0.
Upon receiving the LB entry number and the TLB entry number, the selector A 420 selects one entry from the plurality of entry groups in the address translation buffer 410 based on the value of the TLB entry number, and issues a read request.

When the address translation buffer 410 receives the entry read request, it reads the corresponding one entry and sets the read data in the output register 430 via the signal line 4C0. The contents of one entry read out by this and set in the output register 430 are: V flag 411, VMID entry 412, STO.
An entry 413, a logical address entry 414, an absolute address entry 415 and a main memory key entry 416. Further, the VMID register 440 selects the VMID entry 441 corresponding to the SD address entry 442 holding the absolute address of the SD at the time when the TLB purge request is issued, and the content of this VMID entry 441 is sent via the signal line 4D0. Input to the comparator A450.

On the other hand, the address translation buffer 410 receives the entry read request, reads the corresponding one entry, sets the read data in the output register 430, and then compares whether or not the TLB entry needs to be purged. Is done. This comparison is performed according to the procedure described below.

First, the content of the VMID entry 412 set in the output register 430 is sent to and input to the comparator A450 via the signal line 4E1, and the content of the VMID entry 441 of the VMID register 440 is input to the signal line 4D.
It is input to the comparator A450 via 0, and the comparator A450
In, both input data are compared. A match or mismatch signal as a result of this comparison is sent to the address conversion buffer 410 via the signal line 4E4. If the signal of this comparison result is "1" (match), the V flag 41 of the selected TLB entry of the address translation buffer 410 is obtained.
Write "0" in 1 to invalidate the TLB entry. If the signal of the comparison result is "0" (mismatch), the TLB entry is not invalidated.

FIG. 10 is a view for explaining the area allocation of the MS according to the prior art to each level OS (VMCP) in the system shown in FIG.

An example of MS area allocation shown in FIG.
In the virtual machine system according to the conventional technology, the level 1 OS operating on the real computer creates the address translation table by itself, and operates the level 2 OS as the VM on the virtual address space on the level 1 OS.
The OS is also an example of allocating an area of the real MS to the system that creates the address conversion table and creates the virtual address space. That is, in FIG. 10, a VMCP 510 is a level 2 OS operating on a real computer and a level 2 OS operating on a virtual address space on the level 1 OS.
The VMCP 520 is used as the real MS area allocated to the level 1 OS of the system that operates the level 3 OS 530 on the virtual address space on the level 2 OS, and the level 2 operating on the virtual address space on the level 1 OS
The real MS area allocated to the OS and the real MS area allocated to the level 3 OS operating on the virtual address space on the level 2 OS are shown.

In the example shown in FIG. 10, level 1 VMC
The real MS area assigned to P510 is the area shown in area A, which is equal to all real MS areas. The real MS area assigned to the level 2 VMCP 520 operating in the virtual address space on the level 1 VMCP 510 is the area shown by the area B, which is assigned to a part of the area A as shown in FIG. Also, level 2
The real MS area assigned to the level 3 OS 530 operating in the virtual address space on the VMCP 520 is the area C
This is the area indicated by, and this is area B as shown in FIG.
Assigned to a part of.

Then, the level 1 VMCP 510 runs with the value of the assigned VMID being "A", and the level 1 VMCP 510
Level 2 VM operating on virtual address space on 510
The CP 520 runs with the value of the allocated VMID being “B”, and the level 3 OS 530 operating in the virtual address space on the level 2 VMCP 520 is the allocated VM.
The vehicle runs with an ID of "C".

That is, the level 1 VMCP 510 runs using the area A of the MS with the assigned VMID being "A", and the level 2 VMCP 520 is assigned VMID.
Is a value of "B", the area V is a part of the area A of the MS, and the level 3 OS 530 is assigned VMI.
The vehicle travels using the area C, which is a part of the area B when D has a value of "C".

FIGS. 11 and 12 show the case where the virtual computer system configured as shown in FIG. 7 operates and the TL
9 is a flowchart showing a control flow of a level 1 VMCP, a level 2 VMCP, and a level 3 guest OS when B purging is required.

Below, with reference to the flow charts shown in FIGS. 11 and 12, when the virtual computer system configured as shown in FIG. 4 is operated and further TLB purging is required, level 1 VMCP, level 1 2VMCP and level 3
The control flow of the OS will be described assuming that the MS is assigned as shown in FIG.

Step 601: Level 1 VMCP51
0 is a level 2 VMC as a pre-process for running a level 3 guest OS on a level 1 VMCP 510 VM.
SD (hereinafter referred to as L1SD) which is an operand of the SIE instruction for activating P520 is initialized as predetermined.

Step 602: Level 1 VMCP51
0 is SI with L1SD which is the operand of the SIE instruction initialized in step 601 as the operand.
Issue the E instruction to activate the level 2 VMCP 520 on the VM of the level 1 VMCP 510. From this point, control starts from level 1 VMCP 510 to level 2 VMCP 52.
Move to 0.

Step 603: Level 1 VMCP51
Level 2 VMCP 520 runs on 0 VMs. The level 2 VMCP 520 is a VM of the level 2 VMCP 520
As a pre-processing to run the level 3 OS 530 above,
SD (hereinafter referred to as L2SD) which is an operand of the SIE instruction for activating the level 3 OS 530 is initialized in a predetermined manner.

Step 604: Level 2 VMCP52
0 is SI with L2SD which is the operand of the SIE instruction initialized in step 603 as an operand.
E command is issued to try to activate the level 3 OS 530 on the VM of the level 2 VMCP 520.

Step 605: In step 604, when the level 2 VMCP 520 issues an SIE instruction while trying to activate the level 3 OS 530 on the VM of the level 2 VMCP 520, this SIE instruction has an instruction interception factor. Occurrence and control is returned to the Level 1 VMCP 510 from the Level 2 VMCP 520 on the VM of the Level 1 VMCP 510.

Step 606: Level 1 VMCP51
0 analyzes the interception code which caused the control to be returned to the level 1 VMCP 510 from the level 2 VMCP 520 on the VM of the level 1 VMCP 510, and performs the interception process for each code. In this case, the interception code indicates instruction interception.

Step 607: The specific processing content of this processing is to carry out the processing corresponding to each interception code separately. For example, if the interception code indicates instruction interception, the instruction Perform a simulation. In this example, since the instruction interception occurred while trying to execute the SIE instruction, the simulation of the SIE instruction is performed.

Level 1 VMCP 510 is level 1 VM
As a pre-process for running the level 3 OS 530 on the VM of the CP 510, the L1SD prepared for starting the level 2 VMCP 520 and the L2SD prepared for starting the level 3 OS 530 are combined to generate the level 1 VM.
A provisional SD (hereinafter referred to as a shadow SD) for running the level 3 OS 530 on the VM of the CP 510 is initialized in a predetermined manner.

Step 608: Level 1 VMCP51
0 issues the SIE instruction with the shadow SD which is the operand of the SIE instruction initialized in step 607 as an operand, and activates the level 3 OS 530 on the VM of the level 1 VMCP 510. This activation is equivalent to activating the level 3 OS 530 on the VM of the level 2 VMCP 520. Control is level 1 from this point
Move from the VMCP 510 to the level 3 OS 530.

Step 609: Level 2 VMCP52
The level 3 OS 530 runs on the VM of 0 and executes a predetermined process.

Step 610: Level 2 VMCP52
While the level 3 OS 530 is executing the process on the VM of 0, the address translation exception related to the address translation table controlled by the level 2 VMCP 520 (hereinafter referred to as level 2) by the MS access issued from the level 3 OS 530.
An address translation exception) is detected. Details of Level 2 address translation exceptions are described in the aforementioned publications.

Step 611: In step 610, when the level 3 OS 530 on the VM of the level 2 VMCP 520 detects the level 2 address translation exception, this address translation exception has a host interrupt factor, so a program interrupt to the host occurs. , Control is level 2 VMC
Level 3 OS 530 on VM of P520 to level 1V
Returned to MCP510.

Step 612: Level 1 VMCP51
0 analyzes the host program interrupt code that caused the control to be returned to the level 1 VMCP 510 from the level 3 OS 530 on the VM of the level 2 VMCP 520, and performs interrupt processing for each code. In this case, the host program interrupt code indicates a level 2 address translation exception.

Step 613: The specific processing content of this processing is that the processing corresponding to each interrupt code is separately performed. For example, if the interrupt code indicates a level 2 address translation exception, the level 2 VMCP 520 is processed. Notify an address translation exception. In this example, level 2 VMC
Since the level 3 OS 530 on the VM of P520 detected the level 2 address translation exception, the level 1 VMC
The P510 notifies the level 2 VMCP 520 of the address translation exception.

That is, since the level 1 VMCP 510 notifies the level 2 VMCP 520 of the address translation exception, the level 2 VMC on the VM of the level 1 VMCP 510.
Level 2 VMC as pre-processing to run P520
L1SD prepared for starting P520 and shadow SD prepared for starting Level 3 OS 530
Are combined and L1SD for activating the level 2 VMCP 520 is initialized in a predetermined manner.

Step 614: Level 1 VMCP51
0 is SI with the L1SD which is the operand of the SIE instruction initialized in step 613 as the operand.
Issue the E instruction to activate the level 2 VMCP 520 on the VM of the level 1 VMCP 510. Level 2 at this time
In the PSA of the VMCP 520, the interrupt parameter associated with the address translation exception is stored in advance by the level 1 VMCP 510, and the instruction address field of the interrupt PSW in the PSA of the level 2 VMCP 520 is stored in the instruction address field in the L1SD. . That is, the level 1 VMCP 510 is the same as the level 2 VMCP 52
Simulate an address translation exception interrupt for 0. From this point, control begins at level 1 VMCP510.
To Level 2 VMCP520.

Step 615: Level 2 VMCP52
0 analyzes the interrupt code notified from the level 1 VMCP 510 and performs interrupt processing for each code. In this case, the interrupt code indicates an address translation exception interrupt.

Step 616: The specific processing content of this processing is to perform the processing corresponding to each interrupt code separately. For example, if the interrupt code indicates an address translation exception interrupt, the address translation table Rewrite and maintain. In this example, since the address translation exception interrupt has occurred, the address translation table is maintained.

Step 617: Level 2 VMCP52
0 executes maintenance processing of the address translation table, and as a part of the maintenance processing of the address translation table, Purge T
Issue the LB instruction (hereinafter referred to as the PTLB instruction). P
Details of the TLB instruction specifications are described in the aforementioned publications.

Step 618: In step 617, when the level 2 VMCP 520 issues a PTLB instruction, this PTLB instruction has an instruction interception factor, so instruction interception occurs, and control is performed at the level 2 VMCP 52 on the VM of the level 1 VMCP 510.
Returned from 0 to level 1 VMCP 510.

Step 619: Level 1 VMCP51
0 is level 2 VMCP520 to level 1 VM
The interception code that is a factor returned to the CP 510 is analyzed, and the interception process for each code is performed. In this case, the interception code indicates instruction interception.

Step 620: The specific processing content of this processing is to carry out the processing corresponding to each interception code separately. For example, if the interception code indicates instruction interception, this instruction Perform a simulation. In this example, level 1V
Level 2 VMCP520 on VM of MCP510 is PT
Since an instruction interception occurred while trying to execute the LB instruction, the level 1 VMCP 510 is set to P
Simulate the TLB instruction.

Step 621: Level 1 VMCP51
On 0, the PTLB instruction is issued as part of the PTLB instruction simulation process. By executing this PTLB instruction, all TLB entries having the values of all VMIDs are purged.

Step 622: Level 1 VMCP51
0 is level 2 VM on level 1 VMCP 510 VM
Level 2 VM as a pre-processing to run CP520
The L1SD which is the operand of the SIE instruction for activating the CP 520 is initialized in a predetermined manner.

Step 623: Level 1 VMCP51
0 is SI with L1SD which is the operand of the SIE instruction initialized in step 622 as the operand.
Issue the E instruction to activate the level 2 VMCP 520 on the VM of the level 1 VMCP 510. From this point, control starts from level 1 VMCP 510 to level 2 VMCP 52.
Move to 0.

Step 624: Level 1 VMCP51
Level 2 VMCP 520 runs on 0 VMs. Since the level 2 VMCP 520 has completed the simulation processing of the level 2 address translation exception detected by the level 3 OS 530, it is necessary to activate the level 3 OS 530 again. Therefore, as pre-processing for running the level 3 OS 530 on the VM of the level 2 VMCP 520, SIE
The L2SD which is the operand of the instruction is initialized in a predetermined manner.

Step 625: Level 2 VMCP52
0 is SI with L2SD which is the operand of the SIE instruction initialized in step 624 as an operand.
E command is issued to try to activate the level 3 OS 530 on the VM of the level 2 VMCP 520.

Step 626: In step 625, when the level 2 VMCP 520 issues an SIE instruction while trying to activate the level 3 OS 530 on the VM of the level 2 VMCP 520, this SIE instruction has an instruction interception factor. Occurring and control is returned from the level 2 VMCP 520 on the VM of the level 1 VMCP 510 to the level 1 VMCP 510.

Step 627: Level 1 VMCP51
0 analyzes the interception code which caused the control to be returned to the level 1 VMCP 510 from the level 2 VMCP 520 on the VM of the level 1 VMCP 510, and performs the interception process for each code. In this case, the interception code indicates instruction interception.

Step 628: The specific processing content of this processing is to carry out the processing corresponding to each interception code separately. For example, if the interception code indicates instruction interception, this instruction Perform a simulation. In this example, since the instruction interception occurred while trying to execute the SIE instruction, the level 1 VMCP 510 simulates the SIE instruction. Level 1 VMCP510
Is a level 3 OS5 on a level 1 VMCP 510 VM.
Level 2 VMCP5 as pre-processing to run 30
L1SD and level 3O prepared to start 20
L2SD prepared for starting S530 is combined, and level 3 OS5 is executed on the VM of level 1 VMCP 510.
Initialize the shadow SD for running the 30 as specified.

Step 629: Level 1 VMCP51
0 issues the SIE instruction using the shadow SD which is the operand of the SIE instruction initialized in step 628 as an operand, and activates the level 3 OS 530 on the VM of the level 1 VMCP 510. This activation is equivalent to activating the level 3 OS 530 on the VM of the level 2 VMCP 520. Control is level 1 from this point
Move from the VMCP 510 to the level 3 OS 530.

Step 630: Level 2 VMCP52
Level 3 OS 530 runs on 0 VM.

As described above, in the conventional virtual machine processing, the processing of the level 2 address translation exception detected by the level 3 OS 530 is performed by the level 1 VMCP 510 and the level 2 VMC from step 611 to step 630.
This is realized by the cooperative operation of P520.

In addition, the above-mentioned conventional technique is a level 3 OS.
Since the 530 operates with the value of VMID as "C" and the level 2 OS 520 operates with the value of VMID as "B", this PTLB instruction is intercepted in order to simulate the PTLB instruction issued by the level 2 OS 520. Then, the PTLB instruction is issued by simulation at the level 1 VMCP510, and all VMI
It was necessary to purge the TLB entry with D.

The virtual machine system according to the prior art described above has the TLB in the level 2 OS like the processing of the level 2 address translation exception detected in the level 3 OS.
When purging the PTLB, it is impossible to directly execute the PTLB instruction on the level 2 OS, and the PT for the issuance of the PTLB instruction on the level 2 OS due to the intervention of the level 1 OS.
LB instruction simulation operation was required. Then, in the above-mentioned conventional technique, all the TLB entries are purged by the execution instruction of the PTLB instruction, and the TLB entries that should not be originally purged are also purged.

Therefore, in the above-described conventional virtual computer system, the TLB usage efficiency is significantly reduced, which causes an overhead to the system and hinders the performance improvement of the virtual computer system.

[0097]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
When purging the TLB in the level 2 OS like the processing of the level 2 address translation exception detected in the level 3 OS, it was impossible to directly execute the PTLB instruction on the level 2 OS. Therefore, in the above-mentioned conventional technique, in response to the issuance of the PTLB instruction on the level 2 OS,
The PTLB instruction simulation operation for the PTLB instruction issuance on the level 2 OS due to the above-mentioned intervention was required.

The processing time required for this operation becomes a major factor that hinders the performance improvement of the virtual computer system as an overhead, and issuance of the PTLB instruction by the level 1 OS requires that all TLB entries are purged and originally purged. I also purged the missing TLB entries.

Accordingly, the above-mentioned conventional technique can be
There is a major problem that cannot be ignored in the performance of the virtual computer system, that is, the use efficiency of the virtual computer system is significantly reduced, and the overhead resulting from this is a major factor that hinders the performance improvement of the virtual computer system.

The object of the present invention is to solve the above-mentioned problems of the prior art, and when it is necessary to purge the TLB in the level 2 OS in the processing of the level 2 address translation exception detected in the level 3 OS, Allows the PTLB instruction to be executed directly, which allows level 1
Address translation buffer control of the virtual computer system that can improve the performance of the virtual computer system by removing the overhead such as the reduction of the TLB usage efficiency due to the TLB purge operation using the PTLB instruction for all TLB entries performed by the OS. To provide a method.

[0101]

According to the present invention, the above-described object will be described below with respect to the function of selectively purging the address translation buffer entry using the VMID when allocating the VMID to each VM and purging the address translation buffer. It is achieved by the configuration.

That is, according to the present invention, the value of VMID assigned when the level 1 OS runs is changed to the level 2O.
VM that is determined when S and level 3 OS are running, and is assigned when level 2 OS is running
The value of ID is determined as a value dependent on the value of VMID assigned when the level 1 OS runs. Similarly, the V assigned when the level 3 OS is running
The value of MID is determined as a value dependent on the value of VMID assigned when the level 2 OS runs.

The above-mentioned object is a function of selectively purging an address translation buffer entry having a VMID entry matching the VMID of the VM when executing an instruction accompanied by the selective purging of the address translation buffer issued by the VM. And a function of selectively purging an address translation buffer entry having a VMID entry subordinate to the VMID value of the VM, and a VM of the VM.
Selective purging of address translation buffer entries with VMID entries matching the ID, and other VMs with the value of one or more VMIDs dependent on the VM
This is achieved by providing the function of executing the selective purging operation of the address translation buffer entry having the ID entry in parallel at the same time.

[0104]

According to the address translation buffer control method of the virtual computer system according to the present invention, when executing the instruction accompanied by the purge of the address translation buffer issued by the VM, the IP
VMID that stores the VMID of the VM in the
The VM that the VM has by using the corresponding entry in the register
Only the address translation buffer entry having the VMID entry that matches the ID can be selected, and the purging operation can be performed by the hardware in synchronization with the execution of the instruction for the entry. At the same time, an address translation buffer entry having a specific VMID entry different from the VMID of the VM, that is, an address translation buffer entry having a VMID entry that matches the value of a VMID that is dependent on the VM of another VM. Can be selected to perform the purge operation for the entry selected by the hardware in synchronization with the execution of the instruction.

As described above, as a result of applying the address translation buffer control method according to the present invention to the virtual machine system, when the TLB purging instruction issued by the level 2 OS is executed, the PTLB instruction is directly executed on the level 2 OS. Level 1O that was necessary in the prior art
Since the TLB purge operation using the PTLB instruction for all TLB entries performed by S can be eliminated,
TL for all TLB entries made by Level 1 OS
It is possible to remove the overhead for the system caused by the decrease in the TLB usage efficiency due to the B purge.

Therefore, according to the present invention, the processing time required for the above-mentioned operation by the level 1 OS, that is, the overhead for the system, which is required in the prior art, can be eliminated, so that the system performance of the virtual computer system is significantly improved. Can be improved.

[0107]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an address translation buffer control system for a virtual computer system according to the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a VM used in one embodiment of the present invention.
FIG. 2 is a block diagram showing the structure of a TLB provided with an ID, FIG. 2 is a block diagram showing the detailed structure of an AND gate formed in the TLB, and FIG. 3 is a diagram explaining the operation of the AND gate. 1 and 2, 710 is an address conversion buffer, 720 and 770 are selectors, 730 is an output register, 740 is a VMID register, 75A to 75C are comparators, 750, 760, 7B60 to 7B63 are AND gates, and 780 is an address. Conversion controller, 7B50 to 7B5
3 is an OR gate.

In the configuration of the TLB shown in FIG. 1, the address translation buffer 710 is a hardware mechanism for rapidly converting a logical address when an IP accesses data and an instruction word into an absolute address, and a V flag 71.
1, VMID entry 712, STO entry 713,
Logical address entry 714, absolute address entry 7
15 and main memory key entry 716. Then, this address translation buffer 71
0 is composed of a plurality of groups of entries, each group including the above-mentioned related entry.

The selector A 720 is a selector which receives a logical address when the IP accesses the data and the instruction word and selects one set of related entries from the plurality of sets of entry of the address translation buffer 710. The output register 730 is a register that temporarily holds the contents of a set of related entries selected from a plurality of sets of entry groups in the address translation buffer 710.

The VMID register 740 is composed of a VMID entry 741 and an SD address entry 742. The VMID register 740 is made up of a plurality of sets of entries, with the above-mentioned related entry as one set.

This VMID register 740 is used as an operand of the SIE instruction SD when the VM runs on the IP.
SD address entry 742 corresponding to the address of the VMID entry 742 is selected, and the VMID entry 741 in the entry is selected,
Compared to.

The comparator A75A, the comparator B75B, and the comparator C75C respectively have the contents of the VMID entry 712, the STO entry 713, and the logical address entry 714 temporarily stored in the output register 730, and the V
This is a data comparator that compares the contents of the VMID entry 741 of the MID register 740, the segment table starting point used in main memory access, and the logical address associated with main memory access.

The AND gate 750 has a part of the contents of the VMID entry 741 of the VMID register 740 and the VMID entry 7 temporarily held in the output register 730.
It is an AND gate that takes a logical product with 12. Also, AN
The D gate 760 is an AND gate that takes the logical product of the comparison results of the comparator A75A, the comparator B75B, and the comparator C75C.

The selector B 770 has an output register 730.
The contents of the absolute address entry 715 and the main memory key entry 716 temporarily stored in the AND gate 76
The address conversion control unit 780 is a control unit that controls the entire TLB operation shown in the block diagram of FIG.

When performing the partial purge of the TLB, the comparator A75A described above, the contents of the VMID entry 741, a part of the contents of the VMID entry 741 and the VMID entry 71 temporarily held in the output register 730.
It is also a data comparator for comparing the logical product output of 2.

Next, the purging operation of the TLB address translation buffer used in the present invention configured as described above will be described.

In FIG. 1, when a TLB purge request is issued from the PIP, the TLB entry number is changed from the PIP to the address translation buffer 710 via the signal line 7A0.
Will be sent to. The address translation buffer 710 receives the TLB purge request from the PIP and its TLB entry number via the signal line 7A0. One entry is selected from the entry group and a read request is issued.

Upon receiving the entry read request, the address translation buffer 710 reads the corresponding one entry and sets the read data in the output register 730 via the signal line 7C0. The contents of one entry read out by this and set in the output register 730 are: V flag 711, VMID entry 712, STO.
An entry 713, a logical address entry 714, an absolute address entry 715 and a main memory key entry 716. Further, the VMID register 740 corresponds to the SD address entry 742 that holds the absolute address of the same SD using the absolute address of SD sent via the signal line 7H1 at the time when the TLB purge request is issued. VMID entry 741 to be selected.

This selection operation is mainly performed by the microprogram, and the contents of the VMID entry 741 corresponding to the SD address entry 742 are sent to the signal line 780. After that, the contents of the signal line 780 are
75A and AND gate 750. at the same time,
The VMID entry 712 temporarily held in the output register 730 is transferred to the AND gate 7 via the signal line 7E1.
50 is input. The comparator A75A compares the content of the signal line 780 with the output of the AND gate 750, and outputs the result to the signal line 7I0. This output is used to control whether the illustrated TLB entry needs to be purged.

A match or mismatch signal of the result of this comparison is sent to the address conversion buffer 710 and the address conversion control unit 780 via the signal line 7I0. If this signal is "1" (match), the V flag 71 of the selected TLB entry in the address translation buffer 710 is detected.
“0” is written in 1 and the TLB entry is invalidated. Also, the signal of this comparison result is "0" (mismatch)
If so, the TLB entry is not invalidated.

Next, referring to FIG. 2, the AND gate 750 which controls the purging of the TLB entry will be described.

The illustrated AND gate 750 controls whether or not purging of TLB entries is necessary in the address translation buffer control method of the virtual machine system according to the embodiment of the present invention. In FIG. 2, the VMID register 740 is used. Signal line 78 from the VMID entry 741 of
The signals from bit 0 to bit 3 from the signal line group 7B10 corresponding to 0 are OR gates 7B50, OR
Gate 7B51, OR gate 7B52 and OR gate 7
The data is input to B53, logically operated as shown in FIG. 2, and output from each OR gate.

These OR gate 7B50, OR gate 7B51, OR gate 7B52 and OR gate 7B53.
Are output from AND gate 7B60, AND gate 7B61, AND gate 7B62 and AND gate 7 respectively.
Input to B63. Also, the VM of the output register 730
Signal line group 7B2 which is a signal line from the ID entry 712
Each signal from 0 to bit 0 to bit 3 is
AND gate 7B60, AND gate 7B61, AND
Input to the gate 7B62 and the AND gate 7B63,
The outputs of the OR gate 7B50, the OR gate 7B51, the OR gate 7B52, and the OR gate 7B53 are logically ANDed and output from bit 0 to bit 3 of the signal line group 7B30. The output of the signal line group 7B30 is the AND in FIG.
The output of the gate 750, which is one input of the comparator A75A, is compared with the VMID data input via the signal line 780.

FIG. 3 for explaining the operation of the AND gate 750.
Shows the relationship between the data pattern input to the signal line group 7B10 and the signal line group 7B20 and the data pattern output to the signal line group 7B30.

As can be seen from FIG. 3, the right 2-bit or 1-bit data of the input data pattern of the signal line group 7B20 is converted into "0" by the input data pattern of the signal line group 7B10 and output to the signal line group 7B30. To be done. According to the input data pattern of the signal line group 7B10, the signal line group 7
The 2-bit or 1-bit data on the right side of the input data pattern of B20 is converted to "0" and output to the signal line group 7B30, which means that the VMID entry sent to the signal line 780 in the TLB shown in FIG. The contents of 741 are input to the comparator A75A and the AND gate 750, and further sent via the signal line 7E1. AN
This means that the data of the VMID entry 712 input to the D gate 750 undergoes the above-mentioned conversion by the AND gate 750, is compared by the comparator A75A, and the result is output to the signal line 7I0. This output is TL
Used to control whether purging of B entries is required.
For example, if the content of the VMID entry 741 sent to the signal line 780 is “1100” in binary, the VMID entries having binary patterns of “1100”, “1101”, “1110”, and “1111” are displayed. TL to have
B entry will be partially purged. If the content of the VMID entry 741 sent to the signal line 780 is “1010” in binary, it is “10” in binary.
The TLB entry having the VMID entries having the patterns of 10 "and" 1011 "is partially purged. Further, if the content of the VMID entry 741 sent to the signal line 780 is" 1011 "in binary number. ,
A TLB entry having a VMID entry having a binary pattern of "1011" will be partially purged.

As described above, by using the AND gate having the structure shown in FIG. 2, the TLB shown in FIG.
It is understood that, by configuring the above, the TLB entry group having a plurality of VMID entries can be partially purged at the same time by using one VMID entry.

Level 1V as described with reference to FIG.
Area A allocated to MCP510, level 1 VMC
Level 2V operating on virtual address space on P510
Area B allocated to MCP520 and level 2 VM
Level 3 operating on the virtual address space on the CP520
Assuming that each of the areas C allocated to the OS 530 runs with the values of VMID “A”, VMID “B” and VMID “C”, the VMID “A” of the area A is set to 2
Set the VMID “B” in area B to 2 with a decimal number of “1100”
Set it to "1110" in radix and add VMID of area C
If "C" is set to "1111" in binary, level 1
The command to purge the TLB issued by VMCP510 is
The corresponding TLB entries in the areas A, B and C can be partially purged by one TLB purging operation. Similarly, the TLB issued by the level 2 VMCP 520
The command for purging is the corresponding TL of area B and area C.
The B entry can be partially purged by one TLB purge operation, and the TLB purge command issued by the level 3 OS 530 can partially purge only the corresponding TLB entry in the area C by one TLB purge operation. it can.

Next, an example of a processing procedure of the address translation buffer control method of the virtual computer system according to the embodiment of the present invention will be described in detail with reference to the drawings.

FIGS. 4 and 5 are flow charts showing the processing procedure of the address translation buffer control system of the virtual computer system according to the present invention, and the level when the virtual computer system configured as described with reference to FIG. 7 operates. 1
VMCP, Level 2 VMCP and Level 3 guest OS
Shows the control flow of.

Hereinafter, assuming that the allocation of the MS to each level OS is performed as described with reference to FIG. 10, the processing procedure in one embodiment of the present invention will be described with reference to FIGS. 1, 4 and 5. The details will be described.

Step 801: Level 1 VMCP51
0 is a level 2 VMC as a pre-process for running a level 3 guest OS on a level 1 VMCP 510 VM.
The L1SD which is the operand of the SIE instruction for activating P520 is initialized in a predetermined manner. At this time, the level 1 VMCP 510 is running with the VMID set to binary “1100”.

Step 802: Level 1 VMCP51
0 is an SI with the L1SD which is the operand of the SIE instruction initialized in step 801 as the operand.
Issue the E instruction to activate the level 2 VMCP 520 on the VM of the level 1 VMCP 510. From this point, control starts from level 1 VMCP 510 to level 2 VMCP 52.
Move to 0. At this time, the level 2 VMCP 520 is
The ID is set to a binary number "1110" and set by the microprogram to run.

Step 803: Level 1 VMCP51
Level 2 VMCP 520 runs on 0 VMs. The level 2 VMCP 520 is a VM of the level 2 VMCP 520
As a pre-processing to run the level 3 OS 530 above,
The L2SD which is the operand of the SIE instruction for activating the level 3 OS 530 is initialized in a predetermined manner.

Step 804: Level 2 VMCP52
0 is SI with L2SD which is the operand of the SIE instruction initialized in step 803 as an operand.
E command is issued to try to activate the level 3 OS 530 on the VM of the level 2 VMCP 520.

Step 805: In step 804, when the level 2 VMCP 520 issues an SIE instruction while trying to activate the level 3 OS 530 on the VM of the level 2 VMCP 520, this SIE instruction has an instruction interception factor. Occurrence and control is returned to the Level 1 VMCP 510 from the Level 2 VMCP 520 on the VM of the Level 1 VMCP 510. At this time, the level 1 VMCP 510 is VMID
Is set to a binary number "1100" by a microprogram and travels.

Step 806: Level 1 VMCP51
0 analyzes the interception code which caused the control to be returned to the level 1 VMCP 510 from the level 2 VMCP 520 on the VM of the level 1 VMCP 510, and performs the interception process for each code. In this case, the interception code indicates instruction interception.

Step 807: The specific processing content of this processing is to carry out the processing corresponding to each interception code separately. For example, if the interception code indicates instruction interception, the instruction Perform a simulation. In this example, since the instruction interception occurred while trying to execute the SIE instruction, the simulation of the SIE instruction is performed.

Level 1 VMCP 510 is level 1 VM
As a pre-process for running the level 3 OS 530 on the VM of the CP 510, the L1SD prepared for starting the level 2 VMCP 520 and the L2SD prepared for starting the level 3 OS 530 are combined to generate the level 1 VM.
A provisional SD (hereinafter referred to as a shadow SD) for running the level 3 OS 530 on the VM of the CP 510 is initialized in a predetermined manner.

Step 808: Level 1 VMCP51
0 issues an SIE instruction using the shadow SD which is the operand of the SIE instruction initialized in step 807 as an operand, and activates the level 3 OS 530 on the VM of the level 1 VMCP 510. This activation is equivalent to activating the level 3 OS 530 on the VM of the level 2 VMCP 520. Control is level 1 from this point
Move from the VMCP 510 to the level 3 OS 530. At this time, the level 3 OS 530 sets the VMID to binary “11”.
11 ", the vehicle is set by the microprogram and travels.

Step 809: Level 2 VMCP52
The level 3 OS 530 runs on the VM of 0 and executes a predetermined process.

Step 810: Level 2 VMCP52
It is assumed that a level 2 address translation exception is detected by the MS access issued from the level 3 OS 530 while the level 3 OS 530 is executing processing on the VM of 0.

Step 811: In step 810, when the level 3 OS 530 on the VM of the level 2 VMCP 520 detects a level 2 address translation exception, this address translation exception has a host interrupt factor, so a program interrupt to the host occurs. , Control is level 2 VMC
Level 3 OS 530 on VM of P520 to level 1V
Returned to MCP510. At this time, level 1 VMCP
The 510 runs with the VMID set to a binary number “1100” by a microprogram.

Step 812: Level 1 VMCP51
0 analyzes the host program interrupt code that caused the control to be returned to the level 1 VMCP 510 from the level 3 OS 530 on the VM of the level 2 VMCP 520, and performs interrupt processing for each code. In this case, the host program interrupt code indicates a level 2 address translation exception.

Step 813: The specific processing content of this processing is to carry out the processing corresponding to each interrupt code separately. For example, if the interrupt code indicates a level 2 address translation exception, the level 2 VMCP 520 is processed. Notify an address translation exception. In this example, level 2 VMC
Since the level 3 OS 530 on the VM of P520 detected the level 2 address translation exception, the level 1 VMC
The P510 notifies the level 2 VMCP 520 of the address translation exception.

That is, the level 1 VMCP 510 notifies the level 2 VMCP 520 of the address translation exception, so that the level 2 VMC on the VM of the level 1 VMCP 510.
Level 2 VMC as pre-processing to run P520
L1SD prepared for starting P520 and shadow SD prepared for starting Level 3 OS 530
Are combined and L1SD for activating the level 2 VMCP 520 is initialized in a predetermined manner.

Step 814: Level 1 VMCP51
0 is SI with L1SD which is the operand of the SIE instruction initialized in step 813 as an operand.
Issue the E instruction to activate the level 2 VMCP 520 on the VM of the level 1 VMCP 510. Level 2 at this time
The interrupt parameter associated with the address translation exception is stored in advance in the PSA of the VMCP 520 by the level 1 VMCP 510. Further, the instruction address field of the interrupt PSW in the PSA of the level 2 VMCP 520 is stored in the instruction address field in the L1SD. Is stored. That is, the level 1 VMCP 510 is the same as the level 2 VMCP 52
Simulate an address translation exception interrupt for 0. From this point, control begins at level 1 VMCP510.
To Level 2 VMCP520. At this time, the level 2 VMCP 520 sets the VMID to binary “1110”.
And, it runs by being set by the micro program.

Step 815: Level 2 VMCP52
0 analyzes the interrupt code notified from the level 1 VMCP 510 and performs interrupt processing for each code. In this case, the interrupt code indicates an address translation exception interrupt.

Step 816: The specific processing content of this processing is to carry out the processing corresponding to each interrupt code separately. For example, if the interrupt code indicates an address conversion exception interrupt, the address conversion table Rewrite and maintain. In this example, since the address translation exception interrupt has occurred, maintenance of the address translation table is executed.

Step 817: Level 2 VMCP52
0 executes maintenance processing of the address conversion table. The level 2 VMCP 520 issues a PTLB instruction as part of the maintenance process of the address conversion table. At this time, as the value of VMID, V of binary “1110”
The MID entry is selected and sent out on signal line 780. At that time, the content of the signal line 780 changes to the comparator A75.
The VMID entry 712, which is input to each of A and the AND gate 750 and is temporarily held in the output register 730, is input to the AND gate 750.

The comparator A75A has the contents of the signal line 780,
That is, the binary number "1110" VMID data and A
The output of the ND gate 750 is compared, and the result is output to the signal line 7I0. This result controls whether or not to purge the TLB entry. That is, if the comparison result is a match, the selected TLB entry is invalidated. Also, if the comparison results do not match,
The TLB entry is not invalidated. in this case,
TLB entries having VMID entries of binary numbers “1110” and “1111” are targets for invalidation.

The above operation is repeated by the number of TLB entries, and the partial purging of the TLB for the two VMIDs is performed.

Step 818: Level 2 VMCP52
0 completes the processing of the level 2 address translation exception detected by the level 3 OS 530.
It is necessary to activate 30. So, level 2 VMCP
520 is level 3 on the VM of level 2 VMCP 520
As a pre-process for running the OS 530, the L2SD which is the operand of the SIE instruction is initialized in a predetermined manner.

Step 819: Level 2 VMCP52
0 is SI with L2SD which is the operand of the SIE instruction initialized in step 818 as the operand.
E command is issued to try to activate the level 3 OS 530 on the VM of the level 2 VMCP 520.

Step 820: In step 818, when the level 2 VMCP 520 issues an SIE instruction while trying to activate the level 3 OS 530 on the VM of the level 2 VMCP 520, this SIE instruction has an instruction interception factor. Occurring and control is returned from the level 2 VMCP 520 on the VM of the level 1 VMCP 510 to the level 1 VMCP 510. At this time, the level 1 VMCP 510 is the VMID.
The binary number "1100" is set by the microprogram and the vehicle runs.

Step 821: Level 1 VMCP51
0 analyzes the interception code which caused the control to be returned to the level 1 VMCP 510 from the level 2 VMCP 520 on the VM of the level 1 VMCP 510, and performs the interception process for each code. In this case, the interception code indicates instruction interception.

Step 822: The specific processing content of this processing is to perform the processing corresponding to each interception code separately. For example, if the interception code indicates instruction interception, this instruction Perform a simulation. In this example, since the instruction interception occurred while trying to execute the SIE instruction, the level 1 VMCP 510 simulates the SIE instruction. Level 1 VMCP510
Is a level 3 OS5 on a level 1 VMCP 510 VM.
Level 2 VMCP5 as pre-processing to run 30
L1SD and level 3O prepared to start 20
L2SD prepared for starting S530 is combined, and level 3 OS5 is executed on the VM of level 1 VMCP 510.
Initialize the shadow SD for running the 30 as specified.

Step 823: Level 1 VMCP51
0 issues an SIE instruction using the shadow SD that is the operand of the SIE instruction initialized in step 822 as an operand, and activates the level 3 OS 530 on the VM of the level 1 VMCP 510. This activation is equivalent to activating the level 3 OS 530 on the VM of the level 2 VMCP 520. Control is level 1 from this point
Move from the VMCP 510 to the level 3 OS 530. At this time, the level 3 OS 530 sets the VMID to binary “11”.
11 ", the vehicle is set by the microprogram and travels.

Step 824: Level 2 VMCP52
Level 3 OS 530 runs on 0 VM.

As described above, according to one embodiment of the present invention, when purging a TLB entry having a different VMID, when a simulation of an instruction that requires manipulation of the TLB entry is executed, for example, level 2 VMCP.
When executing the level 2 address translation exception processing on the 520, the level 1 VMCP 510 issues the SIE instruction using L1SD which is the operand of the SIE instruction as an operand, and the VM on the level 1 VMCP 510 outputs the level 2 VM.
When the CP 520 is started, the level 2 address translation exception is the level 3 OS5 on the VM of the level 2 VMCP 520.
Level 2 VMCP52 due to being detected on 30
0 starts the rewriting maintenance processing of the level 2 address conversion table, and when the PTLB instruction is issued there, the instruction interception is suppressed and the control is performed at the level 1 VMC.
Instead of returning from the level 2 VMCP 520 on the VM of P510 to the level 1 VMCP 510, it is executed as it is.

According to one embodiment of the present invention, this PTLB
In the execution of instructions, without interception,
The TLB entry of the own PIP having the VMID value corresponding to the VMID given to the level 2 VMCP 520 and the VMI corresponding to the VMID given to the level 3 OS 530
It is possible to partially purge the local PIP TLB entry having the value of D at the same time.

As a result, according to the embodiment of the present invention, the interception process of the PTLB instruction and the total T which are major factors that hinder the improvement of the performance of the virtual computer system.
It is possible to remove the overhead to the system caused by the decrease in the TLB usage efficiency due to the LB purging process, and it is possible to significantly improve the performance of the virtual computer system.

The above-described one embodiment of the present invention has been described by taking an example in which one CPU is used as the real CPU constituting the VM, but the present invention is a real CPU having a multiprocessor configuration.
It can also be applied to a virtual computer system that uses the. In this case, when the PTLB instruction issued by the level 2 VMCP 520 is executed, the L1SD in the L1SD is
Address, L2SD address and TSD entry of own PIP having VMID value corresponding to shadow SD address are partially purged, and further L1SD of all other PIPs
Purging TLB entries having VMID values corresponding to address, L2SD address and shadow SD address using the multiprocessor communication interface, and
This TLB entry purging operation may be performed in synchronization with the execution of the PTLB instruction.

The above-described embodiment of the present invention is based on the AN
Although the conversion example in which "0" is inserted into the lower 2 bits of the VMID entry data of the TLB entry by the D gate 750 has been shown, the present invention uses the AND gate 750 as a circuit configuration for inserting "0" into an arbitrary number of bits. Well, in addition,
The input from the AND gate 7B60 to the AND gate 7B63 is the OR gate 7B50 to the OR gate 7B5.
The output of 3 may be provided with a register that can be accessed by a microprogram regardless of the OR gate and its input connection.

[0165]

As described above, according to the present invention, the PTLB instruction can be directly executed on the level 2 OS when executing the instruction to purge the TLB issued by the level 2 OS. Like level 1
The TLB purge operation using the PTLB instruction for all the TLB entries performed by the OS can be eliminated, and the system overhead caused by the decrease in the TLB usage efficiency due to the TLB purge performed for all the TLB entries performed by the level 1 OS is removed. be able to.

As a result, according to the present invention, level 2O
It is possible to eliminate the processing time required for the operation by the level 1 OS, that is, the overhead required for the conventional technology such as the interception processing caused by the PTLB instruction issued on S, and to significantly improve the performance of the virtual computer system. Can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a TLB provided with a VMID used in an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed configuration of an AND gate configured in a TLB.

FIG. 3 is a diagram illustrating the operation of an AND gate.

FIG. 4 is a flowchart showing a processing procedure of an address translation buffer control system of the virtual computer system according to the present invention.

FIG. 5 is a flowchart showing a processing procedure of an address translation buffer control system of the virtual computer system according to the present invention.

FIG. 6 is a block diagram showing a configuration of a virtual computer system for explaining sharing of a real CPU with a VM according to a conventional technique.

FIG. 7 is a block diagram showing a configuration of another virtual computer system for explaining sharing of a real CPU with a VM according to a conventional technique.

FIG. 8 is a level 1 VMCP, a level 2 VM when the virtual computer system configured as shown in FIG. 7 operates.
7 is a flowchart showing a control flow of a CP and a guest OS of level 3.

FIG. 9 is a block diagram showing a configuration of a TLB provided with a VMID.

10 is an OS of each level in the system shown in FIG.
It is a figure explaining the area | region allocation of MS by the prior art with respect to (VMCP).

11 shows a control flow of the level 1 VMCP, level 2 VMCP, and level 3 guest OS when the virtual machine system configured as shown in FIG. 7 operates and when TLB purging is required. It is a flowchart.

FIG. 12 shows a flow of control of the level 1 VMCP, level 2 VMCP, and level 3 guest OS when the virtual computer system configured as shown in FIG. 7 operates and when TLB purging is required. It is a flowchart.

[Explanation of symbols]

101, 550 Main storage device 102 Real CPU 111 Virtual machine control program (VMCP) 121-123 Logical CPU 211, 510 Level 1 VMCP 221 Level 1 logical CPU 231, 520 Level 2 VMCP 241, 242 Level 2 logical CPU 251, 252, 530 Guest OS 410, 710 Address conversion buffer 420, 470, 720, 770 Selector 430, 730 Output register 440, 740 VMID register 450-452, 75A-75C Comparator 460, 750, 760, 7B60-7B63 AND
Gate 480, 780 Address conversion control unit 7B50 to 7B53 OR gate

Claims (3)

[Claims] 1. A central processing unit having an address translation function, a main memory unit, an address translation buffer having a virtual computer ID entry, and one or more virtual computers assigned to identify individual virtual computers. In a virtual computer system constructed on an information processing system configured with an address conversion function having a register for storing virtual computer IDs, allocation of virtual computer IDs for identifying the individual virtual computers is performed for each virtual computer. The virtual computer ID of the virtual computer is used as a value that reflects the cooperation of the operating systems operating on the computer, and when the instruction accompanying the purging of the address translation buffer issued by the virtual computer running on the central processing unit is executed. Address conversion with virtual machine ID entry matching with The buffer entry is selectively purged, and at the same time, the address translation buffer entry having the virtual computer ID entry of one or more other virtual computers having the virtual computer ID of the virtual computer is also purged. An address translation buffer control method for a virtual computer system characterized by the above. 2. The virtual computer system comprises a first-level operating system operating on a real computer,
The address translation table is created by itself to generate a virtual address space, the second level operating system as a virtual machine is operated on the virtual address space on the first level operating system, and the second level operating system Is configured to create an address translation table by itself to generate a virtual address space and to operate a third level operating system as a virtual machine on the virtual address space on the second level operating system. 2. The virtual machine system according to claim 1, wherein the value of the virtual machine ID assigned by reflecting the cooperation relationship of the systems is set to a value reflecting the cooperation of the upper and lower relationships of each level of the operating system. Address translation § control system. 3. A virtual computer I possessed by the other virtual computer
The operation of simultaneously purging the address translation buffer entry having the D entry is performed with a part or all of the value of the virtual machine ID of the virtual machine and a part or all of the value of the virtual machine ID entry of another virtual machine. 3. The address translation buffer control method for a virtual computer system according to claim 1, wherein the virtual computer ID entry of another virtual computer to be purged is determined from the above relationship.