JPH0535499A - Data processing device and method - Google Patents

Abstract

PURPOSE:To easily identify the presence or absence of the generation of a software interruption without executing twice the saving operation of an address concerned with a trap command, and the command code, and to reduce an inconsistency with a hardware break processing even at the time of executing the break processing by the software interruption, as for the improvement of a device which executes the software interruption especially during the execution of a program. CONSTITUTION:This device is provided with a command decoding part 11 which decodes a command CMD, command executing part 12 which executes an arithmetic operation based on the command CMD, and interruption control part 13 which controls the interruption requested during the execution of the command CMD And also the device is provided with a judging part 14 which judges control information TB indicating the 'truth' or 'false' of the interruption. Then, the control information TB is allocated to the specific bit of an (n) bit command code CDC decoded by the command decoding part 11.

Description

Detailed Description of the Invention

[Table of Contents] Industrial applications Conventional technology (Fig. 6) Problems to be Solved by the Invention Means for Solving the Problems (FIGS. 1 and 2) Action Example (FIGS. 3 to 5) The invention's effect

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device and a data processing method, and more specifically,
The present invention relates to an apparatus for executing a software interrupt during execution of a program and an improvement in the interrupt generation method.

In recent years, a data processor incorporating a software interrupt process by embedding a trap instruction of a microprocessor or the like as a breakpoint in a debug process during software development or a computer emulation (emulation) by hardware. It is used.

According to this, when executing the embedding process of the instruction code related to the trap instruction, which is a software interrupt, the instruction code of the address related to the trap instruction to be embedded is read, and then the address is read. And the instruction code are saved.

For this reason, the instruction code of the address must be stored together with the address that causes the software interrupt. Also, the instruction code must be a code of a completely different trap instruction in order to distinguish it from other codes. Furthermore, in the case where break processing is performed using the software interrupt of the emulator, the address in which the trap instruction is embedded is not immediately executed when the software interrupt occurs.

Therefore, there is a case where the presence or absence of a software interrupt is easily identified and the break processing is executed by the software interrupt without executing the save operation of the address related to the trap instruction and its instruction code twice. However, there is a demand for an apparatus and method that can eliminate the conflict with the hardware break processing.

[0007]

2. Description of the Related Art FIGS. 5 and 6 are explanatory views of a conventional example. 5A and 5B respectively show a block diagram of a data processing device according to a conventional example and an explanatory diagram at the time of interruption. For example, a microprocessor such as an emulator, in FIG. 5A, includes an instruction decoding unit 1, an instruction execution unit 2, an interrupt control unit 3, a memory unit 5, a data input / output unit 7, which are connected to an internal bus 6. The control unit 4 controls the timing of the above.

With respect to the function of the processor, when a certain command CMD is decoded by the command decoding unit 1, data is arithmetically executed by the command executing unit 2 based on the command CMD. In addition,
The calculation result data is transferred to the memory unit 5 and the data input / output unit 7. If an interrupt is requested during execution of the instruction CMD, the interrupt control unit 3 controls the interrupt.

FIG. 6 shows a processing flowchart at the time of interruption of the microprocessor according to the conventional example. For example, when a software interrupt process is performed by embedding a trap instruction for shifting from a main routine to a subroutine in a memory space as shown in FIG. 5B, first, in FIG. 6, an embedded address related to the trap instruction in step P1. Read the instruction code of.

Next, in step P2, a process of storing the embedded address related to the trap instruction is performed. At this time, the embedded address is saved in the debug monitor area of the memory space. Then, in step P3, the instruction code storage process for the trap instruction is performed. Also at this time, the instruction code is saved in the debug monitor area. Then, step P
In step 4, the software interrupt instruction is embedded.

As a result, the trap command embedding process is executed as a breakpoint in the debug process or emulation when developing software.

[0012]

By the way, according to the conventional software interrupt, when the instruction code embedding process relating to the trap instruction is executed as shown in FIG. 6, the trap instruction to be embedded in step P1 is executed. The instruction code of the address related to is read, and the address and the instruction code are saved in the stack pointer or the like in steps P2 and P3.

Therefore, the following problems occur. The instruction code at that address must be stored along with the address that caused the software interrupt. As a result, two data save areas are required for one trap instruction point in the debug monitor area of the memory space as shown in FIG. 5B.

The instruction code of the address which generates the software interrupt must be a code of a completely different trap instruction in order to distinguish it from other codes. As a result, processing operations such as reading, saving, and writing are required for each instruction code, and the procedure for rewriting the instruction code increases.

When a break process is performed using a software interrupt of the emulator, the address in which the trap instruction is embedded is not immediately executed when the software interrupt occurs.

As a result, in the hardware break processing using an external comparator or the like, a break occurs after the instruction at the address is executed, whereas in the break using the software interrupt, a break point is found at address 1003, for example. If set, a contradiction may occur in which a breakpoint occurs after execution of the instruction at address 1002 before execution of the address.

As a result, the speeding up of data processing is hindered and the memory area cannot be used efficiently. The present invention was created in view of the problems of the conventional example, and easily identifies the occurrence of a software interrupt without executing the save operation of the address related to the trap instruction and its instruction code twice. However, it is an object of the present invention to provide a data processing device and a data processing method capable of eliminating a contradiction with break processing related to hardware even when the break processing is executed by a software interrupt.

[0018]

[Means for Solving the Problems] FIGS.
3A and 3B respectively show principle diagrams of a data processing device and a data processing method according to the present invention.

As shown in FIG. 1A, the data processing apparatus of the present invention comprises an instruction decoding section 11 for decoding an instruction CMD, an instruction execution section 12 for executing an operation based on the instruction CMD,
An interrupt control unit 13 that controls an interrupt requested during execution of the command CMD, and a determination unit 14 that determines control information TB indicating “true” or “false” of the interrupt is provided. And

In the data processor, the control information TB is assigned to a specific bit of the n-bit instruction code CDC decoded by the instruction decoding unit 11.

The data processing method of the present invention is shown in FIG.
As shown in (b), the control information TB indicating the software interrupt "true" or "false" is set in all instruction codes CDC, and the software interrupt is generated based on the determination processing of the control information TB. It is characterized by generating.

In the data processing method, the software interrupt is generated after determining "true" or "false" of the control information TB set to the instruction code CDC as shown in FIG. 1 (c). The above object is achieved.

[0023]

[Operation] According to the data processing device of the present invention, FIG.
As shown in (a), the instruction decoding unit 11, the instruction execution unit 12,
The interrupt control unit 13 is provided, and the determination unit 14 that determines the control information TB indicating “true” or “false” of the interrupt is provided.

For example, when the instruction decoding unit 11 decodes the instruction CMD, an operation based on the instruction CMD is executed by the instruction execution unit 1.
2 is executed. At this time, a specific bit of the n-bit instruction code CDC decoded by the instruction decoding unit 11,
For example, control information TB is assigned to the least significant bit. Further, when an interrupt is requested during execution of the instruction CMD, the determining unit 14 determines the control information TB indicating “true” or “false” of the interrupt.

Therefore, for the occurrence or non-occurrence of the software interrupt, it suffices to focus only on the least significant 1 bit of the instruction code CDC. This makes it possible to easily identify whether or not a software interrupt has occurred. Further, it is not necessary to save the instruction code of the address together with the address which causes the software interrupt as in the conventional example.

As a result, it becomes possible to reduce the data area saved for the breakpoint of one trap instruction to one area. Therefore, the memory area of the data processing device can be efficiently used.

According to the data processing method of the present invention,
As shown in FIG. 1 (b), control information TB indicating "true" or "false" of the software interrupt for all instruction codes CDC
Is set, and a software interrupt is generated based on the determination process of the control information TB.

Therefore, unlike the conventional example, the instruction code of the address which causes the software interrupt is not embedded as the instruction code of the completely different trap instruction, and "true" and "false" are set in the control information. Only As a result, it becomes possible to easily rewrite the instruction code by executing a logical product operation (AND) instruction or a logical sum operation (OR) instruction.

As a result, operations such as reading, saving, and writing become unnecessary, and the procedure of rewriting the instruction code can be reduced. When the breakpoint setting process is performed using the software interrupt of the emulator, the address in which the trap instruction is embedded is executed when the software interrupt occurs. That is,
After determining "true" or "false" of the control information TB set in the least significant bit of the instruction code CDC as shown in FIG. 1C, the break processing is executed.

Therefore, as compared with the break processing related to the hardware using the external comparator, even in the case of the break processing using the software interrupt, it is executed after the execution of the address. It is possible to avoid the contradiction in data processing as in the conventional example. That is, in the break processing related to the hardware, for example, when a break point is set at the address 1003, even if the break processing using the software interrupt is performed, the address 1002 before the execution of the address as in the conventional example is executed. There is no contradiction that a breakpoint will occur after execution of the instruction.

As a result, it is possible to use the data processing related to the trap instruction together without distinguishing between hardware and software.

[0032]

Embodiments of the present invention will now be described with reference to the drawings. 2 to 4 are diagrams for explaining the data processing device and the data processing method according to the embodiment of the present invention, and FIG. 2A is a configuration diagram of the microprocessor according to the embodiment of the present invention. FIG. 2B shows a format example of the instruction code.

For example, a microprocessor applicable to an emulator or the like is shown in FIG.
An instruction decoding unit 11, an instruction execution unit 12, an interrupt control unit 13, a determination unit 14, a register group 15A and an I / O port unit 15B, and a timing generation / control unit 15C for timing control of these units. .

That is, the instruction decoding unit 11 registers the register 11A.
And an instruction decoding unit 11B for decoding the instruction CMD. The instruction execution unit 12 includes an accumulator 12A,
It is composed of a register 12B and an arithmetic operation unit (hereinafter simply referred to as ALU) 12C, and executes an operation based on an instruction CMD. The interrupt controller 13 controls the interrupt requested during the execution of the instruction CMD.

Up to now, the structure is similar to that of the conventional example,
The determination unit 14 is provided in the embodiment of the present invention. Judgment unit 1
Reference numeral 4 is composed of a register 14A and a judgment gate unit 14, and judges a trap bit which is an example of control information TB indicating "true" or "false" of an interrupt. Further, the trap bit TB is decoded by the instruction decoding unit 11, for example,
It is assigned to the least significant 1 bit of the 8-bit instruction code CDC (FIG. 2 (b)).

Table 1 shows a code A that does not generate a software interrupt and a code B that generates a software interrupt.

[0037]

[Table 1]

In Table 1, the code A that does not generate a software interrupt is "0" indicating "false" in the least significant bit of the instruction code CDC for each instruction (mnemonic).
Is written to the code B for generating a software interrupt, and "1" indicating "true" or "false" is written in the least significant bit of the instruction code CDC.

The register group 15A temporarily stores data DATA, instruction code CDC, etc., and the I / O port section 15
B inputs and outputs data DATA and address ADD. In addition, the timing generation / control unit 15C uses the signal output from the instruction decoding unit 11B and the reference clock CLK.
The timing of the instruction execution unit 12, the interrupt control unit 13, the determination unit 14, the register group 15A and the I / O port unit 15B is controlled based on the above.

In this way, the microprocessor according to the embodiment of the present invention is provided with the instruction decoding unit 11, the instruction execution unit 12, and the interrupt control unit 13 as shown in FIG. Or a trap bit T indicating "false"
A determination unit 14 that determines B = “1” or “0” is provided.

For example, when the command decoding unit 11 decodes the command CMD, the operation based on the command CMD is executed by the command execution unit 1.
2 is executed. At this time, the trap bit TB = “1” or “0” is assigned to the least significant 1 bit of the 8-bit instruction code CDC decoded by the instruction decoding unit 11. Also, if an interrupt is requested during execution of the instruction CMD, a trap bit T indicating "true" or "false" of the interrupt
The determination unit 14 determines B = “1” or “0”.

Therefore, it is sufficient to pay attention only to the least significant 1 bit of the instruction code CDC for the occurrence or non-occurrence of the software interrupt. This makes it possible to easily identify whether or not a software interrupt has occurred. Further, it is not necessary to save the instruction code CDC of the address together with the address for generating the software interrupt as in the conventional example.

As a result, the data area saved for the breakpoint of one trap instruction can be reduced to one area. Therefore, the memory area of the microprocessor can be used efficiently.

Next, a data processing method according to the embodiment of the present invention will be described while supplementing the operation of the microprocessor. FIG. 3 is a flowchart of data processing of the microprocessor according to the embodiment of the present invention.
Shows respective supplementary explanatory views thereof. For example, in the emulator, when the program debug process is executed by the instruction as shown in Table 2, the program read process is first performed in step P1 in FIG. Here, Table 2 shows an example of the instruction system of the microprocessor.

[0045]

[Table 2]

At this time, for example, address = “0000”,
By the operation instruction of instruction code CDC = “8000” (hereinafter referred to as MOV), the number # = “0” is read to the register, and the address = “0001”, “0002”, “0003”, “000” in order.
4 ”, instruction code CDC =“ 00 ”,“ B0 ”,“ 12 ”,“ 3 ”
The number # = “0” is stored at addresses 1 to 4 of the memory at “4” (see FIG. 4). The register of the instruction decoding unit 11
When the command CMD is input to 11A, the command CMD is decoded by the command decoding unit 11B. Further, the accumulator 12A, the register 12B and the ALU 12C of the instruction execution unit 12 execute the operation based on the instruction code CDC.

Then, in step P2, data write processing is performed. At this time, the number # = "0" written at addresses 2 to 4 of the memory is read. In addition, the register value is incremented when the address = “0005” (hereinafter, IN
C), and the program read and data read are repeated until the operation is finally completed (FF).

Therefore, when the data read / write is sequentially repeated to reach the program (interruption) process of step P3 from the program read process of step P3, the determination process of trap bit TB = "1" is executed in step P10. A software interrupt is generated based on
At this time, the software interrupt is generated after determining "1" of the trap bit TB set to the address 0011 and the instruction code CDC = OD2000 as shown in Table 2.
It should be noted that the register 14A and the judgment gate unit 14 of the judgment unit 14 judge the trap bit TB = “1” or “0” indicating “true” or “false” of the interrupt, and the interrupt control unit 13
Controls the interrupt requested during execution of the instruction CMD.

As a result, a software interrupt is generated, and instead of executing the original branch instruction (BRA), the address FF00 and instruction code CDC = 3000 are jumped to. Then, in step P11, a trap vector read process is performed. At this time, address = “FF01”, instruction code CDC =
At "00", the trap vector read processing for executing the trap instruction is performed.

Then, in step P12, stack pointer save processing is performed. Here, with the address = “8000” and the instruction code CDC = “2000”, the address related to the execution of the branch instruction (BRA) before the software interrupt is saved in the stack pointer.

Further, in step P13, program read processing relating to the trap instruction is performed. At this time, the address =
The program for executing the trap instruction is read with "3000" and the instruction code CDC = "00". For example, if the address = "3001", the instruction code = "00", the memory area 3001
The program data is stored in the address.

In step P14, a software interrupt recovery process is performed, and then in step P15, other processes are performed. Thus, according to the data processing method of the microprocessor according to the embodiment of the present invention, as shown in Table 1, all the instruction codes CDC are trap bits indicating "true" or "false" of the software interrupt. TB = “1” or “0” is set, and a software interrupt is generated based on the determination process of the trap bit TB = “1” as shown in the processing flowchart of FIG.

Therefore, unlike the conventional example, the instruction code CDC of the address which causes the software interrupt is not embedded in the data memory area as the instruction code CDC of the completely different trap instruction, and the trap bit TB is "true". , "1" or "0" indicating "false" is only set. As a result, the instruction code CDC can be easily rewritten by executing the AND instruction or the OR instruction.

This eliminates the need for processing operations such as reading, saving, writing, etc., and makes it possible to reduce the procedure for rewriting the instruction code CDC. When the breakpoint setting process is performed using the software interrupt of the emulator, the address in which the trap instruction is embedded is executed when the software interrupt occurs. That is, in the data read process of step P10 in the process flowchart of FIG. 3, the address = “0011”, as shown in FIG.
After determining "1" of the trap bit TB set to the least significant bit of the instruction code CDC = "0D", the break processing is executed.

Therefore, in comparison with the break processing related to the hardware using the external comparator or the like, even in the case of the break processing using the software interrupt, it is executed in step P11 after the execution of the address. Therefore, it becomes possible to avoid the contradiction in data processing as in the conventional example. That is, in the break processing related to the hardware, for example, when a break point is set at the address 1003, even if the break processing using the software interrupt is performed, the address 1002 before the execution of the address as in the conventional example is executed. There is no contradiction that a breakpoint will be set in.

As a result, it is possible to use the data processing relating to the trap instruction together without distinguishing between hardware and software.

[0057]

As described above, according to the data processing apparatus of the present invention, the instruction decoding unit, the instruction execution unit, and the interrupt control unit are provided, and the control information indicating the "true" or "false" of the interrupt is determined. A determination unit is provided.

For this reason, whether the software interrupt has occurred or not has to be focused on the control information of the n-bit instruction code decoded by the instruction decoding unit. This makes it possible to easily identify whether or not a software interrupt has occurred. Further, the data area saved for the breakpoint of one trap instruction can be reduced to one area.

According to the data processing method of the present invention,
The control information indicating "true" or "false" of the software interrupt is set for all the instruction codes, and the software interrupt is generated based on the control information determination process.

Therefore, it becomes possible to easily rewrite the instruction code of the address for generating the software interrupt as in the conventional example. This eliminates the need for processing operations such as reading, saving, and writing, and reduces the procedure for rewriting instructions.

Even when the breakpoint setting process is performed using the software interrupt of the emulator, it is determined whether the control information set in the least significant bit of the instruction code is "true" or "false". After that, the break processing is executed.

Therefore, it is possible to avoid the contradiction between the break processing related to hardware and the break processing related to software interrupt as in the conventional example. As a result, it is possible to use the data processing related to the trap instruction together without distinguishing between hardware and software.

This largely contributes to the provision of a data processing device such as a microprocessor for software development by debug processing or virtual calculation processing.

[Brief description of drawings]

FIG. 1 is a principle diagram of a data processing device and a data processing method according to the present invention.

FIG. 2 is a configuration diagram of a microprocessor according to an embodiment of the present invention.

FIG. 3 is a flowchart of data processing of the microprocessor according to the embodiment of the present invention.

FIG. 4 is a supplementary explanatory diagram of the flowchart according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a microprocessor according to a conventional example and an explanatory diagram of interrupt processing.

FIG. 6 is a flowchart of data processing at the time of interruption of the microprocessor according to the conventional example.

[Explanation of symbols]

11 ... Instruction decoding unit, 12 ... Instruction execution unit, 13 ... Interrupt control unit, 14 ... Judgment unit, TB ... control information, CMD ... command, CDC ... instruction code.

Claims (4)

[Claims] 1. An instruction decoding unit (1) for decoding an instruction (CMD).
1), an instruction execution unit (12) that executes an operation based on the instruction (CMD), and an interrupt control unit (13) that controls an interrupt requested during execution of the instruction (CMD). , Control information (T) indicating "true" or "false" of the interrupt.
A data processing device comprising a determination unit (14) for determining B). 2. The data processing device according to claim 1, wherein the control information (TB) is assigned to a specific bit of an n-bit instruction code (CDC) decoded by an instruction decoding unit (11). Characteristic data processing device. 3. A control information (TB) setting process that indicates “true” or “false” of a software interrupt is set for all instruction codes (CDC), and software is executed based on the determination process of the control information (TB). A data processing method characterized by generating a wear interrupt. 4. The data processing method according to claim 3, wherein the software interrupt is generated after determining “true” or “false” of the control information (TB) set and processed in the instruction code (CDC). A data processing method characterized by the above.