JPH0954694A - Pipeline processor and its processing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the performance of a CISC type processor for pipeline control by providing a means which efficiently detects a hazard accompanying the execution of a read-modify-write instruction. SOLUTION: This processor is equipped with an L flag which can be set or reset for every entry into a cache memory. This process includes a step S14 for setting the L flag in a cache read stage 114 wherein an RMW instruction is being executed and a step S17 for resetting the L flag after data writing is completed in a cache write stage 115.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pipeline processor and its processing method, and more particularly to a CISC type pipeline processor for performing a read modify write process and its processing method.

[0002]

2. Description of the Related Art A CISC type pipeline processor of this type divides an instruction interpretation / execution into a plurality of procedures (hereinafter referred to as stages), and executes those stages in parallel to obtain a plurality of instructions. It realizes the simultaneous execution of.
In the following description, for convenience of explanation, it is assumed that all data in the access target memory are copied in the cache memory (hereinafter referred to as cache).

FIG. 4 showing an example of a program for explaining the operation of a general pipeline processor and the configuration of the pipeline stage of each instruction of this program.
Referring to (A) to (C), the program shown in (A) is composed of instructions 11 and 12, and the instruction 11 (INC [12
34]) adds 1 to the contents of the address 1234 of the memory, and writes the addition result back to the original address 1234 again.
MW) command. Command 12 (MOV A, [123
4]) is a move (MV) instruction for reading the contents of the address 1234 of the memory and writing the contents in the register A of the processor. If the numerical value 100 is written in advance at the address 1234 of the memory, the content of the address 1234 of the memory is changed to 101 by the execution of the instruction 11.
Next, when the instruction 12 is executed, the numerical value 101 read from the address 1234 of the memory is written in the register A.

Referring to FIG. 4B showing the operation timing of the instruction 11 (INC [1234]), the passage of time shown in this figure is from left to right, and this instruction 11 is not interpreted or executed. Opcord etch stage 111
, A decode stage 112, a cache read stage 113, a calculation stage 114, and a cache write stage 115. The processor executes each stage 111-115 from left to right.

Explaining the execution of the instruction 11 along each stage with reference to FIG. 4 (B), first, the processor executes the instruction 11 from the memory at the opcode etch stage 111.
Read the machine language of. However, the processor does not know that the read machine language is the instruction 11 at this stage. In the next decoding stage 112, the previously read machine language is decoded, and the processor recognizes that it is the instruction 11, that is, the operation to be executed. At the next cache read stage 113, the data existing in the cache memory is read, and the temporary work register tm in the processor is read.
p (not shown). Next calculation stage 114
Then, 1 is added to the contents of the register tmp. At the next cache write stage 115, the contents of the register tmp are written back to the original address.

Referring to FIG. 4C showing the operation timing of the instruction 12 (MOV A, [1234]), the instruction 12 shown in this figure is interpreted and executed by the opcode etch stage 121 and the decode stage 122. , Cache read stage 123 and operation stage 124 are divided into four stages.

Explaining the execution of the instruction 12 along each stage with reference to FIG. 4C, the operation up to the opcode etch stage 121 and the decode stage 122 is the same as the instruction 11. At the next cache read stage 123, the data at the specified address is loaded from the cache memory into the work register tmp. In the next arithmetic stage 124, the value is copied from register tmp to register A.

When the program including the RMW instruction of FIG. 4A described above is simply pipelined,
The timing is as shown in FIG. However, at this timing, the operation stage 114 of the RMW instruction 11 and the cache read stage 123 of the next MV instruction 12 are simultaneously executed, and 1234 before updating by the first instruction 11 is performed.
Since the contents of the address are read, an incorrect result, that is, a hazard is generated. That is, if it is executed at this timing, the content of the register A becomes 100.

In the conventional pipeline processor, in order to avoid such a hazard, the RMW of FIG.
A program including an instruction and an MV instruction is executed at the timing when stop stages 126 and 127 are inserted between the decode stage 122 and the cache read stage 123 as shown in FIG. 5B. In this case, the first RM
After the execution of the cache write stage 115 of the W instruction 11 is completed, the cache read stage 123 of the MV instruction 12 is executed. In this case, the execution of the instruction 12 is stopped for two stages.

The conventional pipeline processor processing method is not limited to the case where the same address is accessed as in the first RMW instruction 11 and the second MV instruction 12 in this example, but in both the RMW instruction and the MV instruction. Even when accessing different addresses, the processing is executed at the timing shown in FIG. 5B having two stop stages. Generally, when encountering a program code of a sequence for executing an MV instruction following an RMW instruction as shown in FIG. 4A, it is considered that the addresses of the RMW instruction and the MV instruction are often different from each other. To be When the addresses of the both are different, the execution result is normal even if the execution is performed at the timing of FIG. 5A that does not include the stop stage.

Therefore, in the conventional processor which always executes at the timing including the two stop stages, the RMW is
In a program code of a sequence that executes an MV instruction subsequent to an instruction, in many cases that does not include access to the same address of both instructions, the number of stages required for instruction execution, that is, the number of clocks, is unnecessarily increased, which causes a performance deterioration There is.

With reference to FIG. 6 showing an example of an entry of a cache used in a conventional pipeline processor in relation to the above processing, the cache entry of this conventional processor is stored in the entry. Data 201, the address 202 of the (main) memory of the copy source, and information necessary for controlling the cache operation. In this example, the contents recorded in the address part, the data part, and the entry are valid. It consisted of V-bit 203 indicating invalidity.

[0013]

The above-described conventional pipeline processor and its processing method stochastically execute another instruction such as a move (MV) instruction following a read-modify-write (RMW) instruction. Is a very small special case. In order to prevent hazards caused by accessing the same address of the RMW instruction and other processing instructions, the R
Since the execution of the instructions of the above-mentioned other processes is stopped from the end of the cache read stage of the MW instruction to the end of the cache write stage, there is a drawback that the number of execution stages of both these instructions, that is, the number of clocks, increases and causes a performance deterioration. It was

An object of the present invention is to provide a processing method of a pipeline processor that efficiently detects the above special case and reduces the number of instruction execution clocks to improve the performance of the processor.

[0015]

A pipeline processor according to the present invention reads data from an arbitrary address in a memory, performs a predetermined arithmetic processing on the read data, and writes the processed data to the address. A read-modify-write processing unit that executes the modify-write processing with a single read-modify-write instruction, and a cache memory for buffering the memory are provided, and one processing is divided into a plurality of processing stages and each stage is parallelized. In a pipeline processor that executes processing, a flag that can be set / reset for each entry of the cache memory is provided, and when reading data from the cache memory during execution of the read modify write instruction, the flag corresponding to this data is set. Flag setting means to set, and It is constituted by a flag resetting means for resetting said flag after completion of data writing to the cache memory.

According to the processing method of the pipeline processor of the present invention, data is read from an arbitrary address in the memory via the cache memory, a predetermined arithmetic processing is performed on the read data, and the data after this processing is written to the address. The read-modify-write processing is executed by the first instruction, which is a single read-modify-write instruction, and the read-modify-write processing is performed by the first, second, and third operations corresponding to the reading, operation, and writing of the data. In a processing method of a pipeline processor that is divided into a plurality of processing stages including a processing stage and executes processing in parallel for each stage, a settable / resettable flag is arranged for each entry of the cache memory, 1
Processing step of accessing the entry of the cache memory to read the flag, checking the set state of the flag, reading the data from the cache memory, Setting a flag, the third processing stage including the step of writing the data to the cache memory and the step of resetting the flag of the cache memory. .

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION Next, an entry of a cache memory (hereinafter referred to as a cache) of a pipeline processor which characterizes the embodiment of the present invention is the same as that shown in FIG. Referring to FIG. 2 schematically showing, in addition to the data 201, the address 202, and the V bit 203 which are common to the conventional cache entry of the pipeline processor of this embodiment, a read modify write (RMW) is added. An L flag 204 for displaying during access is added in the process of executing an instruction.

Further, in the present embodiment, for convenience of explanation, it is assumed that the program and the constituent stage of each instruction of this program are shown in FIGS. That is, the program is RMW instruction 11 (INC
[1234]) and MV instruction 12 (MOV A, [12
34]), the instruction 11 is divided into five stages: an opcode etch stage 111, a decode stage 112, a cache read stage 113, a calculation stage 114, and a cache write stage 115. The instruction 12 is divided into four stages, an opcode etch stage 121, a decode stage 122, a cache read stage 123, and a calculation stage 124.

Next, referring to FIG. 1A which is a flow chart showing the execution procedure of the RMW instruction 11 common to the conventional pipeline processor of this embodiment, referring to FIG. 1A, the pipeline processor of this embodiment shown in FIG. RMW instruction 1
In the execution procedure of No. 1, the cache read stage 113 accesses the cache (step S11) and the L flag 204.
Set confirmation (step S12), data read (step S13), and L flag 204 set (step S1)
4) is executed by the arithmetic stage 114 (step S1).
5), the cache write stage 115 writes the data to the cache (step S16) and the L flag 204.
Resetting (step S17) is included.

Next, the processing of the pipeline processor of the present embodiment will be described with reference to FIG.
First, in the cache read stage 113, the L flag 204 of the cache memory is read (step S11).
Then, the presence or absence of the set of 1 is checked (step S1)
2). When 1 is set, L flag 204 is set again
Read (step S11) / judgment (step S12)
I do. As long as the L flag 204 is in the set (1) state, the cache read stage 113 is never finished. In the reset (0) state, the data is read from the cache (step S13) and transferred to the tmp register. After that, the L flag 204 of the cache is set to 1 (step S14), and the execution of the cache read stage 113 is completed. In the next arithmetic stage 114, 1 is added to the tmp register (step S15).
Only the operation of the conventional processor is the same. In the final cache write stage 115, data is first written in the cache (step S16). Next, the L flag 204 in the cache is reset to 0 (step S
17).

Next, referring to FIG. 1B which is a flowchart showing the execution procedure of the MV instruction 12 of the pipeline processor of the present embodiment, the execution procedure of the MV instruction 12 shown in this figure is the cache read stage 123. Includes cache access (step S21), confirmation of setting of the L flag 204 (step S22) and data read (step S23), and the operation stage 124 includes operation execution (step S24).

Next, the processing of the pipeline processor of the present embodiment will be described with reference to FIG.
First, in the cache read stage 123, the L flag 204 of the cache is read (step S21), 1
It is checked whether or not there is a set (step S22). 1
If is set, the L flag 204 is read again (step S21) and determined (step S22).
As long as the L flag 204 is in the set (1) state, the cache read stage 123 is never finished. In the reset (0) state, the data is read from the cache (step S23), transferred to the tmp register, and the execution of the cache read stage 123 ends. In the next arithmetic stage 124, the data is transferred from the tmp register to the A register (step S24), and the arithmetic stage 12
4 is ended.

Next, the hazard detection and its processing procedure in the processing method of the pipeline processor of the present embodiment will be described. As described in the above-mentioned conventional technique, the RMW instruction 11 and the MV instruction 12 following the RMW instruction 11 are described. In the program shown in FIG.
When the access target addresses of the instruction 11 and the MV instruction 12 are different, the conventional ideal operation timing is shown in FIG.
There is no problem even if the processing is executed at the timing of (A).

On the other hand, referring to FIG. 3 showing the execution timing when the access target addresses of the RMW instruction 11 and the MV instruction 12 are the same, as described above, the RMW instruction 11
Sets the L flag 204 of the corresponding entry to 1 in the cache read stage 113. The next operation stage 114 is the cache read stage 1 of the MV instruction 12.
It is executed in parallel with 23. However, the L flag 204 read by the cache read stage 123 is set to 1. Therefore, the MV instruction 11 cannot complete the cache read stage 123 and cannot proceed to the next operation stage 124. The L flag 204
Is reset to 0 for the first time in the cache write stage 115 of the RMW instruction 11, so the reset state of the L flag 204 is confirmed in the cache read stage 123 of the MV instruction 12 and the data can be read by the RM.
This is after the execution of the W instruction 11 is completed. Therefore,
The processor can execute the above program normally.

As described above, at the cache read stage, the hazard can be detected efficiently by checking the value of the L flag 204 in the cache entry.

[0026]

As described above, the pipeline processor and the processing method thereof according to the present invention are provided with a flag that can be set / reset for each entry of the cache memory, and can cope with data read during execution of a read modify write instruction. By checking the value of this flag by setting the above flag and resetting the above flag after the completion of data writing, the hazards caused by the same address access can be detected efficiently, so it occupies most of the processing. There is an effect that it is possible to speed up the processing of the different address access that does not cause a hazard.

[Brief description of drawings]

FIG. 1 is a flowchart showing a processing method of a pipeline processor according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram schematically showing a configuration of an entry of a cache memory which is a feature of this embodiment.

FIG. 3 is a time chart showing execution timings when the RMW instruction and the MV instruction of the present embodiment have the same access target address.

FIG. 4 is a diagram showing an example of a program for explaining the operation of a general pipeline processor and a configuration of a pipeline stage corresponding to each instruction of the program.

FIG. 5 is a time chart showing an example of execution timing of a conventional pipeline processor.

FIG. 6 is an explanatory diagram schematically showing a configuration of an entry of a cache memory of a conventional pipeline processor.

[Explanation of symbols]

 11 RMW instruction 12 MV instruction 111,121 Opcode etch stage 112,122 Decode stage 113,123 Cache read stage 114,124 Operation stage 115 Cache write stage 201 Address 202 Data 203 V bit 204 L flag

Claims (2)

[Claims] 1. A read-modify-write process for reading data from an arbitrary address in a memory and performing a predetermined arithmetic process on the read-out data and writing the processed data to the address with a single read-modify-write instruction. A read-modify-write processing unit that executes the data and a cache memory for buffering the memory are provided.
In a pipeline processor that divides one process into a plurality of processing stages and executes the processes in parallel for each stage, a flag that can be set / reset for each entry of the cache memory is provided, and the read-modify-write instruction is being executed. A flag setting means for setting the flag corresponding to the data at the time of reading data from the cache memory, and a flag reset means for resetting the flag after the writing of the data to the cache memory is completed. Pipeline processor. 2. A read-modify-write process in which data is read from an arbitrary address in the memory via a cache memory, a predetermined operation process is performed on the read data, and the processed data is written to the address in a single read. The read-modify-write processing is executed by the first instruction which is a modify write instruction, and the read-modify-write processing is performed for the first, second, and third data corresponding to the read, operation, and write of the data.
In a processing method of a pipeline processor that divides into a plurality of processing stages including a processing stage and executes processing in parallel for each stage, a settable / resettable flag is arranged for each entry of the cache memory, The first processing stage accesses the cache memory entry to read the flag; checks the set state of the flag; reading the data from the cache memory; Setting the flag, the third processing stage including writing the data in the cache memory and resetting the flag in the cache memory. Processor processing method.