JP3497087B2 - Instruction control apparatus and method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an instruction control device and a method thereof, and more particularly to an instruction control device and a method thereof that enable out-of-order instruction execution for high-speed instruction processing in an information processing device.

Here, out-of-order instruction execution (out-of-o)
rder) is a process that is executed at any time from an instruction with input data in a different order from the instruction order instructed by the program. Instruction execution can be in any order,
Resources accessible to the program, namely storage,
The instruction is executed as if the register contents were updated and referenced in the program order.

[0003]

2. Description of the Related Art In an information processing apparatus capable of executing out-of-order instructions in order to execute instruction processing at high speed, after the instruction decoding cycle, the information is stored in a decoded instruction storage means called a reservation station. Multiple decoded instructions are stored. Then, regardless of their decoding order, the decoded instruction whose source operand is usable is selected and the instruction is issued from the reservation station to the arithmetic unit.

Further, in order to execute out-of-order instruction execution at high speed and efficiently, a register renaming technique for ensuring that the register contents are updated and referred to in the program order is used. The register renaming technology renames logical registers used in instructions and allocates them to different physical registers or memories, and when the use of the same register by multiple instructions conflicts with each other, the processing can be performed independently. It is a technology that enables them to be executed in parallel. It is efficient hardware as a mechanism for operating simple instructions at high speed.

FIG. 1 shows an example of a conventional register renaming technique. In FIG. 1, when the instruction fetched into the instruction register 10 through an instruction cache (not shown) is an instruction to update the contents of the logical register R, the register update buffer (RU) is used instead of the logical register R.
B: Register Update Buffer) 14 is allocated.
For the allocation, the update buffer address table and the register update pending table 11 are indexed based on the logical register address on the instruction register 10.

In the former update buffer address table, each general-purpose register (GPR: General Purpose Register) is used.
The address of the register update buffer 14 corresponding to
The latter register update pending table 11 stores register update pending bits for instructing either use of a general-purpose register or use of an allocated register update buffer. As a result of the index, the address of the update buffer corresponding to the logical register R and its update pending instruction are read out and registered in the reservation station 12 of the next stage.

In the reservation station 12, the general purpose register (GP) is used as an operand to be used in the operation according to the update suspension instruction when the instruction is issued to the arithmetic unit 15.
R) 13 or register update buffer (RUB) 14 is designated.

FIG. 2 shows a reservation station 12
3 shows an example of the configuration of the operand part of the. In FIG. 2, each of the entries 1 to 3 of the reservation station 12 stores an instruction issued to the arithmetic unit 15. The first operand of entry 1 is composed of an update suspension instruction (P1), a register address (RA1) and an update buffer address (UBA1), and the second operand is also composed of P2, RA2 and UBA2. Where P
If 1 is on (= 1), RA1 is read, and if P1 is off (= 0), UBA1 is read.

[0009]

On the other hand, it is necessary to ensure that not only the registers but also the memory contents are updated and referenced in program order. Therefore, in the prior art, there is a problem that fetch access to the cache memory is waited until data is stored in the cache memory, and as a result, the calculation performance is deteriorated.

For example, FIG. 3 shows an example of a conventional instruction operation time chart. FIG. 3A shows an example of a register-register instruction, and FIG. 3B shows an example of a register-memory instruction. Here, the D cycle is an instruction decode cycle, the P cycle is a register read cycle, the X cycle is an operation execution cycle, and the W cycle is a store cycle.

Instruction 1 in FIG. 3A is a register storage instruction, and the operation result is stored in the update buffer in W cycles. Next, in the register read instruction of the instruction 2,
As indicated by a dotted arrow in (a) of FIG.
Is read by. As described above, in the register-register instruction, even if the update register and the read register interfere with each other, the pipeline arithmetic processing is not delayed.

On the other hand, the instruction 1 in FIG. 3B is a memory storage instruction. In the W cycle, data is stored in the store buffer. The address of the cache ram is set in the subsequent A cycle, and the data is written in the cache ram in the next B cycle. In the memory read instruction of the instruction 2, the source data must be fetched from the memory address stored in the instruction 1. Therefore, as compared with the register-register instruction of FIG. I need more.

Therefore, in view of the above problem, an object of the present invention is that even in a register-memory instruction, a subsequent instruction does not wait until the preceding instruction stores data in the cache memory, and the subsequent instruction transfers the data to the data. It is an object of the present invention to provide an instruction control device and its method in which the operation performance can be greatly improved by providing a means for immediately executing the fetch access. It is another object of the present invention to provide an instruction control device and a method thereof in which a succeeding instruction can immediately fetch access to data by a forwarding process also in a memory-memory instruction.

[0014]

According to the present invention, a plurality of register update buffers for temporarily storing a result of instruction execution and updating a general-purpose register when the instruction execution is completed, and a designated general-purpose register are updated. An update buffer address table indicating which register update buffer the data is stored in, a register update pending table indicating that a specified general-purpose register is pending update, a general-purpose register address, and the above-mentioned general register corresponding to the general-purpose register. A register update buffer address output from the update buffer address table, and a reservation station for storing an update suspension instruction of the general-purpose register;
If the update suspension instruction is off, the instruction control method in the information processing device using the designated general-purpose register as the source data is targeted.

According to the present invention, at the time of executing an instruction that requires fetch data from the memory as the source data of the operation, if the memory area is not stored in the preceding instruction, the fetch data is updated in the register. If you store it in a buffer and use it, or if the memory area is stored in the preceding instruction and the storage destination address is the same as the fetch destination address of the fetch data, the reservation station that holds the preceding instruction Copy the update pending instruction for designating the storage register, the register update buffer address, and the general-purpose register buffer address to the fetch data specification information area of the reservation station in which the operation instruction is held, and the operation instruction is fetched from the memory. Preceded by data instead of That stores the use of storage register specified in the instruction, the instruction control method comprising is provided.

Further, according to the present invention, at the time of executing an instruction which requires fetch data from the memory as the source data of the operation and updates the general-purpose register with the operation result,
The fetch data is temporarily stored in a register update buffer allocated for general-purpose register update and used as source data, and the operation result is stored again in the register update buffer. When copying the register update buffer address for specifying the storage register from the reservation station holding the preceding instruction to the fetch data specification information area of the reservation station holding the operation instruction because the fetch destination addresses of In addition, the update buffer address assigned to the operation instruction is separately held, and the update buffer is prevented from being updated with fetch data after the operation result is stored in the update buffer based on the copy information. thing,
including.

Further in accordance with the invention, the preceding instruction is
An instruction that calculates memory data and memory data and stores it in the memory. When the instruction that fetches fetch data from the storage address of the preceding instruction is executed, the succeeding instruction is stored in the reservation station. Suppressing the reset of the update pending instruction to be performed, and by suppressing the reset, even if the preceding memory storage instruction does not use the general-purpose register, the subsequent operation instruction is specified in the preceding storage instruction instead of the fetched data. Using a registered update buffer.

Further, according to the present invention, the preceding instruction is an instruction for operating the memory data and the memory data and storing it in the memory, and the instruction fetching the fetched data from the storage destination address of the instruction preceding the succeeding instruction. At the time of execution of, the update buffer for temporarily holding the data to be stored in the memory is provided separately from the update buffer for updating the general-purpose register, and the subsequent operation instruction uses the preceding store instruction instead of the fetched data. Using the specified register update buffer.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 4 shows an example of the basic configuration of an instruction control device according to the present invention. FIG. 5 is an operation flow diagram of the instruction control device of FIG. In FIG. 4, portions different from the conventional example of FIG. 1 are indicated by thick lines. Here, the operation of the instruction control device according to the present invention will be described centering on the thick line portion. In addition, step numbers in FIG. 5 are attached to corresponding portions in the description.

When the memory storage instruction (store instruction) is decoded in the instruction register 10 (S101), the memory address portion A of the data storage destination is stored in the memory storage address holding means 20. Further, the update buffer address table and the register update pending table 11 are indexed from the address of the logical register R of the data storage source for register renaming, and the corresponding update pending instruction (P
1), the general-purpose register address (RA1) and the update buffer address (UBA1) are stored in the reservation station 12. At the same time, the P1, RA1 and UBA1 are also stored in the temporary storage means 22 (S10).
2).

Next, in the instruction register 10, a subsequent memory operation instruction (for example, memory-register addition instruction)
Is decoded (S103), the memory address of the memory address portion is stored in the memory storage address holding means 20.
Is compared by the comparator 21 with the memory address A which is stored in the memory. When they match, the comparator 21 outputs a match signal (S104).

By the output of the coincidence signal, the corresponding operand in the memory operation instruction entry on the reservation station 12 is replaced with the update buffer address for storing the data fetched from the corresponding memory address by the subsequent memory operation instruction, instead of the update buffer address. Contents stored in the temporary storage means 22 (P1, RA1 and UBA1)
Is copied (). At the same time, the storage destination update buffer address is sent to and held in the update buffer address holding means 23. Update buffer address holding means 2
From 3, a control signal for controlling fetch data not to update the update buffer is generated (S105). The details of the operation of the update buffer address holding means 23 will be described later.

According to the above-described structure of the present invention, the contents of the general-purpose register (that is, the corresponding update buffer) for holding the source data to be stored at the predetermined memory address in the store instruction which is the preceding instruction are the contents of the subsequent memory operation instruction. Is used instead of fetch access to the contents of the same memory address. As a result, according to the present invention, what is originally a register-memory instruction is replaced with a register-register instruction, and a high-speed pipeline operation utilizing the register-forwarding processing as shown in FIG. Is possible.

FIG. 6 and subsequent figures show an embodiment of the present invention. FIG. 6 shows an example of a first instruction control operation (register-memory instruction) according to the present invention.
6B shows an operation example according to the present invention, while FIG. 6A shows a conventional example which performs the same operation for comparison with the present invention. In FIG. 6, the load instruction (L
5, A), the contents of memory address A are loaded into general register 5. Subsequent store instruction (ST 5,
In B), the contents of general register 5 are stored at memory address B. Finally, the contents of the general-purpose register 6 and the contents of the memory address B are added by an addition instruction (A 6, B), and the result is written in the same general-purpose register 6.

In the conventional example of FIG. 6A, the fetched data cannot be fetched from the memory by the subsequent instructions only after timing 6 when the result of the store instruction is reflected in the memory, while in FIG. In (), the operation result of the store instruction can be used immediately after the forwarding processing.

FIGS. 7 to 9 show changes in the contents of each register in the operation according to the present invention shown in FIG. 6B according to the instruction cycle sequence. FIG. 7 shows an example of setting data at the timing 1 of FIG. At the timing 1, the update buffer address table and the register update pending table 11 are updated by the load instruction (L 5, A). In this example, the update buffer 1 (P = 1, UBA = 1) for holding the contents fetched from the memory address A and updating the general-purpose register 5 (GR5)
Is assigned.

At timing 2 in FIG. 8, the store instruction (S
The memory address B of T 5, B) is stored in the memory storage address holding means 20. At the same time, the update buffer address table and the register update pending table 11 are indexed on the basis of the general-purpose register address 5 of the store instruction, and GR5 (UBA = UBA =
1, P = 1) is stored in the store instruction entry and temporary storage means 22 of the reservation station 12.

Further, the addition instruction (A
In the D cycle in 6, B), the comparator 21 compares the memory address B on the instruction register 10 with the memory address B stored in the memory storage address holding means 20. In this example, the comparison results match and a match signal is output.

At timing 3 in FIG. 9, the contents of the temporary storage means 22 (GR5; UB
A = 1, P = 1) is copied to the area indicating the fetch data storage destination of the addition instruction entry of the reservation station 12. As a result, the contents of the update buffer 1 (when P = 1) holding the operation result of the preceding store instruction are forwarded, and the subsequent add instruction is immediately executed. As described above, in the present embodiment, the add instruction is the general-purpose register 5 or L instead of the fetch data from the memory.
Since the register update buffer 1 holding the result of the instruction is used as the source data, the subsequent instruction can start the operation using the data faster than the preceding store instruction stores the data in the memory.

Incidentally, FIG. 10 shows an example of an addition instruction entry of the reservation station 12 in the conventional example of FIG. As shown in FIG. 10, at timing 3, the forwarding processing according to the present invention described above is not executed, and the add instruction update buffer (UBA2)
Is designated an update buffer address (in this example, UBA2 = 2) for storing the data fetched from the memory address B. Therefore, the subsequent addition operation is started when the storage in the memory by the preceding store instruction is completed.

By the way, FIG. 11 shows an example in which the fetch data from the memory in the preceding add instruction lags behind the fetch data in the subsequent add instruction.
Each of the addition instructions in FIG. 11 adds fetch data from the memory to the general-purpose register GR5, and the result is GR5.
Is to be updated.

FIG. 12 shows an example of the reservation station 12 extended to cope with the above case. In FIG. 12, an update buffer address (DUBA: which holds the result of newly updating the general-purpose register).
Destination Update Buffer Address) is provided. This will be described with reference to the register contents shown in FIGS. 13 and 14 using the example of FIG.

As shown in FIG. 13, at the timing 1 of FIG. 11, the update buffer address table and the register update pending table 1 are based on the decoding result of the preceding add instruction.
1 is indexed and the update buffer 1 (RUB1) corresponding to the general-purpose register 5 (GR5) is acquired. Also, the update buffer 1 is added to the DUBA that holds the update result of the general-purpose register 5.
Is assigned.

On the other hand, as shown in FIG. 14, at timing 2 in FIG. 11, the update buffer address table and the register update pending table 11 are indexed based on the decoding result of the subsequent add instruction, and the same general register 5 (GR5) is next stored. Update buffer 2 is allocated. Further, the update buffer 2 is also assigned to the DUBA as in the above.

Here, in consideration of the case where the fetch data of the preceding instruction lags behind the fetch data of the following instruction,
The fetch data from the memory is temporarily stored in the update buffer 2 designated by the DUBA. As for the instruction, when the data for the general-purpose register is prepared, the data in the general-purpose register and the update buffer are given to the arithmetic unit.

Next, after waiting for the operation result of the preceding add instruction to be output to the update buffer 1 designated by the DUBA (P1 = 1, UBA1 = 1), the forwarding processing is performed and the subsequent operation is performed. Be started. The operation result is stored in the update buffer 2 designated by DUBA, and written in the general-purpose register 5 in the next W cycle.

However, when the fetch operation from the same memory address is executed after the store instruction which is the first instruction control operation of the present invention in the machine for performing the above-mentioned arithmetic operation, the arithmetic result from the arithmetic unit and the fetch from the memory There is a case where the data and the data are simultaneously written in the same update buffer.

FIG. 15 shows an example thereof.
In FIG. 15, an addition instruction (A using the forwarding processing (store fetch forwarding) according to the present invention is used.
6, B) updates its operation result in X cycle in buffer 2
When writing to (RUB2), the fetch data is written to the same update buffer 2 (RUB2) in the B cycle of the subsequent memory operation instruction at the same time.

As is apparent from the example of FIG. 10, the update buffer 2 (RUB2) is assigned to the DUBA of the normal add instruction that does not perform store fetch forwarding. Therefore, the operation result of the addition instruction after the copy process of FIG. 9 is temporarily written in the update buffer 2 (operation unit → R
UB2). On the other hand, as shown in parentheses in FIG. 15, a B cycle (fetch data → RUB
2) coincides with the X cycle during store fetch forwarding processing.

As a result, two write processes occur simultaneously in the same update buffer (RUB2 in this example) only when the store fetch forwarding process according to the present invention is executed. FIG. 16 is an operation explanatory diagram of the update buffer address holding means 23 for preventing the two simultaneous writing.

FIG. 16A shows a general configuration example in which either the data of the arithmetic unit 15 or the data cache 24 is selected and stored in the update buffer X (RUBX: X = 0 to n) 14. It is a thing. In FIG. 15, the calculation result of the add instruction or the memory fetch data is the update buffer 2
Written in.

FIG. 16 (b) shows an example of the structure of the update buffer address holding means 23. As described above, the contents of the DUBA of the add instruction are held in the buffer 31 at the timing immediately before the data storage destination information of the store instruction is copied to the next add instruction on the reservation station 12. The content of the buffer 31 is the decoder 3
A flag signal (INH_RUBX_UPDATE) that is decoded by 2 and prohibits the update process of the update buffer X by the memory fetch data from the data cache 24 out of the two write processes that occur simultaneously during the above-described store fetch forwarding process is output. .

The flag signal gates the output on the cache side to inhibit the update of the update buffer 2 by the memory fetch data, as shown in FIG. 16C. Here, the + X_DSUBA_EQ_2 signal is an enable signal for the update buffer 2 in the X cycle, and + B_
The DSUBA_EQ_2 signal is an enable signal for the update buffer 2 in the B cycle.

As a result, only the output of the arithmetic unit is stored in the update buffer 2, and the fetched data from the cache 24 which becomes unnecessary by the forwarding processing is discarded. Although only the update buffer 2 is shown here, a similar circuit is provided for each update buffer X and they operate similarly.

FIG. 17 shows an example of another operation sequence using the memory store instruction. 17 (a)
Is the reservation station 12 of the store instruction (ST 5, B) in the W cycle of the load instruction (L 5, A).
The upper P bit is turned off (P1 = 0). This means that the correct value is held in the general-purpose register 5, and in this case, the forwarding processing of the memory fetch data in the next addition instruction (A 6, B) is performed from the general-purpose register 5 instead of from the update buffer. .

As for the instruction for storing the contents of the general-purpose register as in this example, the forwarding process in place of the memory data fetch described above can be executed without contradiction. Here, the “instruction” indicates a general instruction having a DPXW sequence. By the way, as the store instruction, there is also an instruction to add the memory data and the memory data and store in the memory without using the general-purpose register.

FIG. 17B shows an example of such an instruction. In this case, since the data to be forwarded exists only in the update buffer, if the forwarding is attempted at the timing after the W-wise of the preceding instruction shown in (a) of FIG. 17, it may not operate normally.

FIG. 17B shows a case where a total of five update buffers are mounted. Here, the load instruction (L 5, A) uses the update buffer 1 to hold the update data in the general-purpose register 5, and stores the contents of the update buffer 1 in the general-purpose register 5 in the W cycle. As a result, the subsequent instruction 6 is then allowed to use the update buffer 1. By the way, the store instruction (AP A, B in this example) executed next to the load instruction does not use the general-purpose register as the source, but uses the contents of the update buffer 1 as the source as it is.

Subsequent add instructions (A 6, B) forward the contents of the update buffer 1 instead of reading the contents of memory address A according to the invention. However, in this example, the instruction 6 permitted to use the update buffer 1 has already rewritten the contents of the update buffer 1 into fetch data in the B cycle. Therefore, the result obtained by the X cycle of the add instruction executed after that is incorrect.

FIG. 18 shows an example of the second instruction control operation (memory-memory operation instruction) according to the present invention. In FIG. 18, the AP instruction is used as an example of the memory operation instruction that does not use the general-purpose register. The AP instruction is an instruction for adding the contents of the memory A and the contents of the memory B and storing them in the memory A. Here, up to five general purpose register update buffers X (X = 1 to 5) can be used, and the update buffer 6 is assigned as an update buffer dedicated to the AP instruction.

FIGS. 19 and 20 show examples of data setting for timing 2 and timing 3 in FIG. Figure 1
9, the AP instruction (AP
When A, B) are decoded, the memory address portion A of the data storage destination is stored in the memory storage address holding means 20. On the other hand, the update buffer 6 dedicated to the AP instruction is assigned as the fetch destination of the memory address B to be added thereto. It is stored in the DUBA of the AP instruction operand on the reservation station 12, and at the same time is also stored in the temporary storage means 22. Since the general-purpose register is not used in the AP instruction of this example, the update buffer address table and the register update pending table 11 are not indexed.

In FIG. 20, the memory address portion A in the subsequent add instruction (A 6, A) decoded by the instruction register 10 and the memory address A to which the memory storage address holding means 20 holds are compared 21. Compared by. In the present example, since they match, the match signal copies the contents stored in the temporary storage means 22 to the corresponding operand on the reservation station 12. The subsequent operation is the first operation according to the present invention described above.
Is the same as the instruction control operation of.

However, even when the AP instruction is completed, the data for fetch data forwarding of the addition instruction is held in the update buffer 6 dedicated to the AP instruction, and P2
The bit is not reset. As a result, the fetch data forwarding process can be performed using the update buffer 6 dedicated to the AP instruction at any timing. If the addition instruction tries to newly execute a subsequent AP instruction before performing the forwarding processing, the succeeding AP is executed until the forwarding processing is completed.
Instruction decoding is stopped.

According to the configuration of the present invention described above, since the AP instruction update buffer dedicated to the AP instruction that holds the source data to be stored at the predetermined memory address is assigned to the AP instruction that is the preceding instruction, the subsequent memory operation instruction is also used here. Is originally a register-memory instruction that is a register-
It is replaced with an inter-register instruction, and a forwarding processing using the update buffer 6 dedicated to the AP instruction enables a high-speed pipeline operation.

From the above description, the present invention discloses the following contents. First, according to the present invention, a plurality of register update buffers for temporarily storing the result of instruction execution and updating the general-purpose registers at the time when the instruction execution is completed, and which register update buffer contains the data for updating the specified general-purpose register. Output from the update buffer address table indicating whether to store, the register update pending table indicating that the specified general-purpose register is pending update, the general-purpose register address, and the update buffer address table corresponding to the general-purpose register. A register update buffer address, and a reservation station that stores an update pending instruction of the general-purpose register, and specifies the specified register update buffer if the update pending instruction is on, and specifies it if the update pending instruction is off. Information processing apparatus using the general-purpose general purpose register as source data It is premised on the command control method in. There, the following method is disclosed.

(1) When the instruction that requires fetch data from the memory as the source data of the operation is executed and the preceding instruction does not store the memory area, the fetch data is stored in the register update buffer. If the memory area is stored in the preceding instruction and the storage destination address is the same as the fetch data fetch destination address, the previous instruction is used for storing from the reservation station. Copying an update suspension instruction for specifying a register, a register update buffer address, and a general-purpose register buffer address to a fetch data specification information area of a reservation station in which the operation instruction is held, the operation instruction being data fetched from memory. Preceding storage instead of Instruction control method using the specified storage register in decrees.

(2) A register update buffer allocated for updating general-purpose registers at the time of executing an instruction that requires fetch data from a memory as source data for the operation and updates the general-purpose register with the operation result. The operation result is stored again in the register update buffer, and the preceding instruction is retained because the storage address of the preceding instruction and the fetch address of the fetch data are equal. When the register update buffer address for specifying the storage register from the reservation station is copied to the fetch data specification information area of the reservation station where the operation instruction is held, the update buffer address assigned to the operation instruction is held separately What to do It said method comprising the basis of the peak information, that, to prevent that the update buffer is updated by fetching data from after the operation result is stored in the update buffer.

(3) The preceding instruction is an instruction for calculating the memory data and the memory data and storing it in the memory, and at the time of executing the instruction for fetching the fetch data from the storage destination address of the instruction followed by the succeeding instruction, Suppressing the reset of the corresponding update pending instruction in the reservation station in which the subsequent instruction is stored, and by the suppression of the reset, the subsequent arithmetic instruction is fetched even if the preceding memory storage instruction does not use the general-purpose register. Using the register update buffer specified in the preceding store instruction instead of the data.

(4) The preceding instruction is an instruction for calculating the memory data and the memory data and storing it in the memory, and at the time of executing the instruction for fetching the fetch data from the storage destination address of the instruction followed by the succeeding instruction, The update buffer for temporarily holding the data to be stored in the memory is provided separately from the update buffer for updating the general-purpose register, and the subsequent operation instruction specifies the register update buffer specified in the preceding storage instruction instead of the fetched data. Using the above method.

[0060]

As described above, according to the present invention, it is possible to efficiently realize a store fetch forwarding function for a memory operation instruction in an information processing device that performs register renaming.

[Brief description of drawings]

FIG. 1 is a diagram showing an example of a conventional register renaming technique.

FIG. 2 is a diagram showing a configuration example of an operand section of a reservation station.

FIG. 3 is a diagram showing an example of a conventional instruction operation time chart.

FIG. 4 is a diagram showing a basic configuration example of an instruction control device according to the present invention.

5 is an operation flowchart of the instruction control device of FIG.

FIG. 6 is a diagram showing a first instruction control operation example (register-memory instruction) according to the present invention.

7 is a diagram showing an example of data setting at timing 1 in FIG. 6 (b).

8 is a diagram showing an example of data setting at timing 2 in FIG. 6 (b).

9 is a diagram showing an example of data setting at timing 3 in FIG. 6B.

10 is a diagram showing an example of a reservation station in the conventional example of FIG. 6 (a).

FIG. 11 is a diagram showing another operation example of an addition instruction.

FIG. 12 is a diagram showing an example of an extended reservation station.

13 is a diagram showing an example of data setting at timing 1 in FIG.

14 is a diagram showing an example of data setting at timing 2 in FIG.

FIG. 15 is an explanatory diagram of simultaneous writing by store fetch forwarding processing.

FIG. 16 is an operation explanatory diagram of an update buffer address holding unit.

FIG. 17 is a diagram showing another operation example using a store instruction.

FIG. 18 shows a second instruction control operation (memory-
It is the figure which showed an example of the instruction between memories.

19 is a diagram showing an example of data setting at timing 2 in FIG.

20 is a diagram showing an example of data setting at timing 3 in FIG.

[Explanation of symbols]

10 ... Instruction register 11 ... Update buffer address table and register update pending table 12 ... Reservation station 13 ... General purpose register 14 ... Register update buffer 15 ... Arithmetic unit 20 ... Memory storage address holding means 21 ... Comparator 22 ... Temporary storage means 23 ... Update buffer holding means 24 ... Cache 31 ... Buffer 33 ... Decoder

Claims (8)

(57) [Claims] 1. A method for controlling an instruction of an information processing apparatus having a reservation station for storing a plurality of decoded instructions and an update buffer for register renaming, wherein a storage instruction is decoded in a preceding instruction, Holds the memory address of the data storage destination and also holds the information of the update buffer allocated to the data storage source, and executes the instruction that requires the fetched data from the memory address as the source data of the subsequent instruction. When detecting a match between the memory address and the held memory address, when the match is detected, the information of the data storage source of the subsequent instruction registered in the reservation station is updated to the information of the update buffer. To the fetch data from the memory. Instruction control method characterized by consisting, the use of data stored in the update buffer instead. 2. Before the replacement, information on a data storage source of the subsequent instruction is separately held, and the subsequent instruction stored in the update buffer based on the held information on the data storage source. 2. The method according to claim 1, further comprising preventing the result of the operation from being updated by subsequent fetch data. 3. The preceding instruction is an instruction for calculating memory data and the memory data and storing it in the memory,
Suppressing the release of the corresponding update buffer in the reservation station in which the subsequent instruction is stored during execution of the instruction that fetches fetch data from the data storage destination address of the instruction that follows the preceding instruction; 2. The method of claim 1, wherein the subsequent arithmetic instruction uses stored data in the update buffer instead of fetched data from memory even if the preceding memory stored instruction does not use a general purpose register. 4. The preceding instruction is an instruction for operating the memory data and the memory data and storing it in the memory,
Temporarily holding the data to be stored in the memory in the dedicated update buffer provided separately from the update buffer for updating general-purpose registers when executing the instruction that fetches fetch data from the data storage destination address of the preceding instruction The subsequent operation instruction uses the stored data of the dedicated update buffer instead of the fetched data from the memory,
The method according to claim 1 or 3, which comprises: 5. An instruction control device which uses a designated register update buffer as a source data when an update suspension instruction of a general-purpose register is turned on, and uses a designated general-purpose register as source data when an update suspension instruction is turned off. A comparator for comparing the memory address of the data storage destination of the memory storage instruction decoded by the register with the memory address of the memory address portion of the subsequent memory operation instruction decoded by the instruction register, and a match signal from the comparator Is output , the memory address information of the subsequent memory operation instruction on the reservation station is updated and stored in the previous memory store instruction.
Stay instruction, general-purpose register address and update buffer address
Instruction control apparatus characterized by comprising means for replacing the scan of information. 6. The memory address information of the subsequent memory operation instruction on the reservation station before replacement is saved, and the operation result of the subsequent instruction is prevented from being updated by the fetch data by the decode information. Update buffer address holding means,
The device of claim 5, comprising: 7. The preceding instruction is an instruction for calculating memory data and the memory data and storing it in the memory,
When the instruction that fetches fetched data from the data storage destination address of the preceding instruction is executed by the following instruction, the preceding arithmetic operation instruction precedes the fetched data instead of the fetched data even if the preceding memory storage instruction does not use a general-purpose register. 6. The apparatus according to claim 5, further comprising means for suppressing resetting of a corresponding update pending instruction in a reservation station in which a subsequent instruction is stored so as to use the register update buffer specified in the store instruction. 8. The preceding instruction is an instruction for calculating memory data and the memory data and storing it in the memory,
When the instruction that fetches fetch data from the data storage destination address of the preceding instruction is executed by the instruction that follows, the data to be stored in the memory is held exclusively, and the subsequent operation instruction uses the held data instead of the fetched data. 8. A device according to claim 5 or 7, comprising a dedicated register update buffer for use.