JP2000259411A - Processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform out-of-order execution and speculative operation execution with the small number of rename registers even if there are an instruction whose execution time is long and an instruction whose execution time is short. SOLUTION: This processor is provided with a register rename table 12 in an instruction dispatching part 11 and is further provided with a score board 17. Whether an instruction to be written to a rename register or an instruction to be registered with the score board is recorded on the table 12 according to the kind of an instruction and the number of a register where writing is performed is registered before defining instruction execution. When the instruction execution is defined, it is recorded by the board 17. About a subsequent instruction, the table 12 and the board 17 are retrieved to know the number of a writing register of the preceding instruction. Thus, efficiency can be improved even with a small number of rename registers because the rename registers are not used even if an instruction using the score board has long execution time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to instruction control of a processor, and more particularly to a processor that performs register rename.

[0002]

2. Description of the Related Art In recent years, in processor technology, a superscalar technology for executing a plurality of instructions at the same time, and an out-of-order technology for rearranging and executing instructions in particular have high effects. In the out-of-order technology, there is a register renaming technology that reallocates registers specified by an instruction at the time of execution and eliminates dependencies between instructions to increase efficiency. Is assigned a temporary rename register number. Since the assignment of the rename register number is usually performed at the start of the execution of an instruction, if there is an instruction that takes a long time to execute, it is necessary that the number of the rename registers be the same in order for the execution of a sufficient number of instructions to start. Must have a number. The execution result of the instruction is managed as a pair with the assigned rename register number. Usually this is achieved by having as many rename registers as the number of rename register numbers. Therefore, if the execution time differs depending on the type of instruction,
Unless a large number of rename registers are prepared in accordance with the instruction having the longest execution time, sufficient efficiency cannot be achieved. Examples of such an instruction having a long execution time include an instruction for performing a complicated operation such as division or a square root, and an instruction for reading a main memory or other external storage outside a low-speed processor.

As another technique for resolving dependencies between instructions without using a rename register, there is a scoreboard technique for recording whether or not an instruction to be written to a register of that register number is being executed for each register number. In the conventional scoreboard technology, an instruction that attempts to read or write a register recorded as having another instruction to be written to the scoreboard suspends execution, and terminates execution of the write instruction recorded in the scoreboard. Execution of the instruction is resumed by clearing the scoreboard record. In such a conventional scoreboard technique, the order of instructions is recorded on the scoreboard in accordance with the order of instructions, and an instruction that attempts to read or write a register recorded on the scoreboard and subsequent instructions are stopped. This is a basic operation. If a subsequent instruction is to be executed out-of-order, the write register of the stopped instruction cannot be recorded on the scoreboard, so that the dependency with the stopped instruction cannot be resolved. Therefore, it is difficult to use the conventional scoreboard technique simultaneously with the out-of-order technique. Also, in speculative execution in which the branch destination of a branch instruction is predicted and the predicted target instruction is executed out-of-order before the branch instruction, if the prediction is incorrect, the speculatively executed instruction of the prediction target is executed. Must be revoked. At this time, if a prediction target instruction that may be canceled is recorded on the scoreboard, the scoreboard recording must be canceled when the cancellation occurs. If the branch prediction is wrong, the number of instructions to be canceled may be from several to ten or more, so cancellation of the scoreboard is not easy, and the recovery process at the time of prediction failure takes much time and penalties are likely to occur.

Conventionally, the above-mentioned rename register technique and the conventional scoreboard technique are separate techniques used when the former performs out-of-order and the latter does not perform out-of-order. Therefore, it is difficult to efficiently achieve both at the same time.

[0005]

In order to obtain sufficient efficiency in the register renaming technique, it is necessary to prepare a large number of rename registers for instructions having the longest execution time. If the number of the rename registers is small, the number of instructions that can start executing continuously when an instruction with a long execution time is executed decreases, and the efficiency decreases. Further, when the conventional scoreboard technique is used for out-of-order execution, it is difficult to correctly resolve dependencies between instructions, and penalties are likely to occur even for speculative execution. The present invention makes it possible to adapt the scoreboard even when performing out-of-order or speculative execution, makes it compatible with the rename register technology at a low cost, and even if there are long-running instructions with a small number of rename registers. The purpose is to provide a sufficiently high efficiency.

[0006]

SUMMARY OF THE INVENTION A processor according to the present invention writes the result of an instruction to solve the above problems.
One or more numbered registers, register renaming means for rewriting the number of the register for writing specified by the instruction in the first type of instruction to a temporary rename register number, and second type And a scoreboard for recording for each register number that execution of an instruction to be written to the numbered register has been determined, and for both the first and second types of instructions, Rename hit determining means for determining whether the number of the register performing the read is not replaced by the temporary rename register number by the register renaming means, and when an instruction reads or writes the register. A document that examines the contents of the scoreboard and indicates whether there are any more instructions to write to the register. It is characterized by comprising write instruction determining means and instruction execution inhibiting means for inhibiting the execution of the read or write instruction when the result of the write instruction determining means indicates that there is another write instruction.

According to this configuration, even if the execution time of the second type of instruction is long, the rename registers are not used, so that a sufficient number of rename registers can achieve sufficient efficiency.

More specifically, the instruction execution inhibiting means temporarily executes an instruction temporarily, an instruction temporary execution canceling means canceling the result of the temporary execution of the instruction, and the instruction to read or write the instruction. And an instruction re-executing unit for re-executing the instruction execution, thereby simplifying the instruction execution inhibiting unit due to dust.

Further, for each of the numbered registers,
A scoreboard preceding recording means for detecting that there is the second type of instruction to perform writing before the execution of the second type is determined; and, when the instruction performs reading or writing of the register, A scoreboard preceding write command determining means for indicating whether or not another command to be written to the register is recorded by the scoreboard preceding recording means, and when the result of the scoreboard preceding write command determining means is another command to be written; Preferably, the instruction re-executing means re-executes an instruction for reading or writing to the register after the execution of the other write instruction is determined. According to this configuration,
Before the execution of the second type of instruction is determined, the second type
, It is possible to correctly detect the dependencies caused by the instructions of the above type, and the execution of the instructions can be expedited without waste.

Further, the register renaming means and the scoreboard preceding recording means are constituted by the same register writing preceding recording means, so that it can be implemented with a simple configuration.

[0011] The present invention further includes provisional instruction execution means for temporarily executing the instruction, instruction execution determination means for determining whether execution of the instruction is determined, and determined instruction execution means for executing the instruction whose execution has been determined. Wherein the instruction is divided into a first type of instruction executed by the instruction provisional execution means and a second type of instruction executed by the definite instruction execution means. When the type of instruction uses the result of the second type of instruction, the second type
Determination means for determining whether the execution of an instruction of the type has been completed and a result has been obtained; and the first or the second method when the result of the determination instruction execution completion determination means has not yet been completed. Instruction execution inhibiting means for inhibiting the execution of the two types of instructions, so that even if the execution time of the second type of instruction is long, the execution of the other type of instruction is not performed until the execution of the instruction using the second type of result. Make it executable.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to the drawings. In the following, it is assumed that all signal lines in the figure have the necessary number of bits for transmitting necessary instruction codes, register numbers, and the like.

FIG. 1 shows an example of an embodiment of a processor according to the present invention.

In FIG. 1, the rename register file 14
The main body register file 15 is a register file in which the numbered registers are collected by the number of numbers.

The instruction fetch unit 10 reads an instruction code from a memory or an instruction cache outside the processor and sends the instruction code to the instruction dispatch unit 11.

The instruction dispatch unit 11 decodes the instruction to determine the type of the instruction, and determines whether the instruction is a type of writing the result in the rename register or an instruction of registering the result in the scoreboard 17. In the case of an instruction of a type to be written in the rename register, a new rename register number is assigned to the write register number, and this is registered in the register rename table 12 in the instruction dispatch unit 11 with a mark indicating that the instruction is to be written to the rename register. In the case of an instruction of the type to be written to the scoreboard 17, a new rename register number is similarly assigned to the write register number, a mark indicating that the instruction is to be written to the scoreboard is added, and the register is registered in the register rename table 12. For both instructions, check the register rename table 12 for the read register number and the write register number. If the read register number is assigned a rename register number marked to write to the rename register, the read register number , And retrieve the assigned rename register number so as to read the rename register. If a read register number or a write register number is assigned a rename register number marked to be written to the scoreboard, an instruction re-execution mark signal 177 is sent to the instruction Notify that it will be re-executed. At the same time, the read register number and the write register number are sent to the scoreboard 17 via the signal line 171, it is checked whether or not the scoreboard 17 is marked, and the result is received via the signal line 172. When the signal line 172 reports that the read register number or the write register number is marked on the scoreboard 17, the instruction completion unit 16 is similarly notified by the instruction re-execution mark signal 177. After performing the above processing, the instruction control information and the register number are sent to the instruction execution unit 13 to instruct the instruction execution. Also, the instruction completion instruction is notified to the instruction completion control unit 16 through the signal line 162 together with the instruction type and the write register number.

In the instruction execution unit 13, when the read register number is assigned a rename register number marked to be written to the rename register, the result is stored in the register of the rename register file 14 in the rename register file. The execution of the instruction is made to wait until it is written, and when the result is written, it is read and the instruction is executed. In other cases, a value is read from the register of the number designated by the instruction in the main body register file 15 and the instruction is executed. At this time, even if there is an instruction waiting for the result to be written to the rename register, if there is another instruction instructed to be executed by the instruction dispatch unit 11, the control is performed so that the instruction is executed first. Do. This is the out-of-order instruction execution control.

In the case of an instruction of the type to be written in the rename register, when the execution of the instruction is completed, the result is written to the assigned rename register number of the rename register file 14 via the signal line 173. Further, the completion of the instruction is notified to the instruction completion control unit 16 via the signal line 163.

For an instruction of the type to be registered in the scoreboard, execution of the instruction is started when the instruction execution decision signal 174 is received from the instruction completion control unit. At this time, if the execution result of the instruction is not written in the main body register file 15, the execution of the instruction may be partially performed before receiving the instruction execution determination signal 174. When the execution of the instruction is completed, signal line 17
Write the result to the register specified by the instruction of the main unit register file 15 by 5 and the signal line 17 to the scoreboard 17
A write completion signal and a write completion register number are transmitted by 6.

The instruction completion control unit 16 manages the order of the instructions notified from the instruction dispatch unit 11 and, if the instruction is a type of writing a result to the rename register, the instruction execution unit 13 terminates execution of each instruction. Record whether signal 163 was sent. The instruction in which the execution end signal 163 is recorded reads the data stored in the rename register file 14 using the read instruction signal 165 in the order notified from the instruction dispatch unit 11, and reads the data in the main body register by the write instruction signal 166. • Write to the register of the write register number specified by the instruction in file 15. At this time, a rename reset signal 178 is sent to the instruction dispatch unit 11, and the register rename table 178 is sent.
Delete the registration in 12. As described above, since writing to the main body register file 15 is performed in the order of the original instruction, even if an instruction is overtaken by the instruction execution unit 13 by out-of-order execution control and executed, Are consistent in order.

In the case of the type of instruction to be registered in the scoreboard, the execution of all the previous instructions is completed in the same order as notified by the instruction dispatch unit 11, and the result is transferred from the rename register file 14 to the main body register. File 15
Is transferred to the instruction execution determination signal 174, the instruction execution unit 13 is notified that the execution of the instruction has been determined. At this time, a write register number of the instruction whose execution has been determined is simultaneously transmitted to the scoreboard 17 via the signal line 167. Also, rename the reset signal 178 to the instruction dispatch unit 1.
1 and delete the registration in the register rename table 12.

The instruction completion control unit 16 records the instruction re-execution mark signal 177 of all types of instructions when the instruction re-execution mark signal 177 is sent from the instruction dispatch unit 11, in the order notified from the instruction dispatch unit 11. All previous instructions have completed execution and the result is
When the result is transferred from 14 to the main body register file 15 or execution is started by the instruction execution decision signal 174, the instruction refetch signal 161 is sent to the instruction fetch unit 10, and the instruction reexecution mark signal 177 is sent. Re-fetch from the recorded instruction and re-execute.

In the scoreboard 17, when the instruction completion control unit 16 notifies the instruction register of the execution of the instruction via the signal line 167, this is recorded and recorded in the instruction execution unit 13.
When the completion of the writing is notified by the signal line 176, the record is erased. While the writing is being recorded, when the register number for reading or writing sent from the instruction dispatch unit via the signal line 171 matches the number of the recorded register, this is notified by the scoreboard hit signal 172. .

FIG. 2 shows an example of the embodiment of the instruction dispatch unit 11. The instruction fetched by the instruction fetch unit 10 is decoded by the instruction decode unit 110. As a result, an instruction dispatch signal 212, instruction type control information 211, a read register valid signal 208, a read register number 209, a write register number 207, and a scoreboard write valid signal 205 or a rename write valid signal 206 are output. When the scoreboard write enable signal 205 or the rename write enable signal 206 is output, the write register number 207 is registered in the register rename table 12 together with the mark by the scoreboard write enable signal 205 or the rename write enable signal 206. At this time, the rename register number used for registration is output from the rename register assignment number register 112 to the signal line 201. The rename register assignment number register 112 always outputs the rename register number assigned to the next registration. When the scoreboard write enable signal 205 or the rename write enable signal 206 is output and the current rename register assignment number is used, the OR gate 113
Is added to the output of the rename register assignment number register 112 by the adder 111 to generate a rename register number to be newly assigned next. The generated value is written back to the rename register assignment number register 112 again. O
The output of the R gate 113 is sent as a write register number valid signal 210 to the scoreboard 17 via a signal line 171 together with the write register number 207, read register valid signal 208, and read register number 209.

In the register rename table 12, the read register number 209 is checked to determine whether there is an instruction of a type for writing to the same number or writing to the rename register. If any,
The rename register read signal 202 is output, and the signal line 2
At 03, the rename register number assigned to the write register of the instruction is output as the read rename register number to read the write result of the instruction in place of the read register. If there are a plurality of instructions that write to the same number and write to the rename register, the most recently assigned rename register number is output. Further, for both the read register number 209 and the write register number 207, it is checked whether or not there is an instruction of the type to be registered in the scoreboard that writes in the register of the same number. Such an instruction is not yet registered in the scoreboard 17 before its execution is determined. If such an instruction exists, a scoreboard preceding hit signal 204 is output. This scoreboard preceding hit signal 204 is
Scoreboard hit signal 172 output from OR gate 1
The logical sum is obtained by 14 and becomes an instruction re-execution mark signal 177.

FIG. 3 is an example of an embodiment of the register rename table 12.

In FIG. 3, the number of entries 300 is equal to the number of rename registers. In addition, the number decoder 135 generates an entry selection signal 301 based on the rename register assignment number 201, and the encoder 132 generates the read rename register number 203. OR gate 133 for generating the read signal of the rename register, scoreboard preceding hit signal 2
There is an OR gate 134 that generates 04.

In FIG. 3, when a rename register write valid signal 206 is input, first, an AND gate 302 performs an AND operation with an entry selection signal 301. The entry selection signal 301 is obtained by decoding the rename register assignment number 201 by the number decoder 135 and output at the entry 300 corresponding to the number. In this case, the output of the AND gate 302 becomes a control signal in response to the input of the rename register write enable signal 206 for the entry indicated by the rename register assignment number 201. By the output of the AND gate 302, 1 indicating that the mark is present is recorded in the mark record 123 related to the rename register write valid signal 206. At the same time, the write register number input to the signal line 207 is recorded in the main body register number recording unit 120. Main unit register number recording unit 120
The signal 305 instructing the recording to be performed on the OR gate 127
The logical OR of the rename register write enable signal 206 and the scoreboard write enable signal 205 is obtained, and the result is ANDed with the entry select signal 301 by the AND gate 304 to generate the scoreboard write enable signal 205 Also output when is input. Also AND
By the output of the gate 302, 1 is recorded in the latest record 121 indicating that it is the rename register number most recently assigned to the same write register number. For the entry of another rename register number for which the entry selection signal 301 is not output, the comparator 128 compares the write register number recorded in the main body register number recording unit 120 with the write register number input to the signal line 207. . If the comparison results in a match, the AND gate 306 performs an AND operation with the rename register write enable signal 206, and 0 is recorded in the latest record 121 as a result. By doing so, when there are some entries having the same write register number recorded in the main body register number recording unit 120, 1 is recorded only in the latest record 121 of the entry of the most recently assigned rename register number. Is guaranteed to be.

The read register number input to the signal line 209 is compared by the comparator 122 with the write register number recorded in the main body register number recording section 120. If the comparison results in a match, the AND gate 124 ANDs the mark record 123 related to the rename register write valid signal 206 and the latest record 121 to generate a rename entry hit signal 130. By using the latest record 121, even if there are a plurality of write register numbers recorded in the main body register number recording unit 120, only the rename entry hit signal 130 of the entry of the most recently assigned rename register number is output. .
As a result, the read rename register number 203 is generated by converting the entry to which the rename entry hit signal 130 has been output into a number by the encoder 132. Also, the rename register read signal 202 is
The OR gate 133 generates a logical OR of the rename entry hit signals 130 output from all the entries.

When the scoreboard write valid signal 205 is input, the AND gate 303 causes the entry selection signal 301 to be input.
Is ANDed with By the output of the AND gate 303, 1 is recorded in the mark record 125 relating to the scoreboard write valid signal 205. At the same time, the write register number input to the signal line 207 is recorded in the main body register number recording unit 120.

For the other entries for which the entry selection signal 301 is not output, the read register number 209 and the write register number 207 are respectively set to the main body register number recording section 120.
And the comparators 128 and 122
Are compared. AND gate 129 when the result of comparison is a match
And 126 enable the scoreboard write enable signal 205
, And the logical sum signal and the logical product of the rename write valid signal and the scoreboard write valid signal by the read register valid signal 208 or the output of the OR gate 127, respectively, are taken. As a result, the mark record 125 related to the scoreboard write valid signal 205
When 1 is recorded in the register number, it is checked whether any of the read or write register number matches the register number recorded in the main body register number recording unit 120. Finally, the outputs of the AND gates 129 and 126 are ORed by the OR gate 131, and further ORed by the OR gate 134 for all entries. Thereby, when 1 is recorded in the mark record 125 relating to the scoreboard write valid signal 205 in any entry, the read or write register number is the same as the register number recorded in the main body register number recording unit 120 of that entry. A match is indicated. This is the scoreboard first hit signal 20
It becomes 4.

When a rename reset signal 178 is sent from the instruction completion control unit 16, 0 is recorded in a mark record 123 relating to the rename register write valid signal 206 and a mark record 125 relating to the scoreboard write valid signal 205. Invalidate entry registration. At this time, it is assumed that the rename reset signal 178 can specify which number entry registration is to be invalidated. In brief, a signal having the number of bits corresponding to the number of entries may be used as shown in FIG.

FIG. 4 is an example of the embodiment of the scoreboard 17.

In the figure, when the instruction completion control unit 16 sends a write register number of an instruction of the type to be registered in the scoreboard whose execution has been determined and an execution determination signal to the signal line 167,
Decoded by the scoreboard registration decoder 401. According to the output of the scoreboard registration decoder 401, 1 is recorded in the number corresponding to the write register number of the scoreboard recording unit 403.

If the same register number is sent from the instruction dispatch unit 171 as a read or write register number from the signal line 171 while 1 is recorded in the scoreboard recording unit 403, this is checked and the scoreboard is checked. Return as hit signal 172. More specifically, signal line 171
The read and write register numbers and their valid signals sent by the
4 and is decoded by the write number decoder 407 into a decode signal corresponding to the number. Each decoding signal is ANDed with the recording of the corresponding number in the scoreboard recording unit 403 and the AND gate groups 405 and 408. The outputs of the AND gate groups 405 and 408 are ORed in the OR gates 406 and 409, respectively, and it can be seen that 1 has been recorded in any of the scoreboard recording units 403 corresponding to the read and write register numbers. . Finally, this is ORed with the OR gate 410 to obtain a scoreboard hit signal.
171 is generated.

When the instruction execution unit 13 notifies the completion of the writing of the result of the instruction of the type to be registered in the scoreboard via the signal line 176 together with the register number of the completed writing, this is notified by the scoreboard deletion decoder 402. Decrypt. By the output of the scoreboard deletion decoder 402, 0 is recorded in the record corresponding to the write register number of the scoreboard recording unit 403, indicating that the registration of the scoreboard has been deleted.

FIG. 5 shows an example of the embodiment of the instruction completion control unit 16.

In the figure, a reorder buffer 501 includes an instruction dispatch signal, a scoreboard write enable signal, a rename write enable signal, a write register number, and an instruction re-execution mark signal 177 sent from the instruction dispatch unit 11 via a signal line 162. Are recorded in the order of the sent instructions. As shown in the figure, the scoreboard write valid signal indicates that the instruction is a type of instruction to be registered in the scoreboard, and the rename write valid signal indicates that the instruction is a write instruction to the rename register. , Both cannot be one.

Also, as shown in the figure, when the instruction execution end signal 163 is sent from the instruction execution unit 13, a 1 mark indicating the end is added to the corresponding instruction in the reorder buffer 501.

In the figure, when the instruction that has reached the lower end of the reorder buffer 501, that is, the completion processing of all the preceding instructions is completed and the oldest instruction among the instructions recorded in the reorder buffer 501 is reached, the instruction Execution mark signal 177
Is checked to see if it is 1. If the record of the instruction re-execution mark signal 177 is 1, the instruction re-fetch signal 161
To the instruction fetch unit 10 to instruct that the instruction be re-executed.

When the record of the instruction re-execution mark signal 177 is 0, it is checked whether the record of the scoreboard write valid signal is 1 or the record of the rename write valid signal is 1.

If the record of the rename write enable signal is 1, it is checked whether or not a mark by the instruction execution end signal 163 has been added. If not, the instruction execution section 13 sends the instruction execution end signal 163 to the instruction. Wait until it is sent out. If the mark by the instruction execution end signal 163 is added or the instruction execution end signal 163 is sent, the rename register read signal 165 is sent to the rename register file 14 to instruct the reading of the rename register, and at the same time, the main body register is read. Sends a register write signal and a write register number to the file 15, and instructs the result from the rename register file 15 to be written back to the main body register file 14.

The record of the scoreboard write valid signal is 1
In the case of (1), an instruction execution determination signal 174 is sent to the instruction execution unit 13 to notify that the execution of the instruction has been determined. Also, an execution decision signal and the recorded write register number are sent to the scoreboard 17 as an execution decision register number via the signal line 167, and the scoreboard is registered.

In both cases, finally, a rename reset signal 178 is sent to the instruction dispatch unit 11, and the registration in the register rename table 12 is deleted. This completes the instruction completion processing, deletes the record of the instruction from the reorder buffer 501, and moves to the completion processing of the next instruction.

[0045]

According to the present invention, register renaming can be efficiently performed with a small number of rename registers even if there is an instruction having a long execution time.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a main part of a processor according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an instruction dispatch unit of the processor.

FIG. 3 is a block diagram showing a configuration of a register rename table of the processor.

FIG. 4 is a block diagram showing a configuration of a scoreboard of the processor.

FIG. 5 is a block diagram showing a configuration and operation of an instruction completion control unit of the processor according to the embodiment of the present invention.

[Explanation of symbols]

10 Instruction fetch section 11 Instruction dispatch section 12 Register rename table 13 Instruction execution section 14 Rename register File 15 Body register file 16 Instruction complete control unit 17 Scoreboard 110 Instruction decode unit 112 Rename register assignment Number register 120 ........ Main body register number recording section 121 ...... Latest record 123 ......... Mark record related to rename register write enable signal 125 ........ Mark related to scoreboard write enable signal Record 130 Rename entry hit signal 161 Instruction refetch signal 163 Instruction execution end signal 165 Rename register read instruction signal 166 Main unit register Write instruction signal 172 ... Scoreboard hit signal 174 ... Instruction execution decision signal 177 ... Instruction re-execution mark signal 178 ... Rename reset signal 201 ... Rename Register allocation number 202 ... Rename register read signal 203 ... Read rename register number 204 ... Score board preceding hit signal 205 ... Score board write enable signal 206 ... Rename write enable signal 207 Write register number 208 Read register enable signal 209 Read register number 211 Command type control signal 212 Command Dispatch signal 300 Register entry in register rename table 301 Entry selection signal 401 Scoreboard registration decoder 402 Scoreboard deletion decoder 403 Scoreboard Recording unit 404 .... Read number decoder 407 ... Write number decoder 501 ... Reorder buffer.

Continuation of the front page (72) Inventor Kazunari Tanaka 1 Horiyamashita, Hadano-shi, Kanagawa F-Term Co., Ltd. General term computer division, Hitachi, Ltd. 5B013 AA12 CC05

Claims (5)

[Claims] 1. A temporary rename register for writing one or more numbered registers into which the result of an instruction is written, and the number of the register for writing specified by the instruction when executing the first type of instruction. Register renaming means for renumbering; a scoreboard for recording, for each number of the register, execution of an instruction to be written to the numbered register when executing the second type of instruction; A renaming hit for judging whether or not the number of the register for reading specified by the instruction is replaced by the temporary renaming register number by the register renaming means when executing both the second and the second types of instructions. Determining means for reading or writing the register in accordance with an instruction; Write instruction determining means for indicating whether or not there is another instruction to be written to the master, and instruction execution inhibiting means for inhibiting the execution of the read or write instruction when the result of the write instruction determining means indicates that there is another write instruction With a processor. 2. The method according to claim 1, wherein the instruction execution inhibiting means temporarily executes the instruction, temporarily cancels the result of the temporary execution of the instruction, and executes the read or write instruction again. 2. The processor according to claim 1, further comprising an instruction re-executing means for correcting. 3. The processor according to claim 2, wherein said second type of execution determines that there is said second type of instruction to be written for each of said numbered registers. A scoreboard precedence recording means for detecting beforehand, and a scoreboard precedence indicating whether or not another instruction to be written to the register by the scoreboard precedence recording means when the instruction reads or writes the register. When the result of the scoreboard preceding write instruction determining means includes another instruction to be written, the instruction re-executing means reads out the register after the execution of the other write instruction is determined. Alternatively, a processor for re-executing a write instruction. 4. The processor according to claim 3, wherein said register renaming means and said scoreboard preceding recording means are constituted by the same register writing preceding recording means. 5. An instruction temporary execution means for temporarily executing an instruction,
An instruction execution determination unit that determines whether execution of an instruction is determined, a determined instruction execution unit that executes an instruction whose execution is determined, and an instruction that is to be newly executed is executed by the determined instruction execution unit. When the result of the instruction is used, the execution of the instruction executed by the finalized instruction executing means is completed, and the finalized instruction execution end determining means for determining whether a result is obtained. A processor comprising instruction execution inhibiting means for inhibiting the execution of the instruction to be newly executed when the execution has not been completed yet.