JP3428253B2 - Sequencer - Google Patents

Description

Description: BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a sequencer for calculating a ladder sequence, and more particularly to a contact lock process for realizing a debug function of a ladder program. 2. Description of the Related Art FIG . 2 shows an example of a ladder circuit, which comprises contacts corresponding to a plurality of memories. Also, this circuit
It is expanded in the program memory of FIG. 3 and further expanded in the data memory as shown in FIG. In FIG. 4 , each numeral indicates an address of a memory location. The program memory and the data memory are prepared as memories 1 and 2 of a block having a hardware configuration of the sequencer in FIG. 1, and store programs and data for constructing a ladder circuit. In the block diagram shown in FIG. 1, the instruction fetch unit 3 reads one instruction from the program memory 1 as data into the instruction register 3B using the value of the program counter 3A as an address. [0005] The analysis unit 4 decodes the operation code portion of the instruction register 3B by the decoder 4A, and sequentially stores it in the pipeline register 4B. The operand data access section 5 takes in the operand section of the instruction register 3B,
The address corresponding to the operand is obtained in the data pointer 5A, and this is set as the address of the data memory 2. By this address designation, the data read from the data memory 2 is transferred from the data buffer 5B to the data register 6. Further, the data in the data buffer 5C is written into the data memory 2. The operation unit 7 executes an operation using the data of the data register 6 in accordance with the result of analysis of the instruction code from the pipeline register 4B. The pipeline register 4B performs a pipeline process for executing an instruction in order to improve the operation speed. The following table shows an example of the pipeline process. [Table 1] The pipeline processing is effective for efficiently using the instruction fetch unit 3, instruction analysis unit 4, operand data access unit 5, and operation unit 7. In the above table, focusing on the step n + 2, it means that the fetch of the instruction C, the analysis of the instruction B, the operand data read, and the operation of the instruction A are processed in parallel. That is, in either the microcode system or the hardware processing system, preprocessing is performed in advance for the execution of an instruction prior to the current execution (operation). At this time, the pipeline register 4B stores
As shown in Table 1, according to the step, the operation unit 7 is instructed, for example, by the instruction A, and at the same time, the program counter 3A is instructed to increment for fetching the instruction C, and the data pointer 5A is instructed. The pointer of B is designated. In the above-described sequencer, when a ladder sequence is created and input to the sequencer, and a predetermined operation is performed, a lock on the data in the data memory 2 of the sequencer or a program memory In many cases, a function for locking one instruction is provided. This data lock is forcibly ON-locking or OFF-locking the contacts (memory data) and commands. Now, assuming that the ladder circuit of FIG. 2 locks the contact of "M40" as the lock for the contact of the data memory, the memory content of "M40" is rewritten from "0" to "1", for example. Can be Therefore, the instruction using the contact “M40” also needs to change its operation content. For example, in the program memory of FIG. 3 , it is necessary to use "1" as operand data of three instructions ST M40, AND M40, and LD M40. Conventionally, in order to realize this function, all the instructions using M40 as an operand are searched from the program memory 1 as shown in FIG. 3 and the operation contents are changed by changing to another code. Therefore, it takes a considerable amount of time to operate a large-capacity instruction code, which causes a problem such as disturbing the operation scan. As a method for solving this problem, a lock designation data memory 8 having the same memory capacity as the data memory 1 and having a one-to-one memory location is provided separately. Rewrite the data at the same memory location of the memory,
There is a method in which the presence or absence of a lock designation and the type of lock designation are identified by referring to a lock designation data memory when executing a ladder program. In this method, when the contact is locked or unlocked, the data at the same memory location in the lock designation data memory can be rewritten by an editor or the like having a debugging function. Need not be operated, and the process of contact lock and release is greatly simplified. In the case of an instruction for writing the operation result to the data memory 2, it is checked whether or not the lock is specified by referring to the relevant memory location of the lock specification data memory. When writing the information, whether it is possible or not is identified. In a conventional system having a lock designation data memory, to execute a ladder program, a code of an instruction to be executed is read from a program memory 1 and a hardware for processing the instruction is read. Transfer the processing right to the firmware or firmware. The hardware or firmware that has received the processing right performs the processing of the instruction, and the execution proceeds sequentially to the reading of the instruction code to be executed next. The final operation is a coil command for driving the coil contacts. When the processing right is transferred to the hardware or firmware that performs the processing of the coil command, it is necessary to check whether the contacts are locked or not by checking the equivalent bits of the lock designation data memory 8. In other words, even when the sequencer has finished debugging and enters the operation state or the test operation state and all locks have been released, the lock designation data 8 is checked for the coil command. For this reason, in the processing of the coil instruction itself, the check time of the lock designation data memory 8 is added to the operation state of the sequencer, and the processing time is increased. The coil instruction is used at a high rate in the ladder program, and the scan time is long. The check as to whether or not the lock is performed is performed every time the coil command is processed. When the lock is not locked, the process becomes useless. An object of the present invention is to provide a sequencer which reduces the processing time by reducing the check of the lock designation of the coil instruction. According to the present invention, there is provided a lock in which contact data of a data memory is forcibly and individually specified to be turned on or off. In a sequencer that provides a designated data memory and debugs a ladder program using the data of the memory when executing a ladder program, checks the lock designated data memory and executes an instruction when there is at least one lock designation Two types of coil instruction processing are prepared: a coil instruction processing to execute an instruction without checking the lock specification data memory when there is no lock specification at all, and a lock specification in the data memory. Prepare a lock flag that indicates on / off whether there is at least one or not at all. The process of the coil instructions of the program and executes by switching the two kinds of coils instruction processing in accordance with the on and off the lock flag. In this embodiment, as a coil instruction processing by a hardware processing method, a firmware processing method, or a microcode processing method, when there is at least one lock specification, the lock specification data is used. Two types of coil instruction processing are prepared: a coil instruction processing for executing an instruction by checking a memory, and a coil instruction processing for executing an instruction without checking a lock designation data memory when there is no lock designation. When the lock designation is 1 in the data memory 2,
A lock flag indicating whether there is at least one or not at all is prepared by on / off, and this lock flag is used for instruction decoding when transferring the processing right to the coil instruction. The lock flag is reserved as a hardware register or a firmware flag, and is switched on / off by a man-machine interface unit of the sequencer or an instruction received from the man-machine interface unit. In the above configuration, for the processing of the coil command, the hardware or the like having received the processing right performs the coil command processing for checking the lock designation data memory and the coil command processing for not checking, depending on whether the lock flag is on or off. And execute. For example, in the hardware processing method shown in FIG. 1, an output signal of a lock flag is input to the input of the decoder 4A when decoding an instruction code, in addition to the instruction code, and the output signal of the lock flag is turned on / off. Analysis part 4
And the operation of the arithmetic unit 7 is switched. That is, the execution is switched between the execution in which the lock designation data memory 8 is checked and the execution in which the check is not made in accordance with the lock flag. In the firmware processing method, a software table is generally used when converting an instruction code into an instruction code processing code entry. A lock flag is added to the input code of this table, and the lock flag is turned on. Switching between two types of entries prepared in the firmware for processing the lock command (one for checking the lock designation data and one for not checking the lock designation data) according to the off state. In the microcode processing method, an output signal of a lock flag is input to an input of a decoder circuit for decoding an instruction code, in addition to the instruction code, and the processing of the lock instruction is performed by turning on / off the lock flag. Two types of microcode entries are prepared, and the lock specification data is checked and executed without checking. Therefore, according to the present embodiment, when a ladder program is created and debugging is performed to perform a test run of a plant, the lock designation memory can be checked by the lock flag. Then, the coil instruction in a state where the contact (memory) locked at the time of debugging is unlocked when the plant is in the operating state does not check the lock designation memory, so that unnecessary processing is eliminated and the speed is increased. it can. The present embodiment can be applied not only to the memory lock by the contact instruction but also to the memory lock by the numerical operation instruction. In the numerical operation instructions, two types of write instructions (an instruction for checking the lock designation memory and an instruction not to check) are used instead of the coil instruction at the time of the contact instruction. As described above, according to the present invention, a data memory is provided. A lock specification data memory that forcibly locks the contact data individually on or off is provided, and when debugging the ladder program using the data of the memory when executing the ladder program, check the lock specification data memory Command processing to be performed and instruction processing not to be checked are prepared, and the command processing is switched depending on whether or not the lock is specified in the data memory. No processing is required, and high-speed processing is possible. [0050]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a sequencer according to the present invention. FIG. 2 is an example of a ladder circuit of a sequencer . FIG. 3 shows an example of a program memory of a sequencer . FIG. 4 is an example of a data memory of a sequencer . [Description of Signs] 1 ... Program memory 2 ... Data memory 3 ... Instruction fetch unit 4 ... Analysis unit 5 ... Operand data access unit 6 ... Data register 7 ... Operation unit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-5-27811 (JP, A) JP-A-1-140301 (JP, A) JP-A-2-5103 (JP, A) JP-A-6-103 318106 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G05B 19/04-19/05

Claims (1)

(57) [Claim 1] A lock designation data memory is provided for individually and forcibly locking the contact data of the data memory to ON or OFF, and the data in the memory is used when executing the ladder program. A sequencer that debugs a ladder program and checks the lock designation data memory when at least one lock designation exists and executes an instruction, and executes the lock designation when there is no lock designation at all. Two types of coil instruction processing are provided: a coil instruction processing for executing an instruction without checking the data memory, and a lock flag indicating on / off whether the data memory has at least one lock specification or no lock specification. In the processing of the coil instruction of the ladder program, the two types are selected according to the on / off state of the lock flag. Sequencer and executes switching the coils instruction processing.