JPH09120307A - Sequencer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the number of lock designation check items of a coil instruction by preparing the check/non-check instruction processing for a lock designation data memory and switching the instruction processing according to the presence or absence of the lock designation. SOLUTION: A lock designation data memory 8 designates to individually and compulsively lock the contact data stored in a data memory 2 in an ON or OFF state. When a ladder program is carried out, the ladder program is debugged based on the data of the memory 2. Then the processing where the memory 8 is checked and an instruction is carried out if the lock designation is confirmed is prepared together with the processing where the instruction is carried out without checking the memory 8 if no lock designation is confirmed. In addition, a lock flag is prepared to show whether the lock designation is given to the memory 2 in an on/off state. Thus two types of coil instruction processing are carried out with switching according to the on/off state of the lock flag when the coil instruction of the ladder program is carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sequencer for calculating a ladder sequence, and more particularly to contact lock processing for realizing a debug function of a ladder program.

[0002]

2. Description of the Related Art FIG. 3 shows an example of a ladder circuit, which is composed of contacts corresponding to a plurality of memories. Further, this circuit is expanded in the program memory of FIG. 4 and further expanded in the data memory as shown in FIG. In FIG. 5, each number indicates the address of the memory location.

The program memory and the data memory are prepared as the memories 1 and 2 of a block whose sequencer is shown in FIG. 1 in a hardware configuration, and stores programs and data for constructing a ladder circuit.

In the block diagram shown in FIG. 1, the instruction fetch unit 3 reads one instruction from the program memory 1 as data to the instruction register 3B using the value of the program counter 3A as an address.

The analysis section 4 decodes the operation code section of the instruction register 3B by the decoder 4A and stores it in the pipeline register 4B sequentially.

The operand data access section 5 fetches the operand section of the instruction register 3B,
The address corresponding to the operand is obtained in the data pointer 5A and is used as the address of the data memory 2. By this address designation, the data read from the data memory 2 is transferred from the data buffer 5B to the data register 6. Further, the data in the data buffer 5C is written in the data memory 2.

The operation unit 7 executes an operation using the data in the data register 6 according to the analysis result of the instruction code from the pipeline register 4B.

The pipeline register 4B performs pipeline processing for instruction execution in order to improve the operation speed. The following table shows an example of pipeline processing.

[0009]

[Table 1]

The pipeline processing is effective in efficiently using the instruction fetch unit 3, the instruction analysis unit 4, the operand data access unit 5, and the operation unit 7. Focusing on the step of n + 2 in the above table, it means that the fetch of the instruction C, the analysis of the instruction B, the operand data read, and the operation of the instruction A are processed in parallel.

That is, in either the microcode method or the hardware processing method, preprocessing is performed in advance in order to execute an instruction prior to the current execution (operation).

At this time, the pipeline register 4B is
As shown in Table 1, according to the step, the arithmetic unit 7 is instructed to perform an operation by, for example, the instruction A, at the same time, the program counter 3A is instructed to increment for fetching the instruction C, and the data pointer 5A is instructed. Pointer B is designated.

In the sequencer as described above, when a ladder sequence is created and input to the sequencer and a predetermined operation is performed, in order to realize a debugging function, lock on the data in the data memory 2 of the sequencer or program memory is performed. In many cases, a function for locking one instruction is prepared. As for the lock for this data, a contact (memory data) or a command is forcibly ON-locked or OFF-locked.

Now, considering the case where the contact of "M40" is ON-locked by the ladder circuit of FIG. 3 as a lock for the contact of the data memory, the memory content of "M40" is rewritten from "0" to "1", for example. To be Therefore, it is necessary to change the operation content of the instruction using the "M40" contact. For example, in the program memory of FIG. 4, it is necessary to use "1" as the operand data of the three instructions ST M40, AND M40, LD M40.

Conventionally, in order to realize this function, all the instructions having M40 as an operand are searched from the program memory 1 as shown in FIG. 4, and the operation contents are changed by changing to another code. Therefore, it takes a considerable amount of time to process a large-capacity instruction code, which causes an adverse effect such as disturbing the operation scan.

As a method for solving this problem, a lock designation data memory 8 having the same memory capacity as the data memory 1 and corresponding memory locations on a one-to-one basis is additionally provided, and the lock designation data is used when contact locking is performed. Rewrite the data in the memory at the same memory location,
There is a method in which the presence or absence of lock designation and the type of lock designation are identified by referring to the lock designation data memory when executing a ladder program.

In this method, when the contact lock or unlock is performed, the data at the equal memory location of the lock designation data memory need only be rewritten by an editor or the like having a debug function. The operation of contact locking and unlocking is greatly simplified.

In the case of an instruction to write the operation result to the data memory 2, it is checked whether or not the lock is specified by referring to the memory location of the lock-specified data memory, and the operation result is stored in the data memory 2. When writing to, identify whether it is possible.

[0019]

[Problems to be solved by the invention]

(First Problem) In the conventional method having the lock designation data memory, in order to execute the ladder program, the code of the instruction to be executed is read from the program memory 1 and the processing right is given to the hardware or the firmware that processes the instruction. Transfer. The hardware or firmware that has received the processing right processes the instruction, and the sequential execution proceeds to read the instruction code to be executed next.

The final operation is a coil command that drives the coil contacts. When the processing right is transferred to the hardware or the firmware that processes the coil command, it is necessary to check the corresponding bits of the lock designation data memory 8 to determine whether the contact is locked. That is, even if the sequencer finishes debugging and enters the operation state or the trial operation state and all the locks are released, the lock designation data 8 is checked for the coil command.

For this reason, the processing of the coil instruction itself adds a check time of the lock designation data memory 8 to the operating state of the sequencer, which increases the processing time. The coil command has a high usage ratio in the ladder program, and the scan time becomes long. The check as to whether or not this is locked is performed every time the coil command is processed, and when it is not locked, it is a wasteful process.

An object of the present invention is to provide a sequencer that reduces the check time of the lock designation of the coil instruction and shortens the processing time.

(Second Problem) In the conventional system provided with the lock designation data memory, the processing by the instruction for the arithmetic unit 7 to write the calculation result to the data memory 2 is performed by referring to the lock designation data memory. Since the check is performed and it is determined whether or not the calculation result is written in the data memory, the calculation speed decreases.

For example, in the pipeline processing shown in the table below, the write instruction C is executed over a plurality of steps because the processing content is large. In this command C, step b
Then, the operand part of the instruction C is read (read) to the operand data access part 5, the lock specification data c ′ is read in step c, the presence or absence of lock specification is analyzed and the operand part of the instruction C is reread in step c + 1. ,
At step c + 2, the calculation result is written (written). The reason why this re-reading is necessary is that the memory element generally has a plurality of bit widths, and it is not possible to write only 1 bit of the operation result, so read modify write is performed.

[0025]

[Table 2]

Therefore, in the instruction for writing the operation result to the data memory 2, since the operand data read in advance cannot be directly used for the read modify write, the lock specifying data is read, the data is analyzed, and the lock is specified. Since it is confirmed that the calculation result is not written, the number of steps required for the processing is increased and the calculation speed is reduced.

Another object of the present invention is to provide a sequencer which reduces the number of processing steps when writing the operation result in the data memory and improves the operation speed.

[0028]

[Means for Solving the Problems]

(First invention) The present invention provides a lock designation data memory for forcibly individually turning on or off the contact data of a data memory, and uses the data in the memory when executing the ladder program. In a sequencer for debugging the above, a coil instruction process for checking the lock designation data memory and executing an instruction when there is even one lock designation, and a check for the lock designation data memory when there is no lock designation at all There are two types of coil command processing, namely, a coil command processing that executes a command without performing a lock command, and a lock flag that indicates on / off whether or not there is even one lock designation in the data memory. In order to process the coil command of the ladder program, the two types of coil commands are selected depending on whether the lock flag is turned on or off. And executes switch processing.

(Second Aspect) The present invention provides a sequencer for executing a ladder program by pipeline processing by providing a lock designation data memory for individually forcibly turning on or off the contact data of the data memory. The pipeline processing determines whether or not the analysis result after instruction fetch is an instruction for writing operation data in a data memory,
In the case of an instruction to write to the data memory, in the next step, instead of reading data from the data memory, switching to reading lock designating data from the lock designating data memory is performed.

[0030]

BEST MODE FOR CARRYING OUT THE INVENTION

(First Embodiment) In the present embodiment, as the processing of the coil instruction by the hardware processing method, the firmware processing method, or the microcode processing method, when there is even one lock specification, the lock specification data memory is checked and the instruction is issued. There are two types of coil command processing, that is, a coil command processing for executing the command and a coil command processing for executing the command without checking the lock specification data memory when there is no lock specification.

The lock designation in the data memory 2 is 1
A lock flag indicating whether or not there is even one or not at all is prepared, and this lock flag is used for instruction decoding when the processing right is transferred to the coil instruction. The lock flag is secured as a hardware register or as a firmware flag, and can be switched between on and off depending on the man-machine interface section of the sequencer or an instruction from the man-machine interface section.

In the above-described configuration, the coil command is processed by the hardware or the like which has received the processing right, depending on whether the lock flag is on or off. Switch and execute.

For example, in the hardware processing system shown in FIG. 1, an output signal of a lock flag is input to the input of the decoder 4A when the instruction code is decoded, in addition to the instruction code, and the lock flag is turned on / off. And analysis unit 4
And the operation of the calculation unit 7 is switched. That is, depending on the lock flag, the lock designated data memory 8 is switched between checked execution and unchecked execution.

In the firmware processing method, a software table is generally used when converting an instruction code into an instruction code processing code entry. A lock flag is added to the input code of this table and the lock flag is turned on. -Switching between two types of entries (one that checks the lock designation data and one that does not check the lock designation data) prepared in the firmware for processing the lock instruction depending on whether it is off.

Further, in the microcode processing system, the output signal of the lock flag is input to the input of the decoder circuit for decoding the instruction code in addition to the instruction code, and the lock instruction is processed by turning the lock flag on and off. Two types of microcode entries are prepared, and the lock designation data is checked and unchecked.

Therefore, according to the present embodiment, when the ladder program is created and debugging is performed for the trial run of the plant, the lock designation memory can be checked by the lock flag.

When the plant is in the operating state and the coil instruction in the state where the contact (memory) locked during debugging is unlocked, the lock designation memory is not checked, so that there is no wasteful processing, and the speed is increased. it can.

The present embodiment can be applied not only to the memory lock by the contact instruction but also the memory lock by the numerical operation instruction. In the numerical operation command, two types of write commands (commands that check the lock-specified memory and commands that do not check) are prepared and used, instead of the coil command at the time of the contact command.

(Second Embodiment) Table 3 below shows the pipeline processing according to the present embodiment.

[0040]

[Table 3]

As shown in Table 3 and Table 2, the analysis unit 4 is executing the analysis of the instruction C in step a. By this analysis, it can be analyzed that the instruction C is an instruction to write the operation result to the data memory 2.

Therefore, in this embodiment, as shown in Table 3, when the analysis unit 4 analyzes that the instruction C is a write instruction in step a, in the next step b, the operand data of the instruction C is read ( The operand data access unit 5 is instructed to read the data C ′ in the lock designation data memory 8 instead of the conventional method.

By this instruction, the analysis unit 4 can read the lock designation data C ′ read from the data buffer 5B from the data register 6, and in the next step c, the analysis unit 4 analyzes the lock designation data C ′. In parallel with this, the operand data access unit 5 executes the instruction C
Can lead.

If the analysis result by the analysis unit 4 is not the lock designation, the calculation result is written in the data memory 2 in the next step c + 1.

Therefore, in the present embodiment, when the operation result is an instruction for writing the result in the data memory 2, the execution is reduced by one step as compared with the conventional pipeline processing.
The calculation speed can be improved.

FIG. 2 shows a block diagram for realizing the present embodiment with a hardware configuration. 1 is different from FIG. 1 in that the upper digit of the data given from the instruction fetch section 3B to the data pointer 5A of the operand data access section 5 of the operand section is performed via the adder 5D. When the analysis result of 4 is a write command to the data memory 2, the lock designation address addition value is bias-added.

The analysis unit 4 adds the lock designation address when the instruction is writing to the data memory 2,
The lock designation data read from the lock designation data memory 8 is fetched from the data register 6.

Instead of the adder 5D, the output of the data pointer 5A may be switched to the lock designation data memory 8 in the analysis after the instruction fetch.

[0049]

As described above, according to the present invention, the lock designation data memory for individually and forcefully designating the contact data of the data memory to be turned on or off is provided, and the data in the memory is stored when the ladder program is executed. When debugging a ladder program using it, the instruction processing that checks the lock specified data memory and the instruction processing that does not check it are prepared, and the instruction processing is switched depending on whether the data memory has a lock specification. In the coil command in, the check of the lock designation data memory is omitted and unnecessary processing is eliminated, so that the processing can be speeded up.

Further, according to the present invention, when the lock designation data memory is provided and the ladder program is executed by pipeline processing, the pipeline processing is an instruction in which the analysis result after the instruction fetch writes the operation data in the data memory. If it is an instruction to write to the data memory, the next step is to switch to reading lock designation data from the lock designation data memory instead of reading data from the data memory. It is possible to improve the calculation speed by reducing the number of execution steps of.

[Brief description of the drawings]

FIG. 1 is a block diagram of a sequencer according to the present invention.

FIG. 2 is a block diagram of a sequencer according to the present invention.

FIG. 3 is an example of a ladder circuit of a sequencer.

FIG. 4 is an example of a program memory of a sequencer.

FIG. 5 shows an example of a data memory of a sequencer.

[Explanation of symbols]

 1 ... Program memory 2 ... Data memory 3 ... Instruction fetch unit 4 ... Analysis unit 5 ... Operand data access unit 6 ... Data register 7 ... Arithmetic unit

Claims (2)

[Claims] 1. A sequencer provided with a lock designation data memory for individually forcibly turning on or off the contact data of the data memory, and debugging the ladder program by using the data in the memory when executing the ladder program. In the coil command processing for checking the lock specified data memory and executing the command when there is even one lock specified, and for executing the command without checking the lock specified data memory when the lock is not specified at all. Two types of coil command processing, which are the coil command processing to be executed, are prepared, and a lock flag that indicates whether or not there is even one lock designation in the data memory is provided by turning it on and off. For the processing of, the two types of coil command processing are turned off depending on whether the lock flag is turned on or off. A sequencer characterized by being replaced. 2. A sequencer for providing a lock designation data memory for forcibly individually turning on or off the contact data of a data memory and executing a ladder program by pipeline processing, wherein the pipeline processing is instruction fetch It is determined whether the subsequent analysis result is an instruction to write the operation data to the data memory, and if it is an instruction to write to the data memory, in the next step, instead of reading the data from the data memory, the lock specified data memory A sequencer characterized by switching to reading lock specification data.