JPH0916399A - Computer - Google Patents

Abstract

PURPOSE: To execute processing at high speed without wasting processings hitherto executed at the time of recovery even when interrupting processing is generated by providing a control means for reading the middle processing result from a storage means and an instruction executing means for executing an instruction after the middle processing result read by the control means. CONSTITUTION: When no interruption is generated, the instructions are successively executed in the other of respective stages by a control circuit 14. When a certain instruction is put into a pipeline and interrupting processing is generated during successive execution, the middle processing result of the instruction under executing is stored in a storage means such as registers 10-13, an interim processing result is read from the registers 10-13 or the like after the interrupting processing is executed, and the instruction is executed from the following register position. Therefore, even when the interrupting processing is generated, recovery efficiency is improved without wasting processings hitherto executed. As a result, processing speed is accelerated and processing efficiency can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer that executes instructions by pipeline processing.

[0002]

2. Description of the Related Art Conventionally, a computer that executes an instruction in a pipeline has been required to be improved because it takes time to recover when an interrupt process occurs.

In a conventional computer, an internal adder (arithmetic unit) executes an instruction. When an interrupt occurs during the execution of an instruction, the instruction is processed as shown below. That is, as shown in FIG. 4, a pipeline including an F stage, a D stage, an E stage, and a W stage has a plurality of instructions, for example, instructions 1, 2,
When 3, 4, 5, 6 etc. are sequentially issued and executed and an interrupt is generated by an external interrupt signal, the instructions 3, 4, 5, which were input to the pipeline when the interrupt occurred
All 6 are canceled, and the processing result and information in the process at this time are also lost. That is, all the instructions being executed and the processing results are invalidated.

Therefore, in order to re-execute the previously canceled instruction after the interrupt processing is completed,
The invalidated instruction must be reintroduced into the pipeline from the beginning, that is, from instruction 3.

[0005]

However, this has a problem that not only the processing time of the instruction that has been executed up to that point is wasted, but also the loss for re-inputting the instruction occurs and the processing becomes slow. .

The present invention has been made in order to solve such a problem. Even if an interrupt process occurs, a computer capable of executing the process at high speed without wasting the process up to that point at the time of restoration. It is intended to be provided.

[0007]

In order to achieve the above object, a computer according to a first aspect of the present invention is a computer that sequentially inputs and executes instructions in a pipeline consisting of a plurality of stages.
Storage means for storing the instruction processing result of each stage of the pipeline; and, when interrupt processing occurs while the instruction is being sequentially executed by each stage of the pipeline, the instruction processing result of each stage is stored in the storage means. Control means for storing and executing the interrupt processing, and for reading the intermediate processing result stored in the storage means; and instruction executing means for executing an instruction after the intermediate processing result read by the control means. It has.

According to a second aspect of the present invention, in a computer that sequentially inputs and executes instructions in a pipeline consisting of a plurality of stages, a storage means for storing a value of a register in the pipeline, and the instruction is the pipe. When interrupt processing occurs during sequential execution by each stage of the line, the value of the register in the pipeline is stored in the storage means, and after the interrupt processing is executed, the value of the register stored in the storage means. And a command execution unit that sets the value of the register read by the control unit to each register in the pipeline and executes the command from that position.

[0009]

According to the present invention, when an instruction is input to the pipeline and an interrupt process occurs during execution, the intermediate processing result of the instruction being executed is stored in the storage means. Then, after the interrupt processing is completed, the intermediate processing result is read from the storage means and re-executed from the instruction after the processing result.

In addition, when an instruction is input to the pipeline and is being executed,
When interrupt processing occurs, the value of the pipeline register of the instruction being executed is stored in the storage means. After the interrupt processing is completed, the value of that register is set in each register and the instruction is re-executed from that position.

Therefore, even if interrupt processing occurs,
It takes no time to recover, and the processing up to that point is not wasted.

As a result, the processing speed can be increased and the processing efficiency can be improved.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a computer according to an embodiment of the present invention.

In the figure, reference numeral 1 is a register for storing an instruction. Reference numeral 2 is a decoder (logic circuit), which decodes the instruction stored in the register 1 to generate the register file 3
A signal designating a register for reading data from and a signal designating a register for writing a calculation result are generated. 3 is a register file, which internally has a register R
It has 16 registers of 0 to register R15, and stores data necessary for calculation and calculation result. Reference numeral 4 denotes a register in which a signal designating a register in which the calculation result generated by the decoder 2 is stored and a storage permission signal in the register file 3 are stored. Reference numeral 5 is a register in which the data read from the register file 3 is stored.
Reference numeral 6 is a register in which the data read from the register file 3 is stored. An adder (ALU) 7 adds the register values of the registers 5 and 6 and stores them in the register 9. This adder 7 has an instruction fetch (F
The pipeline consists of four stages: stage), decode (D stage), execution (E stage), and write (W stage). Reference numeral 8 is a register in which the signal from the register 4 is stored. 9 is a register, and the adder 7
The result calculated in is stored. 10, 11, 12, 1
3 is a register, and registers 8 and 9 according to the control signal
The value of is stored. Reference numeral 14 denotes a control circuit, which generates a control signal for sequentially storing the operation result of the canceled instruction in the registers 10, 11, 12, and 13 when the pipeline cancellation occurs.

In this computer, the adder 7 executes the following instructions.

Instruction 1 ... ADD (R0, R1, R8); Instruction 2 ... ADD (R1, R2, R9); Instruction 3 ... ADD
(R2, R3, R10); instruction 4 ... ADD (R3, R
4, R11); instruction 5 ... ADD (R4, R5, R1
2); instruction 6 ... ADD (R5, R6, R13); instruction 7
... ADD (R6, R7, R14); instruction 8 ... ADD (R
7, R0, R15); instruction 9 ... ST (R8, 100)
0); instruction 10 ... ST (R9, 1010);

Here, ADD is an addition instruction. For example, if ADD (R0, R1, R2), it indicates that the value of register R0 and the value of register R1 are added and stored in register R2. ST is a store instruction, for example, ST
If it is (R0, 1000), it indicates that the value of the register R0 is written to the address 1000 of the memory.

The initial state of the register file 3 is as follows.

Register R0: 0 × 0, Register R1: 0
X1, register R2: 0x2, register R3: 0x3,
Register R4: 0x4, Register R5: 0x6, Register R6: 0x6, Register R7: 0x7, Register R
8: 0 × 8, register R9: 0 × 9, register R10:
0xA, register R11: 0xB, register R12: 0
× C, register R13: 0 × D, register R14: 0 ×
E, register R15: 0 × F.

In this computer, it is assumed that the interrupt processing is executed from the instruction a to the instruction f, and then the normal processing is restored.

Next, the operation of this computer will be described with reference to FIGS.

In the case of this computer, as shown in FIG. 2, when the interrupt does not occur, the control circuit 14 causes the F
Instructions 1 to 9 are sequentially executed in the order of stage → D stage → E stage → W stage.

On the other hand, during the above instruction processing, if an interrupt occurs at the time when a certain instruction is processed, the following instruction processing is performed.

That is, as shown in FIG.
When the control circuit 14 receives an interrupt signal (true value 0) from the outside in the stage, the processing of each stage of the instruction 3 to the instruction 6 is canceled.

However, the instruction processing up to the E stage is performed in the same way as when the interrupt is not entered.

At this time, in the W stage, the register file 3
The result of instruction 3 instead of being written to
The result of instruction 4 is stored in register 11, the result of instruction 5 is stored in register 12, and the result of instruction 6 is stored in register 13.

That is, at the time when the W stage of the instruction 6 is completed, the operation result in the register 10 is 0 × 5, the register file number is “10”, the operation result in the register 11 is 0 × 7, and the register file number is “0”. 1
1 ", the register 12 has a calculation result of 0x9, the register file number is" 12 ", the register 13 has a calculation result of 0xB, and the register file number is" 1 ".
3 "is written in this way, so that the processing result in the middle of calculation and the write register file number are registered in the register 1
It is written in the storage means such as 0, 11, 12, and 13.

Then, when the instruction a to the instruction f and the like are executed and the instruction is executed from the instruction 3 at the time when the interrupt processing is completed and returned, the instruction Z is executed instead of executing the instruction 3.
Execute

This instruction Z stores the execution result of the canceled instruction (instructions 3, 4, 5, 6 in the embodiment) in the register 1
It is an instruction to extract from 0, 11, 12, and 13 and write to the register file 3.

After the instruction Z is executed, the location counter (not shown) is set so that the next instruction is executed from the instruction 7. If the process does not branch,
For example, when returning to the original routine without any error, the value obtained by adding 1 to the address of the current instruction is used as the address of the next instruction, and when executing instruction Z, adding 4 to the current address. Let the value be the address of the next instruction. That is, after instruction 3, instruction Z is executed, and then instruction 7 that is obtained by adding 4 to instruction 3 is executed. The number 4 changes depending on the number of pipeline stages and the instruction execution mode.

Therefore, as shown in FIG. 3, the instruction 7 is executed next to the instruction Z. As described above, according to the computer of the present embodiment, when an interrupt is generated during the sequential execution of a certain instruction in the pipeline, the intermediate processing result of the instruction being executed is stored in the registers 10, 11, 12, 13 and the like. Even if interrupt processing occurs, even if the interrupt processing occurs, the intermediate processing results are read from the registers 10, 11, 12, 13 and the like and are executed after the interrupt processing is executed. The process up to is not wasted, and the recovery efficiency is improved.

As a result, the processing speed can be increased and the processing efficiency can be improved.

The present invention is not limited to the above embodiment.

For example, when an instruction is input to the pipeline and an interrupt process occurs during execution, the value of each pipeline register in which the instruction being executed is canceled, that is, registers 1, 4, 5, 6, 8, 9, 10, 11, 12, 13
Are stored in a storage means such as a memory, and after execution of the interrupt instruction, the registers 1, 4, 5,
The values of 6, 8, 9, 10, 11, 12, 13 may be read and the instruction executed from that register location.

In this case, although it is necessary to store the values of all the pipeline registers, it is possible to speed up the processing and improve the processing efficiency without wasting the processing until the interrupt processing occurs as in the above embodiment. You can

[0037]

As described above, according to the present invention, the value of the pipeline register to be canceled and the result of the intermediate processing of the instruction are stored in the storage means when the interrupt processing occurs during the execution of the instruction in the pipeline. After the completion of the interrupt processing, the value of the pipeline register and the intermediate processing result of the instruction are read from the storage means and the instruction is executed from the register position.
At the time of restoration, the processing up to that point is not wasted and the restoration efficiency is improved.

As a result, the processing can be executed at high speed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a computer according to an embodiment of the present invention.

FIG. 2 is a diagram showing instruction processing when an interrupt does not occur in this computer.

FIG. 3 is a diagram showing instruction processing when an interrupt occurs at instruction 3 in this computer.

FIG. 4 is a diagram showing instruction processing when an interrupt occurs in a conventional computer.

[Explanation of symbols]

1, 4, 5, 6, 8, 9, 10, 11, 12, 13 ... Registers, 2 ... Decoder (logical circuit), 3 ... Register file, 7 ... Adder (ALU), 14 ... Control circuit.

Claims (2)

[Claims] 1. A computer that sequentially inputs and executes instructions in a pipeline having a plurality of stages, and a storage unit that stores an instruction processing result of each stage of the pipeline; and the instruction is stored in each stage of the pipeline. Running sequentially,
When an interrupt process occurs, a control unit that stores the instruction process result of each stage in the storage unit, reads the intermediate process result stored in the storage unit after executing the interrupt process, and the control unit. A computer comprising: an instruction executing unit that executes an instruction after the read intermediate processing result. 2. A computer that sequentially inputs and executes instructions in a pipeline consisting of a plurality of stages, and storage means for storing register values in the pipeline, and the instructions are sequentially executed by each stage of the pipeline. During,
When an interrupt process occurs, the control unit stores the value of the register in the pipeline in the storage unit, and after executing the interrupt process, reads the value of the register stored in the storage unit; And a command execution means for setting the value of the register read by the above to each register in the pipeline and executing the command from that position.