JPS6242301B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a program control device for a microcomputer.

(Constitution of Conventional Example and its Problems) It is very effective to provide a program control circuit in a microcomputer that repeatedly executes a certain machine language a preset number of times. When a microcomputer with such a control circuit performs so-called string processing, for example, when comparing two consecutive meaningful words of data, the machine language for comparison is executed repeatedly for the number of words. do it. Therefore, when performing a comparison using string processing, it is only necessary to store only one machine language for comparison in the program memory, which not only improves the efficiency of program memory usage but also makes it easier to create string processing programs. It becomes easier.

As described above, as a program control method for repeatedly executing a certain machine language a preset number of times, a counter (hereinafter referred to as a repeat counter) for setting the number of repetitions is provided in the control circuit. There is a method (hereinafter referred to as repeat processing) in which the value of the program counter indicating the address of the program memory currently being executed is not changed until the value of the repeat counter becomes zero. Therefore, the instruction at the same address, that is, the same machine language, continues to be executed until the value of the repeat counter becomes zero. An example of implementing such a control method is Intel's 16-bit microcomputer 8086. On the other hand, when such a control method is adopted, a problem arises in relation to so-called interrupts. When an interrupt occurs, the value of the program counter is usually saved, the address of the interrupt destination is newly set in the program counter, and processing of the interrupt destination is started. When the interrupt destination process is completed, the saved value is returned to the program counter. As a result, the program before the interrupt is executed again. When such an interrupt occurs during repeat processing, no problem occurs if the operator and operand of the instruction undergoing repeat processing are stored in the program memory at the same address. However, when repeat processing is generalized, it may be possible to store only one operator in memory and sequentially store operands to be processed by this operator. However, the interrupt during this repeat processing does not operate normally. For example, as shown in FIG.
Assume that memory addresses ds ₁ 2, dd ₁ 3, ds ₂ 4, and dd ₂ 5 are stored at address 4 as operands. Assume that an interrupt occurs when the program counter indicates the value n+3 after completing the comparison between the contents 6 of the ds ₁ address and the contents 7 of the dd ₁ address in the repeat process. After the interrupt occurs, the value of the program counter, n+3, is saved. After the interrupt destination processing is performed, the saved value n+3 is restored to the program counter. However, since a new instruction code has been fetched into the instruction register during processing at the interrupt destination, instruction code 1, which instructs comparison, no longer exists in the instruction register after returning from the interrupt. Therefore, the microcomputer will not operate correctly after returning from the interrupt. A possible method to prevent this is to not perform interrupt processing during repeat processing. However, interrupts generally require quick response and processing, and therefore it is problematic to prohibit interrupts during repeat processing.

(Objective of the Invention) An object of the present invention is to eliminate the drawbacks mentioned in the conventional example and to provide a program control device capable of processing interrupts even when repeat processing is performed in a format having multiple operands after an operator. It's about doing.

(Structure of the Invention) A program control device of the present invention includes a memory for storing an instruction group including a first instruction for instructing repeated execution and a second instruction to be repeatedly executed, and data, and an address signal for the memory. a program counter that temporarily stores an instruction in the memory indicated by the program counter; and an instruction register that is preset by the first instruction;
a repeat counter whose value is decremented by 1 each time execution of the second instruction is completed; and a repeat counter that is set when the repeat counter is first decremented by 1 and reset when the contents of the repeat counter become zero. When an interrupt is received while the flag and the repeat flag have been reset, the contents of the program counter, the repeat counter, and the repeat flag at that time are saved to the memory and the repeat counter is , means for resetting the repeat flag and, when an interrupt is received while the repeat flag is set, saving the contents of the instruction register to the memory before saving them; , when returning from an interrupt, first restore the contents of the repeat counter and the repeat flag from the memory, and if the restored repeat flag is in a reset state, restore the contents of the program counter from the memory; The present invention is characterized by comprising means for restoring the contents of the program counter and the contents of the instruction register from the memory if the restored reset flag is in the set state.

With the above configuration, by referring to the repeat flag that is set from the time when the repeat counter is first decremented by 1 until the content of the repeat counter becomes zero,
Saving the contents of the program counter, the repeat counter, and the repeat flag to the memory when an interrupt is received at the end of execution of one of the second instructions being repeatedly executed; In addition to resetting the repeat flag, it is determined whether or not the contents of the instruction register are to be saved to the memory, and in the return processing from the interrupt, the repeat flag returned from the memory is referred to. By doing so, by determining whether or not to restore the contents of the instruction register from the memory in addition to restoring the program counter and the repeat counter from the memory, the second instruction Even when there is an operand indicated by the program counter, there is an effect that interrupt processing is possible.

(Description of Embodiment) FIG. 2 shows an embodiment of the present invention. memory 8
stores instructions or operation data, and a program counter 9 indicates the execution address of the program stored in the memory 8. instruction register 10
temporarily stores the contents of the memory 8 indicated by the program counter 9 as an instruction code. The repeat counter 11 is set with an initial value from the data bus 12, and then the instruction register 1
Each time an instruction code that is stored as 0 is executed, its value is decremented. Repeat flag 13 is
After the initial value is set in the repeat counter 11, the instruction code stored in the instruction register 10 is repeatedly executed. This is the flag that is reset. Stack pointer 14 connects memory 8 and address bus 15
When an interrupt occurs, the program counter 9,
A means for saving the repeat counter 11, repeat flag 13, etc. is realized. That is, when an interrupt occurs, the aforementioned program counter 9 and the like are stored in the memory 8 at the address indicated by the stack pointer 14. The interrupt flag 16 is a flag that is set based on external conditions and reset by the output of the control section 17 when interrupt processing is started. The control unit 17 inputs the outputs of the instruction register 10, the repeat flag 13, and the interrupt flag 16, and the zero detection signal 18 indicating that the content of the repeat counter 11 is zero, and controls each of the above-mentioned components. Control.

FIG. 3 shows an example of the configuration of the control section 17 shown in FIG. 2. The cycle counter 19 is a counter that is reset when the instruction code is stored in the instruction register 10, and then incremented every machine cycle. PLA (Programmable
Logic Array) 20 inputs the instruction register 10, cycle counter 19, interrupt flag 16, repeat flag 13, and zero detection signal 18, decodes these with its AND part, and outputs various control signals 21 from the OR part. do. In addition, in order to operate the control unit 17 at the timing described later, the PLA2
A zero input is synchronized using latch 22, which is enabled by clock T2, which will be described later.

FIG. 4 shows the operation timing of the embodiment shown in FIG. 2. 1 machine cycle from T0 to T4
It consists of five clocks. The memory 8 is accessed between T0 and T1, and the instruction code is stored in the instruction register 10 at T1. Also, at this time, the cycle counter 19 is reset. After the instruction code is stored in the instruction register 10, the cycle counter 19 is counted up at timing T1. T2 is the timing for decoding the PLA 20, and the synchronization latch 22 provided at the input section of the PLA 19 is enabled. T3 and T4
is used to take out data from the memory 8 onto the data bus 12 or to write the contents of the data bus 12 into the memory 8. In other words, access to memory 8 starts from timing T3,
Data is output to the data bus 12 at timing T4. Conversely, the contents of the data bus 12 are written to the memory 8 at timing T4. Also T4
At this timing, the repeat counter 11 is set to an initial value from the data bus 12, or its value is decremented. Repeat flag 13
is set and reset at timing T3.

FIG. 5 shows an example of the structure of the repeat counter 11 and repeat flag 13 according to the timing shown in FIG. The down counter 23 has a preset data input terminal 24 and a preset enable terminal 2.
5, has a countdown clock input terminal 26, a reset terminal 27 and an output terminal 28. When the preset enable terminal 25 becomes "1", the down counter 23 outputs the preset data input terminal 24.
The value of is set in the internal flip-flop. Thereafter, when the countdown clock input terminal 26 becomes "1", the down counter 23 decrements its value. The output 28 of the down counter 23, that is, the output of a flip-flop (not shown) constituting the down counter 23, is outputted to the data bus 12 through an output buffer 29. The output 28 of the down counter 23 is also connected to a zero detection circuit 30. The zero detection circuit 30 is
When all inputs are zero, the output 31 is set to "1". The gate 32 outputs T4 when the control signal PRES33 or POP34, which is the output of the control unit 16, is “1”.
At this timing, the preset enable terminal 26 is set to "1". Here, the control signal PRES33 becomes "1" when the instruction to set the initial value in the down counter 23 is executed, and the control signal POP34 becomes "1".
becomes "1" when returning from interrupt processing.
The gate 35 receives a control output which is an output of the control section 16.
At T4 timing when DEC36 is "1" and the content of down counter 23 is not zero,
The countdown clock input terminal 26 is set to "1". Here, when the instruction stored in the instruction register 10 is capable of repeat processing, the control signal DEC36 becomes "1" at each last machine cycle while the instruction is executed for several machine cycles or once. This is output by programming the PLA 20 so that The repeat flag 13 is composed of a flip-flop 37 and an output gate 38. As shown in FIG. 5, at timing T3 when the control output DEC36 is "1", if the content of the down counter 23 is not zero, the output REP3 of the flip-flop 37 is
9 becomes "1", and if the content of the down counter 23 is zero, REP 39 becomes "0". The output REP39 of the flip-flop 37 is also set or reset depending on the contents of the data bus 12 at timing T4 when the control signal POP34 is "1". The control signal PSH40, which is the output of the control unit 16, becomes “1” during interrupt processing and becomes T4.
The contents of the repeat counter 11 and repeat flag 13 are output to the data bus 12 at the appropriate timing.
These values are then stored in the memory 8 at the address indicated by the stack pointer 14. Thereafter, the control signal RES41 becomes "1" and the repeat counter 11 and repeat flag 13 are reset. In addition, the output signal ZERO of the zero detection circuit 30
18 is connected to the control section 17 as described above.

FIG. 6 is a time chart showing an example of the operation of the repeat counter 11 and repeat flag 13 when the program shown in FIG. 1 is executed.
When the instruction to set the initial value to the repeat counter is stored in the instruction register 10, this is stored in the control unit 17.
The control signal PRES33 is output. At this time, as shown in FIG. 6, the output of the gate 32 becomes "1" at timing T4 of the machine cycle 41, and the contents of the data bus 12 are preset in the down counter 23, and therefore the zero detection circuit 3
The output of 0 becomes "0". Here data bus 12
The above data is part of the contents of the memory 8 or the instruction data stored in the instruction register 10, and is set to 2 in this case.

Between T2 of machine cycle 42 and T1 of machine cycle 43, the contents of memory at addresses ds 1 and dd 1 are compared using ds ₁ and dd ₁ , and the contents of memory at addresses n+ ₁ and n+ ₂ are compared, and repeat processing 1 is performed. End the episode. The value of the program counter at the end becomes n+3. Machine cycle 43 T1
In this case, a new instruction code is originally taken into the instruction register 10, but when the output of the zero detection circuit 30 is "0", by programming the PLA 20 so as not to take it in, the comparison instruction 1 is read again from machine cycle 44. is executed. Further, in the machine cycle 43, the PLA 20 is programmed so that the control signal DEC36 becomes "1". Therefore, at T4 of the machine cycle 43, the output of the gate 35 becomes "1" and the value of the repeat counter becomes "1". Further, at T3 of machine cycle 43, since the output 31 of the zero detection circuit 30 is "0", the repeat flag becomes "1", indicating that the first repeat process has been completed.

Between T2 of machine cycle 44 and T1 of machine cycle 45, the contents of memory at addresses n+3 and n+4, ds ₂ 4 and dd ₂ 5, are output, and the contents of memory at address ds _2, 46, and the memory at address dd ₂ are output. The contents 47 are compared and the second repeat process is completed. Furthermore, the operations of the repeat counter 11, repeat flag 13, and instruction repeat counter 10 are as follows.
This is the same as the case of the first repeat process. However, since the content of the repeat counter 11 becomes zero at T4 of the machine cycle 45, the output of the zero detection circuit 30 becomes "1". Furthermore, the value of the program counter 9 when the machine cycle 45 ends is n+5.
becomes.

The third or final repeat process is performed from machine cycle 48 to machine cycle 49. And machine cycle 49 T3
Since the output of the zero detection circuit 30 is "1", the output of the repeat flag 13 is "0". In this way, the repeat flag 13 becomes "1" from the end of the first repeat process to the end of the final repeat process. The value of the program counter at the end of machine cycle 49 is n+7.

At T2 of machine cycle 50, the output of the zero detection circuit 30 is "1" and the value of the program counter is n.
+7, so new instruction 51 is in instruction register 1.
Stored at 0.

Next, interrupt processing will be described. When the interrupt flag 16 is set, the control section 17 decodes it and starts interrupt processing. At the time of an interrupt, the PLA 20 is programmed to follow the procedure shown in FIG. That is, repeat flag 13
is “1”, the value of stack pointer 14 is set to 1.
instruction register 1 in memory 8 indicated by this value.
Save the contents of 0. Next, stack pointer 14
The value of the program counter 9 is decreased by one and the contents of the program counter 9 are saved in the memory 8 indicated by this value. Furthermore, the value of the stack pointer 14 is decremented by one, and the control signal
The PSH 40 is set to "1" and the repeat counter 11 and repeat flag 13 are saved in the memory 8. After the evacuation, the control signal RES41 is set to "1" and the repeat counter 11 and repeat flag 13 are reset. Finally, by setting the execution address of the interrupt destination in the program counter 9, execution of the interrupt destination program is started. If the repeat flag is "0", the instruction register 10 is not saved. Therefore, for example, when the interrupt flag 16 is set at T2 of the machine cycle 44 in FIG. 6, the control section 17 outputs a control signal in accordance with FIG. 7 from then on. Therefore, the memory 8 contains a comparison instruction 1, a program counter 9 with a value of n+3, a repeat counter 11 with a value of 1, and a repeat flag 13 with a state of "1".
is stored.

An interrupt return instruction is stored at the end of the interrupt destination program. The PLA 20 is programmed to output a control signal according to the procedure shown in FIG. 8 using this interrupt return command. That is, first, the values of the repeat counter 11 and repeat flag 13 saved in the memory 8 are restored. Next, the value of the stack pointer 14 is incremented by one, and the value of the program counter 9 saved in the memory 8 is restored. Then, the value of the repeat flag 13 that is returned first is determined, and if the value is "1", the stack pointer 14 is further incremented by one, and the instruction code saved in the memory 8 is transferred to the instruction register 10. By returning, this instruction code is executed. If the value of the restored repeat flag 13 is "0", the contents of the memory 8 indicated by the restored program counter 9 are stored in the instruction register 10 without returning to the instruction register 10. Next, as an example, consider a case where a program that starts interrupt processing at timing T2 of the machine cycle 44 shown in FIG. 6 returns from the interrupt. The control section 17 outputs a control signal according to the procedure shown in FIG. Therefore, first, the values of the repeat counter 11 and repeat flag 13 are restored from the memory 8. Therefore, the value of repeat counter 11 is 1 and repeat flag 13.
The value of is "1". Next, the value of the program counter 9 is restored from the memory 8 and becomes n+3. now,
Since the restored repeat flag 13 is "1", the instruction code is further restored from the memory 8,
Comparison instruction 1 is stored in instruction register 10 .
Then, the memory 8 whose value ds ₂ 4 is pointed to by the value n+3 of the program counter 9 is accessed. That is, the second repeat process that was interrupted due to the interrupt is started.

(Effects of the Invention) As described above, according to the present invention, in a microcomputer that can perform string processing using an instruction format in which one operator and a plurality of operands are successively stored in the memory at the following address, Interrupts are possible even when the program counter does not indicate the operator of the instruction currently being executed, but only the operand. That is, by referring to the repeat flag that is set from when the repeat counter is first decremented by 1 until the contents of the repeat counter become zero, one of the second instructions being repeatedly executed is When an interrupt is accepted at the end of execution, the contents of the program counter, repeat counter, and repeat flag are saved to memory, and in addition to resetting the repeat counter and repeat flag, the contents of the instruction register are saved to memory. A decision is made as to whether or not to perform the process. In the process of returning from an interrupt, by referring to the repeat flag returned from memory, it is determined whether or not to restore the contents of the instruction register from memory in addition to restoring the program counter and repeat counter from memory. make a judgment. As a result, even when the second instruction has an operand indicated by the program counter, interrupt processing is possible. Therefore, string processing can be performed without impairing the interrupt function, which is provided for starting a program that requires an urgent need. Further, in order to realize these functions, the main hardware that must be added to the conventional microcomputer program control device is a down counter and a flip-flop, and there is no significant increase in hardware.

[Brief explanation of the drawing]

Fig. 1 shows an example of a repeat processing program, Fig. 2 shows an embodiment of the present invention, Fig. 3 shows an example of the configuration of the control section in Fig. 2, and Fig. 4 shows an embodiment of the invention. Figure 5 shows an example of the configuration of the repeat counter and repeat flag in Figure 2.
Fig. 6 shows the timing when the program shown in Fig. 1 is executed in one embodiment of the present invention shown in Fig. 2, and Fig. 7 shows the timing when executing the program shown in Fig.
The control procedure programmed in the PLA is
The diagram shows the steps in Figure 3 to perform interrupt recovery processing.
The control procedures programmed into the PLA are shown below. 8...Memory, 9...Program counter, 10...
Instruction register, 11...Repeat counter, 13...
Repeat flag, 14...Stack pointer, 2
3...down counter, 30...zero detection circuit, 37...
Flip flop.

Claims (1)

[Claims] 1. A memory that stores an instruction group including a first instruction that instructs repeated execution and a second instruction that is to be repeatedly executed, and data; a program counter that provides an address signal to the memory; and a program counter that provides an address signal to the memory; an instruction register that temporarily stores instructions in memory; a repeat counter that is preset by the first instruction and whose value is decremented by one each time execution of the second instruction is completed; and the repeat counter whose value is initially decremented by one. A repeat flag is set when the program is executed, and is reset when the contents of the repeat counter become zero, and when an interrupt is received while the repeat flag is reset, the program counter at that time is set. , the contents of the repeat counter and the repeat flag are saved to the memory, the repeat counter and the repeat flag are reset, and when an interrupt is accepted with the repeat flag set, Prior to these saves, means for saving the contents of the instruction register to the memory, and upon returning from an interrupt, first restoring the contents of the repeat counter and the repeat flag from the memory; means for restoring the contents of the program counter from the memory if the repeat flag is in the reset state, and restoring the contents of the program counter and the contents of the instruction register from the memory if the restored repeat flag is in the set state; A program control device comprising: