JPS5947651A - Program controller - Google Patents

Abstract

PURPOSE:To ensure an interruption even under the repeating processing in a style having plural operands, by saving and resetting a program counter, a repeating counter and a repeating flag when an interruption is set. CONSTITUTION:When an interruption flag 16 is set from outside under execution of repeating process, a control part 17 shunts an instruction register RG10 to an address of a memory 8 which is shown by the value obtained by subtracting 1 from the value of a stack pointer SP14. Then a program counter PC9 is saved to the address of the memory 8 having the value obtained by subtracting 1 from the value of the SP14. Furthermore, a repeating counter RC11 and a repeating flag RF13 are saved to the address of the memory 8 shown by the value obtained by subtracting 1 from the value of the SP14. Then the RC11 and RF13 are reset, and the address of an address receiver is set to the PC9. When the interruption is reset, the RC11 and RF13 are reset from the memory 8 in order reverse to the saving state and then reset to the PC9 and RG10 from the memory 8 of an address having the value obtained by increasing the SP14 one by one. Thus the normal program processing is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a program control device for a microcomputer.

(Constitution of Conventional Example and its Problems) It is very effective to provide a program control circuit in a microcomputer that repeatedly executes a certain machine language a preset number of times. When a microcomputer with such a control circuit performs so-called string processing, for example, when comparing two consecutive words of data, it repeatedly executes the machine language for the comparison for the number of words. do it. Therefore, when performing a comparison using string processing, it is only necessary to store only one machine language for comparison in the program memory, which not only improves the efficiency of memory usage but also improves the efficiency of string processing programs. It is also easy to create.

As described above, as a nologram control method for repeatedly executing a certain machine code a preset number of times, a counter (hereinafter referred to as a repeat counter) for setting the number of repetitions is provided in the control circuit, and the repeat There is a method (hereinafter referred to as repeat processing) in which the value of a program counter indicating the address of the program memory currently being executed is not changed until the value of the counter becomes zero.

Therefore, the instruction at the same address, that is, the same machine language, continues to be executed until the value of the repeat counter becomes zero.

An example of implementing such a control force method is Intel's 16-bit microcomputer 808b. A problem that arises when such a control method is adopted is the relationship with so-called interrupts. When an interrupt occurs, the value of the program counter is usually saved, the address of the interrupt destination is newly set in the program counter, and processing of the interrupt destination is started. When the interrupt destination process is completed, the saved value is returned to the 70 program counter. As a result, the program before the interrupt is executed again. When such an interrupt occurs during repeat processing, no problem occurs if the operator and operand of the instruction undergoing repeat processing are stored in the program memory at the same address. However, when repeat processing is generalized, it may be possible to store only one operator in memory and sequentially store operands to be processed by this operator.

However, the interrupt during this repeat processing does not operate normally. For example, as shown in Figure 1, an instruction code 1 that specifies a comparison as an operator in the memory at address n is written as an operand at addresses n121 to n+4, which is the memory address ds12+dc113+ds.
24 + ddz 5 is stored.

In the repeat process, it is assumed that an interrupt occurs when the comparison between the content 6 of address ds1 in the memory and the content 7 of address dd is completed, and when the glogram counter indicates the value n+3. After an interrupt occurs, the value of the program counter, n+
3 is saved. After the interrupt destination has been processed,
The saved value n+3 is restored to the 70 program counter. However, since a new instruction code has been added to the instruction renoster during the processing at the interrupt destination, the instruction code 1 that instructs the comparison does not already exist in the instruction renoster after returning from the interrupt. Therefore, after returning from an interrupt, the microcontroller will not work properly for a while.A way to prevent this is to handle interrupts during repeat processing.
One possible method is not to do so. However, interrupts generally require quick response and processing, and therefore it is problematic to stop interrupts during repeat processing. .

(Objective of the invention) The purpose of the present invention is to eliminate the drawbacks mentioned in the conventional example, and to prevent interrupts from occurring even when repeat processing is performed in a format that has multiple The object of the present invention is to provide a program-controlled device capable of processing.

(Structure of the Invention) A program control device of the present invention includes: a memory that stores a series of instructions and data; a program counter that indicates an execution address of the instruction group stored in the memory;
An instruction renostar that takes in an instruction stored in the memory and instructed by the program counter when the value of a repeat counter (to be described later) is zero; A repeat counter that is reset and decremented by 1 each time an instruction is executed until its value becomes zero, and
- The initial value of the counter is set to 1, and the value is 61'i.
A flag is set after 11 instructions stored in the instruction renoster have been executed and is reset after the value of the repeat counter reaches zero, and when an interrupt occurs while the flag is reset, i/( saves the contents of the program counter, the repeat counter, and the flag, and resets the repeat counter 011, and when the flag is set, further saves the contents of the instruction renoster and resets the flag. means for resetting, and means for first restoring the flag when returning from an interrupt, restoring the program counter and the repeat counter if the flag is in a reset state, and further restoring the instruction renoster if the returned flag is in a set state; It is characterized by having the following.

(Description of Embodiment) FIG. 2 shows an embodiment of the present invention. The memory 8 stores instructions or operation data, and the program counter 9 indicates the execution address of the program stored in the memory 8. The instruction register 10 temporarily stores the contents of the memory 8 indicated by the program counter 9 as an instruction code. The repeat counter 11 is set with an initial value from the r-tapus 12, and thereafter decrements the value each time the instruction code stored in the instruction register IO is executed until it becomes zero. The repeat flag 13 is set at the end of the first execution in the process of repeatedly executing the instruction code stored in the nostar 10 after the initial value is set in the repeat counter 11. This is a flag that is reset when execution is complete.

The stack pointer 14, together with the memory 8 and the address bus 15, is used to register the program counter 9, repeat counter 11 . A means for evacuating the repeat flag 13, etc. is realized. That is, when an interrupt occurs, the aforementioned program counter 9 and the like are stored in the memory 8 at the address indicated by the stack pointer 14. The interrupt flag 16 is a flag that is set by an external condition and reset by the output of the control unit 17 when interrupt processing is started. The control unit 17 inputs the outputs of the instruction reno star 10, the repeat flag l:3, and the interrupt flag 16, and the zero detection signal 18 indicating that the content of the repeat counter 11 is zero, and controls each of the above-mentioned components. control.

FIG. 3 shows an example of the configuration of the control section 17 shown in FIG. 2.

The cycle counter 19 is a counter that is reset when an instruction code is stored in the instruction reno star IO, and is incremented every 1 machine cycle thereafter. P
LA (Programmable Logic Array)
) 20 is an instruction register 10. cycle counter 19
, an interrupt flag 16, a repeat flag 13, and a zero detection signal 18 are input, these are decoded by the AND section, and various control signals 21 are outputted from the OR section. In addition, for convenience of operating the control unit 17 at the timing described later,
The inputs of the PLA 20 are synchronized using a latch 22 enabled by a clock T2, which will be described later.

FIG. 4 shows the operation timing of the embodiment shown in FIG. 2. One machine cycle is constructed using five clocks from TO to T4. The memory 8 is accessed between TO and TI, and the instruction code is stored in the instruction recorder 10 at T1. Also, at this time, the cycle counter 19 is reset. After the instruction code is stored in the instruction register 1o, the cycle counter 19 is incremented at the timing Tl. T2 is a timing for decoding the PLA 20, and the synchronization latch 22 provided at the input section of the PLA 19 is enabled. T3 and T4 are used to take out data from the memory 8 onto the data bus 12, or to write the contents of the data bus 12 into the memory 8. In other words, from the timing of T3, memory 8
Access is started, and data is output to the data bus 12 at timing T4. Conversely, the contents of the data bus 12 are written to the memory 8 at timing T4.

Further, at the timing T4, the repeat counter 11 is set to an initial value from the data bus 12, or its value is decremented. Repeat flag, T 3 is T
It is set and reset at timing 3.

FIG. 5 shows an example of the repeat counter 11 and repeat flag 13 according to the timing shown in FIG. The down counter 23 has a counter input terminal 24, a preset enable terminal 25, a countdown clock input terminal 26, a reset terminal 27, and an output terminal 28. When the reset enable terminal 25 becomes “l”,
The down counter 23 sets the value of the hit data input terminal 24 to an internal value of .70.

After that, the countdown clock input terminal 26 becomes It I
When the value reaches II, the down counter 23 decrements the value. The output 28 of the down counter 23, that is, the fritsuno flop 0 constituting the down counter 23
(not shown) is output to data bus 12 through output buffer 29. Output 2 of down counter 23
8 is also connected to the zero detection circuit 30. The zero detection circuits 30i-t set their outputs 31 to 1 when all inputs are zero.
When the control signal PRES 33 or POP 34, which is the output of the control unit 16, is 1, the gate 32 outputs T4.
At the same time, set the preset enable terminal 26 to
”.Here, the control signal pRgs 33 is “
The control signal POP 34 becomes '1' when returning from the interrupt processing. Gate 35 is control 1 part 1
The control output DEC36, which is the output of 6, is II II II, and at the T4 timing when the content of the down counter 23 is not zero, the countdown clock is input to the input terminal 7-
26 as 111 II. Here the control signal ]) EC3
6 is such that when the instruction stored in the instruction renoster 10 is capable of repeat processing, the instruction becomes "1" in each last machine cycle while the instruction is executed over several machine cycles. It is output by programming PLA 19 in the 0 program. repeat flag 1
3 is composed of a Fritzno flop 37 and an output gate 38. As shown in Fig. 5, the control output DEC
At the T3 timing when 36 is °゛l'', if the contents of the down counter 23 are not zero, then the
7's output REP 39 becomes 9'1''', and if the content of the down counter 23 is zero, REP 39 becomes 1°0.
”. The output REP 39 of the Fritsuno flop 37 is also set or reset depending on the contents of the data bus 12 at timing T4 when the control signal POP 34 is II I IT.

The control signal PSH40, which is the output of the control unit 16, becomes P1'' during interrupt processing and outputs the contents of the repeat counter 11 and repeat flag 13 to the data bus 12 at timing T4. Then, the control signal PE541 becomes l''' and the repeat counter 11 and repeat flag 13 are reset. Further, the output signal ZERO18 of the zero detection circuit 30 is connected to the control section 17 as described above.

FIG. 6 is a time chart showing an example of the operation of the repeat counter 11 and repeat flag 13 when the program shown in FIG. 1 is executed.

When an instruction to set an initial value to the repeat counter is stored in the instruction reno star IO, this is decoded by the control unit 17 and a control signal PRES 33 is output.

At this time, as shown in FIG. 6, the machine cycle 410T4
At this timing, the output of the gate 32 becomes 1'', the contents of the data bus 12 are preset in the down counter 23, and therefore the output of the zero detection circuit 30 becomes 10''. Here, the data on the data bus 12 is the contents of the memory 8 or a part of the instruction code stored in the instruction recorder 10, and is assumed to be 2 in this case.

From T2 of machine cycle 42 to T of machine cycle 43
1, the contents of memory at addresses n+1 and n+2 ds
ds1 address and dd using 1 and dd.

The contents of the memory at the address are compared and the first repeat process is completed. And the value of the program counter at the end is n
It becomes +3. At T1 of machine cycle 43, a new instruction code is originally taken into the instruction recorder 10, but when the output of the zero detection circuit 30 is 0'', P
By programming LA 20, comparison instruction 1 is executed again from machine cycle 44. Also, in machine cycle 43, the control signal DEC36 or II
Program the PLA 20 so that it becomes II. Therefore, in machine cycle 430T4, the output of the gate 35 is l'' and the value of the 9 repeat counter is l.In addition, in machine cycle 43, T3, the output 31 of the zero detection circuit 30 is 1'0'', so the repeat flag is 1”, indicating that the first repeat process has been completed.

Machine cycle 44 T2 to machine cycle 450T
1, the contents of memory at addresses n+3 and t++4 d
H4 and dd25 are output, the contents 46 of the memory at address ds2 and the contents 47 of memory at address dd2 are compared, and the second repeat process ends. Further, the operations of the repeat counter 11, the repeat flag 13, and the instruction register 10 are the same as in the case of the first repeat process. However, at T4 of machine cycle 45, repeat counter 11
Since the content of is zero, the output of the zero detection circuit 29 is '°1''
becomes. Furthermore, the value of the glogram counter 9 when the machine cycle 45 ends is n-1-5.

The third or final repeat process is performed from machine cycle 48 to machine cycle 49.

In machine cycle 490T3, the output of the zero detection circuit 30 is l", so the output of the reheat flag 13 is 1.
''.In this way, the repeat flag 13 becomes +11 I+ from the end of the first repeat process to the end of the last time.The value of the Zoroku Ram counter at the end of the machine cycle 49 is It becomes n+7.

At T2 of machine cycle 50, the output of zero detection circuit 30 is +
1111 and the value of the program counter is n+7, so a new instruction 51 is stored in the instruction register 10.

Next, interrupt processing will be described. When the interrupt flag 16 is set, the control unit 17 precodes it and starts interrupt processing. At the time of an interrupt, the PLA 20 is programmed so as to follow the procedure shown in FIG. That is, if the reheat flag is 13 or "Ill", the value of the stack pointer 14 is decreased by 1, and the contents of the instruction register 10 are saved in the memory 8 indicated by this value.Next, the value of the stack pointer 14 is decreased by 1, and this value is The contents of the program counter 9 are saved in the memory 8 indicated by .Furthermore, the value of the stack pointer 14 is decremented by one, and the control signal PSH40 is set to "1", and the repeat counter 11 and repeat flag 13 are saved in the memory 8.And after saving sets the control signal RES 41 to "L" and resets the repeat counter 11 and reheat flag 13. Finally, by setting the execution address of the interrupt destination in the program counter 9, execution of the program of the interrupt destination is started., -! , or the beat flag is "θ", the instruction register 10 is not saved. Therefore, for example, when the interrupt flag 16 is set at T2 of the machine cycle 44 in FIG. A control signal is output according to the figure.Therefore, the memory 8 stores a comparison instruction 1, a program counter 9 with a value of n+3, a repeat counter 11 with a value of ■, and a reheat flag 13 with a state of 1''. Ru.

An interrupt return instruction is stored at the end of the interrupt destination program (7). This interrupt return instruction causes the PLA 2 to output a control signal according to the procedure shown in FIG.
Program 0. That is, first, the values of the repeat counter 11 and repeat flag 13 saved in the memory 8 are restored. Next, the value of the stack pointer 14 is incremented by one, and the value of the program counter 9 saved in the memory 8 is restored. Then, the value of the repeat flag 13 returned first is judged, and if the value is "l", the stack pointer 14 is further incremented by one, and the instruction code saved in the memory 8 is returned to the instruction register 10. This instruction code is executed by executing this instruction code. If the value of the returned repeat flag 13 is 9°0'', the return to the instruction register 10 is not performed, and the contents of the memory 8 pointed to by the returned program counter 9 are executed. Store in instruction register 10. Next, as an example, consider a case where a program that starts interrupt processing at timing T2 of the machine cycle 44 shown in FIG. 6 returns from an interrupt. The control section 17 outputs a control signal according to the procedure shown in FIG. Therefore, first, the values of the reheat counter 11 and repeat flag 13 are restored from the memory 8. Therefore, the value of the repeat counter 11 is 1, and the repeat flag is 1.
The value of 3 becomes 1''. Next, the value of the zologram counter 9 is restored (flj) from the memory 8 and becomes n + 3. Since the repeat flag 13 that has just been restored is 1'', the value of the zologram counter 9 is further retrieved from the memory 8. The instruction code is returned from , and the comparison instruction l is stored in the instruction renoster 10. Then, the memory 8 whose value ds24 in the memory 8 pointed to by the value n+3 of the zologram counter 9 is accessed. Start the second repeat process.

(Effects of the Invention) As described above, according to the present invention, a microcomputer can perform string processing using an instruction format in which a plurality of operands are successively stored in the memory of one operator and the following address. In the above, an interrupt is possible even when the zologram counter does not indicate the operator of the currently executing instruction but only indicates the operand. In other words, string processing can be performed without impairing the interrupt function, which is provided for starting a program that requires an urgent need.

Further, in order to realize these functions, the main hardware that must be added to the conventional microcomputer program control device is a down counter and a frig 70 horn, and there is no significant increase in hardware.

[Brief explanation of the drawing]

Fig. 1 shows an example of a repeat processing program, Fig. 2 shows an embodiment of the present invention, Fig. 3 shows an example of the configuration of the control section in Fig. 2, and Fig. 4 shows an embodiment of the invention. Figure 6 shows an example of the configuration of the repeat counter and repeat flag shown in Figure 2, and Figure 6 shows the example of the program shown in Figure 1 in an embodiment of the present invention shown in Figure 2. Figure 7 shows the timing of execution, and Figure 8 shows the control procedure programmed into the PLA in Figure 3 to perform interrupt processing.
The control procedures programmed in the PLA in FIG. 3 to perform interrupt recovery processing are shown below. 8...Memory, 9...Program counter, lo...
Instruction reno star, 11... Repeat counter, 13...
Repeat flag, 14...Stack pointer, 23
...Down counter, 30...Zero detection circuit, 37...
Free ruff 0 flop. 258 Figure 4 T4

Claims (1)

[Claims] A memory for storing a series of instructions and data, a zologram counter for indicating the execution address of the instruction group stored in the memory, and instructions stored in the memo 1 and instructed by the program counter as described below. When the repeat counter is zero, the number of repeated executions of the instruction stored in the instruction register is reset as the initial value, and each time the instruction is executed, the instruction register is set to zero. a repeat counter that decrements by l until the initial value is preset to the repeat counter and the instruction stored in the instruction register is set after one instruction is executed, and the repeat counter is set after the value of the repeat counter becomes zero. The flag to be reset, and when an interrupt occurs while the flag is reset,
The contents of the program counter, the previous repeat counter, and the flag are saved, and the repeat counter is reset, and when the flag is set, the contents of the instruction register are saved, and the flag is reset. and means for first restoring the flag when returning from an interrupt, restoring the program counter and repeat counter if the flag is in a reset state, and further restoring the instruction renoster if the returned flag is in a set state. Program control device with.