JPH02187829A - Digital signal processor - Google Patents

Abstract

PURPOSE:To perform recovery from interruption completely by saving a program counter, a repeat flag stack, the count value and register value of each register before the execution of an interruption processing routine. CONSTITUTION:When the interruption is accepted, an interruption request is issued from an interruption control part 13 to a sequence control part 5. When the request is received, an instruction which performs no processing is set at an instruction execution control part 2, and also, the update of a program counter 3 is prohibited. And the count value of the counter 3 is automatically set at a PC stack 4, and also, an interruption address is set at the counter 3. Also, the register value of a repeat flag register 17 is automatically saved to the repeat flag stack 18. The saving of the register value of the register used in the interruption processing routine is performed at an interruption address destination, and it is performed by a register saving instruction. In such a way, the recovery from the interruption of an ordinary operation and under execution of a repeat instruction can be performed completely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a digital signal processing processor that performs arithmetic processing mainly on signal sequences.

[Conventional technology]

FIG. 4 is a simplified block diagram mainly showing the configuration of the audio signal processing processor (DSSPI), which was shown in the 1986 IEICE Communication Division National Conference Symposium Proceedings (NaS10-1), for example. In (1
) is an instruction memory in which instruction words are stored, (2) is an instruction execution control unit that controls operations such as decoding and calculation of instruction words, (
3) is a program counter that holds instruction addresses, (
4) is a PC stack that saves the return destination address during subroutine processing and interrupts, and this PC stack (
4) saves the instruction address (301) output from the program counter (3) immediately before the interrupt until the end of the interrupt process. (5) is a sequence control unit that is in charge of the entire control function, (6) is a repeat control unit that is in charge of counting processing during loop/repeat between sequence control unit (5), and (7) is a repeat instruction being executed. (8) is a program bus that transfers decoded control data, (9) is a data bus that transfers main data, (10) is a program bus (8) and a data bus ( 9) is a bus interface register that performs the connection, (11) is a data memory that stores calculation data, (12) is an arithmetic processing circuit that performs operations such as addition, subtraction, multiplication, and division, and (13) is an interrupt control that starts interrupt processing. part, (14) is an external interrupt request signal, (
15) is an external interrupt enable signal.

Next, the operation will be explained. - Signal processing processors for boat fishing have a pipeline structure for the purpose of improving processing speed; for example, in the case shown in the figure, it has a three-stage pipeline structure. Therefore, here, explanation will be given based on pipeline processing.

In the first stage of the pipeline, the instruction word (101) specified by the instruction address (301) output from the program counter (3) is read from the instruction memory (1) and sent to the instruction execution control unit (2). is input.

In the second stage of the pipeline, the instruction execution control unit (2
) decoded control signals and data are sent to each part.

In the third stage of the pipeline, control signals are used to read arithmetic data (111) from the data memory (11) to the data bus (9), write it from the pig bus to the data memory, and write the arithmetic data (111) in the arithmetic processing circuit (12). Various operations such as arithmetic processing are controlled.

The interrupt control unit (13) has three levels of interrupt functions in addition to RESET. RESET initializes control system registers such as the status register (SR), flag register (FR), interrupt, and bus control, as well as resetting the program counter (3).

Interrupt 0 (INTRO) is non-maskable,
When the lNTR0 signal is input, the program counter (
3) is set to address 1.

Interrupt 1 (INTRI) is maskable and RE
It is masked when either SET or 1NTR01I NTR1 is accepted, or by designation in the program. The mask is canceled by a program, and when this interrupt is accepted, the program counter (3) is set to address 2.

Interrupt 2 (lNTR2) is maskable and is a normal interrupt with an acknowledge function.

RESET, lNTR0, INTRI and lNTR2
is accepted or masked by program settings. Unmasking is done programmatically,
When this interrupt signal is accepted, an acknowledge signal (
I NTA 2 ) is output, and the program counter (
3) is set to address 3.

Now, the instruction word to be executed next to the normally executed instruction word is the instruction address (3) where the executed instruction word was stored.
01) plus rlJ.

Therefore, in the first stage of the vibe line, the instruction address (301
) is “+1” by the adder, and the instruction address (301
) is created by adding "1" to the address.

Generally, in a processor having a vibe line structure, there is a delay due to the vibe line until instruction execution is completed.

For example, as shown in FIG. 5, in the machine cycle at time Tn, a H/W interrupt request signal (14) is inputted from the outside to the interrupt control section (13).

When the external interrupt enable signal (15) is output from the interrupt control unit (13) due to the above input, the instruction word specified by the instruction address PC(n) is read, but the interrupt signal is not acknowledged. Therefore, in the machine cycle at time Tn+1, the instruction word stored at address n in the instruction execution control unit (2) is invalidated, and an instruction (n
o p).

Further, the program counter (3) is set to address 3 in the machine cycle at time Tn, and interrupt processing is executed. Before this interrupt processing is executed, the PC (n-
1), the execution of the instruction word specified by PC(n) has not been completed, and the program counter (3) and each key register are not saved at the time of an interrupt, so complete recovery from the interrupt is not possible. It is possible.

[Problem to be solved by the invention]

Conventional digital signal processing processors with a vibe line structure are configured as described above, so if an external interrupt occurs during normal instruction execution, accurate data before the interrupt is not guaranteed, and the Once the interrupt is taken, the remaining repeat instructions will not be executed. This poses problems such as a decrease in processing efficiency in the field of image signal processing, which requires execution of external H/W interrupts, high-speed processing of large amounts of data, and accurate calculation results. Ta.

This invention was made with the aim of solving the above-mentioned problems.It suppresses the decrease in processing speed and increase in the number of instruction steps, and transfers each register value saved at the time of interrupt to each register when returning from an interrupt. An object of the present invention is to obtain a digital signal processing processor that can be completely restored after a complete recovery.

[Means to solve the problem]

The digital signal processing processor according to the present invention has a plurality of register saving memories in which each register data is saved when an interrupt is executed, and enables accurate data transfer to each register when returning from an interrupt, and also has a memory for saving each register when an interrupt is executed. An interrupt control unit that controls a complete return from interrupt processing by restarting execution for the remaining number of repeats even after the interrupt returns, and an interrupt enable control that provides an interrupt disable period that disables H/W interrupts even when not during interrupt processing. It is equipped with a section.

[Effect]

The register saving memory in this invention writes the register value of each register after completing the instruction that has already been executed when an interrupt occurs, and the interrupt control unit writes the register value to the register saving memory when the interrupt ends. In addition to restoring the value to each register, even if an interrupt occurs during the execution of a repeat instruction, the repeat instruction can be executed for the remaining number of repeats after the return, and the enable control unit can execute branch instructions and return instructions when there is a memory wait while accessing external data memory. - By providing an interrupt prohibition period that prohibits external interrupts during decoding and execution of software included instructions, it is possible to improve the processing capacity of a digital signal processor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, the same or equivalent parts as in FIG. 4 are given the same reference numerals, and redundant explanation will be omitted.

(16) is a register save memory where the data of each register is saved when an interrupt is executed, and (17) is a repeat flag register (rfr) that indicates that a repeat instruction is being executed.
, (18) is a repeat flag stack (rfsk) for saving when an interrupt is accepted, and (19) is a back repeat counter (rfsk) for holding the initial number of repeats.
ch) and (20) are interrupt enable control units that perform automatic disable processing of interrupts when interrupts are activated.

The register saving memory (16) is a memory that appropriately holds only the register values of registers that need to be saved in the interrupt processing routine. Further, the interrupt enable control unit (20) is a control unit that automatically inhibits H/W interrupts during external data memory access and execution of branch instructions, return instructions, and S/W interrupt instructions.

Next, the operation of H/W interrupt processing will be explained based on FIG. When an interrupt request occurs in the external device, the external device notifies the interrupt control unit (13) of the occurrence of the interrupt using an interrupt request signal (14).

When an interrupt is accepted, an interrupt request is issued from the interrupt control section (13) to the sequence control section (5). When this interrupt request is received, the instruction execution control unit (
2) sets an instruction to do nothing and prohibits updating of the program counter (3).

Next, the interrupt control unit (13) sends an interrupt enable signal (15) to the external device, basically prohibiting H/W interrupts during interrupt processing.

Note that this is replaced with an instruction that does nothing in the sequencer control unit (5). In addition to interrupt processing, the interrupt enable control unit (20) automatically disables interrupts during memory wait cycles during access to external data memory, and during decoding and execution of branch instructions, return instructions, and S/W interwoven.

When an interrupt is accepted, an instruction to do nothing is set in the instruction execution control unit (2), the count value of the program counter (3) is automatically bushed in the PC stack (4), and the interrupt address is set in the program counter. set.

In the case of an interrupt during repeat, it is also necessary to remember the state of the repeat flag register (17) at that time.
The register value of the repeat flag register (7) is automatically saved to the repeat flag stack (18) so that interrupts can be accepted even during execution of a repeat instruction.

The register value of the register used in the interrupt processing routine is saved by using the interrupt address light and by a register save instruction (push). Return from an interrupt is performed by a return instruction (r t i), but before this return instruction, a register value return instruction (p o
p) sets the register values before the interrupt processing routine in each register.

Thereafter, a return instruction returns from the interrupt.

At this time, the program counter (
3), pops the count value, sets an instruction to do nothing in the instruction execution control unit (2), and then restores the register value of the repeat flag register (17) from the repeat flag stack (18).

FIG. 2 is a timing chart for explaining the normal interrupt operation. FIG. 3 is a timing chart for explaining the interrupt operation during execution of a repeat instruction. In the second stage of the repeat instruction, the register value of the repeat flag register (17) is set to "1", and the back repeat counter ( 19) is subtracted by "1" and set to repeat.

At this time, the program counter (3) is not updated in the first stage of the instruction word specified by the instruction address PC (n+1). In addition, in the second stage, if the repeat flag register (17) is set to "1", the count value of the back repeat counter (19) is subtracted by "1" and becomes 0.
Test whether. If it is 0, execute the same instruction.

When an interrupt is accepted, an instruction to do nothing is set in the instruction execution control unit (2), and the repeat flag register (
The register value of 17) is the repeat flag stack (18)
PC (n+1) is saved to PC stack (4). After the interrupt, the count value of the repeat counter (7) is saved in the register save memory (16) by a register save instruction.

Before the interrupt processing routine is completed, the saved count value of the repeat counter (7) and each register value are set in each register by a register value return instruction. Upon return from an interrupt, the instruction address PC(n+1) is popped from the program counter stack (4) to the program counter (3) by the S/W return instruction, and
Further, an instruction to do nothing is set in the instruction execution control unit (2) as the next instruction. Then repeat flag stack (
18) to the repeat flag register (17).

As a result, "1" is set in the repeat flag register (17).
Since -C is set, the repeat counter (7) is decremented by 1 and becomes 1, and the repeat] instruction is re-executed.

As described above, by performing the processing as in this embodiment for external H/W interrupts, it is possible to completely recover the processor even for normal interrupts and interrupts during execution of repeat instructions, and it is possible to prevent a decrease in processor processing efficiency.

In the above embodiment, the number of repeats is set to 4, and an interrupt is generated during the repeat. However, it is possible to completely return from an interrupt immediately after the repeat instruction is executed, and immediately before the end of the repeat instruction. You may interrupt.

Further, it is clear that the detailed specifications of the above embodiments are unrelated to the essence of the invention and do not limit the content of the invention.

〔Effect of the invention〕

As described above, according to the present invention, the program counter, the repeat flag stack, and the count value and register value of each register are saved before the interrupt processing routine, so that the program counter, the repeat flag stack, and the count value and register value of each register are saved. Complete recovery is possible, and the interrupt disable period can be automatically inhibited by the interrupt enable control section, which has the effect of making it possible to improve the processing capacity of the digital signal processor.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of a digital signal processing processor according to an embodiment of the present invention, FIG. 2 is a timing chart for explaining the normal interrupt operation of the present invention, and FIG. 3 is a repeat instruction execution of the present invention. 4 is a block diagram showing the configuration of a conventional digital signal processing processor. FIG. 5 is a timing chart illustrating the normal interrupt operation of a conventional digital signal processing processor. It is. In the figure, (1) is instruction memory, (2) is instruction execution control unit, (3) is program counter, (4) is PC stack, (7) is repeat counter, (11) is data memory, (13) is is the interrupt control unit, (16) is the register save memory, (17) is the repeat flag register, (
18) is a 1 beat flag tap, (19) is a back repeat counter, (20) is an enable control unit, (301)
is the instruction address. In the figures, the same number 71 indicates the same or equivalent parts. Agent Patent attorney Masuo Oiwa (2 others) Return return 7 command nop command pc (n〒1) Timing diagram of 4N interrupt operation Figure 2 pc-Interrupt address rfr←rfsk pop (-1) Rita/ Instruction PC(n+1) pc(in-mouth 2) PC(n+3) Timing chart of interrupt operation during execution of libbit instruction Figure 3 Procedural amendment (spontaneous) Claims and scope of the specification to be amended Column for detailed description of the invention. 6. Contents of the amendment 2. Name of the invention Digital signal processing processor 3. Name of the person making the amendment Nei (601) Mitsubishi Electric Corporation Representative Moriya Shiki 4. Proxy address Tokyo 2-2-3 Marunouchi 2-chome, Chiyoda-ku, Tokyo and above Claims: An instruction memory in which command words instructing various internal operations are stored in advance, and an instruction execution control for controlling operations such as calculations instructed by the command words. a data memory that stores operation data; an operation section that performs an operation on the operation data as instructed by the instruction word and outputs the result and status of the operation; a program counter that holds an instruction address; A PC stack that saves the count value of the program counter during interrupt processing; a repeat counter that counts the number of repeats during execution of the repeat instruction; a repeat flag register that indicates that the repeat instruction is being executed; and a register of the repeat flag register. A repeat flag stack that saves values during interrupt processing; a plurality of register save memories that save register values of each register during interrupt processing; By saving the count value and the register value of the repeat flag register, complete recovery from the interrupt is realized. If a normal instruction is being executed during the interrupt processing, the instruction address is saved in advance and the user can perform the interrupt processing. An interrupt control unit that controls complete recovery from interrupt processing by saving the register values of each register used in routines, and a memory wait cycle during external data memory access, branch instruction return instructions, and S/W interrupts. A digital signal processing processor comprising: an interrupt enable control unit that inhibits H/W interrupts during instruction decoding and execution.

Claims (1)

[Scope of Claims] An instruction memory in which instruction words instructing various internal operations are stored in advance; an instruction execution control unit that controls operations such as operations instructed by the instruction words; and data for storing operation data. a memory; an arithmetic unit that performs an operation specified by the instruction word on the operation data and outputs the result and status of the operation; a program counter that holds an instruction address; and an interrupt processing unit that processes the count value of the program counter. A PC stack that is saved at the time of execution, a repeat counter that counts the number of repeats during execution of a repeat instruction, a repeat flag register that indicates that the repeat instruction is being executed, and a repeat flag that saves the register value of the repeat flag register during interrupt processing. a stack; a plurality of register saving memories for saving the register values of each register during the interrupt processing; and, if a repeat instruction is being executed during the interrupt processing, the count value of the repeat counter and the register of the repeat flag register are saved in advance; By saving the value, a complete recovery from the interrupt is realized, and when a normal instruction is being executed during the interrupt processing, the count of the repeat counter is saved in advance, and each register used by the user in the interrupt processing routine is saved. An interrupt control unit that controls a complete return from interrupt processing by saving the register values of An interrupt enable control unit that disables H/W interrupts of the digital signal processing processor.