JPS62209650A - Memory access system - Google Patents

Abstract

PURPOSE:To carry out other internal processing especially in a write mode by storing the write related information delivered from a processor together with a write instruction until a common bus is available. CONSTITUTION:When data are written to a memory 3, a processor 2 outputs a write instruction and also the write related information, i.e., the data to be written and the address information. The write related information is stored in a write information store means 4. Then the processor 2 is released from the access processing of the memory 3 and can perform other processing. While the write related information stored in the means 4 is used for the write processing that is carried out by a write control means (not shown here) which subjected to the write instruction, for example, and in its own memory access cycle.

Description

[Detailed Description of the Invention] [Summary] In a system in which processors access memory via a common bus, it is possible to improve the processing efficiency of a processor that can perform other processing in addition to memory access. Therefore, a write information storage means is provided which can store write-related information output together with write commands from the processor until the common bus becomes available.

[Field of Industrial Application] 1. The present invention relates to a memory access system in which a processor accesses memory via a common bus.

[Prior Art 1] Conventionally, this type of memory access system has been realized as part of a so-called multiprocessor system in which a common bus can be used by a plurality of processors. In this conventional system, when a processor accesses memory via a common bus, the state of the common bus is checked, and when the common bus is not occupied by another processor and becomes open, the processor checks the state of the common bus. I am trying to perform access processing.

[Problems to be Solved by the Invention] In the conventional memory access system, there is room to further improve the processing efficiency of a processor that can perform other processing in addition to memory access.

This is due to the following reasons.

The basic cycle of processing in a processor is generally shorter than the cycle of memory access processing, including processing on the common bus, and the processor continues to operate on its own until memory access processing, including processing on the common bus, is completely completed. The process of

Also, if another processor occupies the common bus when a processor attempts to access memory,
Keep the processing of the processor in question until the common bus is released.

Additionally, especially when writing to memory over a common bus,
Processing inconsistency should not occur even if the processor executes other internal processing before the write processing is completed.

Therefore, an object of the present invention is to enable the execution of other internal processing in the processor even before the writing processing including processing on a common bus is completed during memory access processing, especially during writing. That's true.

[Means for solving the problem] The present invention is based on a system in which the processor 2 accesses the memory 3 via the common bus 1, as shown in FIG. A technical means for solving the problem is to include a write information storage means 4 capable of storing write-related information output together with a write command from the processor 2 until the common bus 1 becomes available for use.

[Operation] When writing data to the memory 3, the processor 1 outputs write-related information, that is, the data to be written and address information, together with a write command, and this write-related information is stored in the write information storage means 4. Thereafter, the processor 2 is released from the memory 3 access process and becomes ready to perform other processes. On the other hand, the write-related information stored in the write information storage means 4 is subjected to write processing performed in its own memory access cycle by a write control means (not shown) that follows the write command, for example.

[Embodiments of the invention] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a circuit configuration diagram showing an example of a memory access system according to the present invention. This system includes means for storing n pieces of write data and addresses output from the processor.

In the figure, 10 is a processor, and this processor 10 outputs a memory request signal during access processing, especially write processing, to the memory 30, and also outputs write data, write address, and register set timing signals for registers as described below. It is designed to be output. Reference numeral 11 denotes a bus interface control circuit, and this bus interface control circuit 11 monitors the write command status in the processor 10 based on the status of the memory request signal from the processor 10, and also controls the data bus 35a1 and the address bus 35b. The state of memory write access on the configured common bus 35 is monitored, and when the write command in the processor 10 is completed, a write end signal WEND is output, while the actual memory write access on the common bus 35 is monitored. When the bus end signal BEND is completed, the bus end signal BEND is output.

12 is an n-ary up/down counter, and this up/down counter 12 is connected to the bus interface control circuit 11.
This light end signal WE is inverted by the inverter G1 of the bus end signal BEND from the bus end signal WE and is incremented by the right end signal WEND through the AND gate G2.
It is down-counted by the bus end signal QBEND via the AND gate G4 which is gate-controlled by the inverted signal from the ND inverter G3. Each n-ary output bit of the up/down counter 12 is input to an AND gate G5, and the memory request signal is input to a Nant gate G6 together with the output of the AND gate G5. The basic tarok signal is sent to the processor 10 via the AND gate G1 which is gate controlled by the output of the Nant gate G6.
, and all processing in the processor 10 is basically performed in synchronization with this OFF signal.

13 is an n-ary counter that counts the bus end signal BEND from the bus interface Mtl11 circuit 11;
14 is an adder that adds the output of the up/down counter 12 and the output of the counter 13, and 15 is a decoder that decodes the output of the adder 14. This decoder 15 is n
output terminals, and the output value from the adder 14 is +
<t-0, 1,..., n-1)
The t+1st output terminal is set to an H level state.

16 (1), 16 (2),...
..., 16(n) are n data registers capable of storing write data from the processor 10;
17(1), 17(2),..., 17 (n>
are n address registers that can store write addresses from the processor 10, and each data register 16
(j) and each address register 17(j) receives the write data in synchronization with the register set timing signal from the processor 10 via an AND gate 18(j) which is gate-controlled by the third output of the decoder 15. and a write address (here, j-1, 2, . . . , n). 1
8 is from each data register 16(1) to 16(n) -
A multiplexer 19 selects and outputs the data in the registers of the address registers 17(1) to 17(n
20 is a decoder that decodes the count value of the counter 13. This decoder 20 outputs information of ++1 for the count value i, and outputs the information of ++1 to each multiplexer 18. 19 selectively outputs data and addresses in each register 16 (1+1>, 17 (++1)) based on the decoded output ++1.

The write data selectively output from the multiplexer 18 is supplied to the data bus 35a via the driver 21, and the write address selectively output from the multiplexer 19 is supplied via the driver 22 to the address bus 35a.
5b, and the write data on the address data bus 35a of the memory 30 specified by the write address is written.

Next, the write operation in this system will be explained.

First, in the initial state, the up/down counter 12 and the counter 13 are each preset to "O".

Therefore, the output of the adder 14 is also "0", and accordingly, the first output terminal of the decoder 15 goes into the H level state, and the AND gate G8 (1) goes into the allowable state.
The decode output of the decoder 20 becomes "1'°, and the multiplexers 18 and 19 select the data register 16 (1) and the address register 17 (1), respectively.

In this state, the processor 10 executes the defined processing in synchronization with the basic tarok signal via the AND gate G1. In the process, when writing data to the memory 30, write data, a write address, and a register set timing signal are output together with a memory request signal. Then, the write data from the processor 10 is stored in the data register 16 (1) in synchronization with the register set timing signal via the AND gate G8 (1) that is in the permissible state, while the write data from the processor 10 is stored in the data register 16 (1). is stored in the address register 17(1) in synchronization with the register set timing signal. Then, as described above, when the processor 10 ends the write command by outputting the write data and write address and lowers the memory request signal, the bus interface control circuit 11 determines that the write command has ended in the processor 10, Outputs a light end signal WEND. Then, the up/down counter 12 counts up, the output becomes 1", the output of the adder 14 becomes "1", and accordingly, the decoder 1
The second output terminal of 5 becomes H level, and the AND gate G
8(2) is in the permissible state. At this time, counter 13
The count value of each multiplexer 18.19 does not change.
The selection status of does not change. That is, multiplexer 18.
19 holds the selected states of the data register 16(1) and address register 17(1), respectively.

Here, for example, if the common bus 35 is occupied by another processor, each register and multiplexer 18, 19 will continue to be in the above state, and the processor 10 that has completed the write instruction will perform other unique processing. Executes in synchronization with the basic lock signal. In such a state, when the processor 10 outputs the memory request signal as well as the write data, write address, and register set timing signal in order to write data to the memory 30 again, the write data is The data register 16 (
2), while the write address is stored in the same register.
The address register 17 is synchronized with the set timing signal.
(2).

When the write command in the processor 10 is completed by outputting the write data and the write address, the processor 10 lowers the memory request signal, and accordingly, the bus interface control circuit 11 outputs the write end signal WEND in the same manner as above. Output. Then, the up/down counter 12 counts up again and its output becomes "2", and accordingly, the third output terminal of the decoder 15 becomes H level, and the processor 10
AND gate G8(3), which is a control gate for the register set timing signal from , enters the allowable state.

Thereafter, if the common bus 35 continues to be occupied by another processor, the processor 10 will execute other unique processing each time the write command is completed. On the other hand, each time the write command ends, the up/down counter 12 is
is counted up, and based on the output "j", AND gate G8 (j + 1) enters the allowable state. Then, the write data and the paired write address from the processor 10 associated with the write command are synchronized with the register set timing signal via the AND gate G8 (j + 1), which is in the allowable state at that point. Data register 16 (j+1), address register 17 (j
+1) respectively.

Here, when the common bus 35 is no longer occupied by another processor, write access processing on the common bus 35 is started.

In the process described above, the output of the counter 13 holds "0", and based on this, the output of the decoder 20 causes the multiplexers 18 and 19 to select the data register 16 (1), respectively.
), address register 17(1) is selected. Therefore, when the write access process is started, the write data in the data register 16(1) is transferred to the multiplexer 1.
8, is supplied to the data bus 35a via the driver 21, and the write address in the address register 17(1) is supplied to the address bus 35b. Then, actual write address processing is performed based on the write data and address data supplied to the common bus 35, and the write data is written into the memory 30 at the address specified by the write address.

When the write access processing on the common bus 35 as described above is completed, the bus interface control circuit 11 detects the end of the processing and outputs a bus end signal BEND. Then, the counter 13 counts up and its output becomes "1", and accordingly, the output of the decode 20 becomes II 211, and the multiplexers 18 and 19 output the data register 16 (2) and the address register 17 (2), respectively.
> is selected. Therefore, in the next write access process, the write data stored in the data register 16(2) will be written to the address of the memory 30 specified by the write address stored in the address register 17(2) via the common bus 35. be included. Thereafter, the counter 13 is similarly incremented by the bus end signal BEND from the bus interface control circuit 11 every time the write access process is completed, and in the next write access process, the decoder 20 is incremented based on the count value 11j''. Data register 1 corresponding to output “j+1”
Write data in 6(j+1) is in address register 17
(j+1>) is written to the address in memory 30 specified by (j+1>) via common bus 35.

In the above process, the counter 13 is incremented every time the write access process is completed, and at the same time, the down counter 12 is incremented. Therefore, since the output of the adder 14 does not change and the AND gate G8(j) which is in the permissible state also does not change, the write data and write address accompanying the write command of the processor 10 are written in the order described above. It is stored in the data register 16(j) and address register 17(j).

Also, for example, when the common bus 35 is occupied by another processor, it remains open for a long time, and all data registers 16(1) to 16(n>) and address registers 17(1) to 17
When a write command is further issued from the processor 10 with the write data and write address stored in (n), the output of the AND gate G5 becomes H level, the output of the NAND gate G6 becomes L level, and the AND gate G7 is inhibited, and the basic clock signal to the processor 10 is cut off. As a result, the internal processing of the processor 10 is interrupted, and this state continues until the write access processing on the common bus 35 is completed, that is, until the up/down counter 12 counts down, as in the case of sub-back.

As described above, according to this embodiment, even if the common bus 35 is occupied by another processor for 6 seconds, the processor 1
The process related to the write command can be executed up to n times regardless of the state of the common bus 35, and during this time, the processor 10 can also execute other unique processes.

Further, even if the access cycle on the data bus 35 and the basic processing cycle of the processor are different, the processor 10 can execute processing related to its own write command and other processing regardless of the access cycle. Become.

FIG. 3 is a circuit configuration diagram showing another example of the memory access system according to the present invention.

In this example, an n-pit circular shift register 23 is used instead of the counter 13 in FIG. 2, and an adder 14 . Shifter 24 instead of decoder 15
It is configured with . Furthermore, each of these registers 23,
The functions realized by the shifter 24 are similar to those shown in FIG. 2, and its operation and effects are also similar to those of the embodiment shown in FIG.

[Effects of the Invention] As described above, according to the present invention, the write-related information output together with the write command from the processor can be stored until the common bus becomes usable. During access processing, particularly during writing, it becomes possible to allow the processor to execute other internal processing even before the writing processing including processing on the common bus is completed.

[Brief explanation of drawings]

FIG. 1 is a principle diagram of the present invention, and FIGS. 2 and 3 are circuit configuration diagrams showing an example of a memory access system according to the present invention. 1.35...Common bus 2.10...Processor 3.30...Memory 4...Write information storage means 11...Bus interface control circuit 12...Up/down counter 13...Counter 14,...Adder 15.20...Decoder 16(1) to 16(n)...Data register 17(1
)~17 (n)...Address register 18.19.
...Multiplexer 21, 22...Driver 35a...Data bus 35b...Address bus Patent applicant Fujitsu Limited Representative Patent attorney Sada Igata -,\4
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Claims (1)

[Claims] A processor (2) is connected to a memory (3) via a common bus (1).
), the system has a write information storage means (4) capable of storing write-related information outputted together with a write command from the processor (2) until the common bus (1) becomes available for use. A memory access system comprising: