JPS6156812B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a program counter control circuit with an input condition selector, and relates to a program counter control circuit with an input condition selector.
The present invention relates to a program counter control system with an input condition selector that reliably maintains a multi-bit conditional branch flag input to a selector at the time of a request (referred to as DMA) in the state immediately before the DMA request.

(b) Technical background What is a program counter with input condition selector?
A sequential circuit with an input condition selector, for which the applicant of this patent applied for a patent in 1957, is used as a program counter. The output of the FF is the output of the current state, and this and the input conditions of multiple bits are input to the ROM, and the output becomes the output of the next state. The ROM is provided with a selector for selecting a predetermined one bit from among the input conditions of the plurality of bits, and a means for outputting a selection signal for making this selection.
By setting the bit as the input condition of the ROM,
The capacity can be reduced. The present invention relates to a control system for this program counter with input condition selector.

(c) Prior art and problems Figure 1 is a block diagram of the main part of the control circuit of a conventional program counter with input condition selector.
The figure shows a time chart of each part in Figure 1, where A is the clock, B is the DMA request signal, and C is the FF.
8, D is a clock to FF3, E is a program address (input to ROM 4), F is a program instruction output (output from ROM 4), G is a multi-bit conditional branch flag, and H is a DMA enable signal.

In the figure, 1 is a program counter with an input condition selector, 2 is a ROM, 3 and 8 are FFs, 4 is a ROM containing a program, 5 is a selector, 6 is an AND circuit, 7 is a note circuit, and 9 is a delay circuit. .

In this circuit, when a DMA request signal is received as shown in FIG. 2B, the output of FF8 is delayed by half a period, and becomes a "1" output during DMA processing as shown in C. By using this signal and the AND circuit 6, FF3 is
Stop the clock. As a result, the program address to the ROM 4 is stopped at No. 2 as shown in E. On the other hand, with the output of FF8, the output of ROM4 is set as a NO-OPERATION command as shown in F, and the bus (not shown) in the processor is opened to enable DMA processing. The command outputs of ROM4 shown in F, No. 1, No. 2, and No. 3 correspond to program addresses No. 1, No. 2, and No. 3,
NOP indicates NO・OPERATION. Since the clock to FF3 is stopped, the multi-bit conditional branch flag output from selector 5 is output from DMA as shown in G.
Permission is granted and the program stops in state No. 4, just before DMA execution. G No.2, No.3, No.4 are the above program addresses, program command output No.2, No.3,
Each corresponds to No.4. The DMA permission signal indicated by H is output by the delay circuit 9 with a delay of one instruction execution time. Once the DMA processing is complete, the clock will turn off.
It is sent to FF3 and continues operating from the state immediately before DMA execution. However, during DMA execution, the conditional branch flag of No. 4, which is currently stopped, may change. Therefore, the 1-bit conditional branch flag output from selector 5 is also changed, and the DMA
When the processing is finished, the operation must be continued from the state immediately before the DMA execution, but the disadvantage is that the operation is different and cannot be continued.

(d) Object of the Invention The object of the present invention is to eliminate the above-mentioned drawbacks and to provide a program counter control system with an input condition selector that can reliably continue operation from the state immediately before DMA execution after completion of DMA processing.

(e) Structure of the Invention In order to achieve the above object, the present invention includes a program counter control circuit with an input condition selector, which includes a flip-flop that holds a multi-bit conditional branch flag to be input to the selector.
When a DMA request is made, the output of the delay circuit that grants DMA permission stops the clock to the flip-flop,
The present invention is characterized in that the conditional branch flag of the plurality of bits immediately before the DMA execution is held so that it does not change during the DMA execution.

(f) Embodiment of the invention An embodiment of the invention will be described below with reference to the drawings. FIG. 3 is a block diagram of the main parts of the program counter control circuit with input condition selector according to the embodiment of the present invention, and FIG. 4 is a time chart of each part of FIG.
A is clock, B is DMA permission signal, C is FF10
It is a clock to

Components in the figure that have the same functions as those in FIG. 1 are indicated by the same symbols. 10 is a FF, and 11 is an AND circuit.

The only difference between FIG. 3 and FIG. 1 is that an FF10 that holds a multi-bit conditional branch flag and an AND circuit 11 are provided to control the clock to the FF10. This is the same as the explanation for Figure 1. When the DMA request signal comes, the output of the delay circuit 9 which outputs the DMA permission signal as shown in B is added to the AND circuit 11, and the FF is inputted as shown in C.
The clock to 10 is stopped, and FF10 holds the multiple-bit conditional branch flag immediately before DMA execution. As a result, the conditional branch flag does not change during DMA execution.

Therefore, continuation processing can be reliably executed after the DMA processing is completed.

(g) Effects of the invention As explained in detail above, according to the present invention,
After the DMA processing is completed, it is possible to reliably continue processing from the state immediately before the DMA request.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main part of the control circuit of a conventional program counter with input condition selector.
The figure is a time chart of each part in Fig. 1, Fig. 3 is a block diagram of the main part of the control circuit of the program counter with input condition selector according to the embodiment of the present invention, and Fig. 4 is a time chart of each part in Fig. 3. be. In the figure, 1 is a program counter with input condition selector, 2 is ROM, 3, 8, 10 are FF, 4 is ROM containing the program, 5 is a selector, 6, 1
1 is an AND circuit, 7 is a NOT circuit, and 9 is a delay circuit.

Claims (1)

[Claims] 1 When a direct memory access request is made, the output of the first flip-flop holding this signal stops the clock to the program counter, disables the instruction indicated by the program counter, and outputs the first flip-flop. In a program counter control circuit with an input condition selector that uses the output of the delay circuit that delays the direct memory access permission signal as a direct memory access permission signal, inputting the output to the selector;
An input condition selector comprising a second flip-flop holding a multi-bit conditional branch flag, and stopping the clock to the second flip-flop at the output of the delay circuit when a direct memory access is requested. Program counter control method.