JPH0711782B2 - Micro program control system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a micro program control system thereof.

(Prior Art) Conventionally, in a data processing device adopting a micro program control method, a micro order for memory access is issued when a memory is accessed, and thereafter, in order to synchronize with a memory operation timing, A memory waiting order was issued. As a result, the execution of the microprogram is delayed and synchronized with the operation of the memory.

Therefore, if the memory access time is long, the memory wait order is issued after executing the internal processing for the minimum memory access clock after issuing the memory access order. The calculation operation was parallelized to improve the processing efficiency.

(Problems to be Solved by the Invention) In the conventional microprogram control method described above, when the system includes both high-speed memory and low-speed memory, the memory queuing order is issued after the memory access order is issued. The time interval until it is determined is determined by the operation timing of the high speed memory.

For this reason, there has been a drawback that the parallelism between the memory operation and the internal operation operation is lowered during low speed memory access.

An object of the present invention is to have a plurality of micro orders for activating memory access and a queuing order for waiting for memory access, and comparing the memory address at the time of issuing the memory access activating order with a fixed value. It is an object of the present invention to provide a microprogram control method configured to eliminate the drawbacks and control whether the actual access activation to the memory is performed at the time when the microorder is issued or invalidated.

(Means for Solving Problems) A microprogram control method according to the present invention is a control method for executing a microprogram using a memory in which a high-speed memory area and a low-speed memory area are divided by an address at a boundary. And a first memory access order, a second memory access order, and a memory access control means.
A waiting instruction for suspending program execution is set to accept the second memory access order and the access response on the basis of the access time of the low-speed memory, and a high-speed operation is performed between the second memory access order and the waiting instruction. The memory access time is used as a reference to perform the other program processing with the first memory access order set so as to match the waiting instruction.

The comparison means is for comparing the execution address of the microprogram with the boundary address of the memory and determining and outputting the high speed memory area or the low speed memory area.

The first memory access order has access memory type information that permits access when the execution address is a high speed memory.

The second memory access order has access memory type information that permits access when the execution address is a low speed memory.

The memory access control means, when the memory access request,
When the access memory type information held by the first and second memory access orders and the judgment output of the comparing means match, the memory access is executed, and when they do not match, the memory access is not executed. .

(Example) Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram partially showing one embodiment for realizing the microprogram control method according to the present invention. In FIG. 1, 1 is a micro address selector, 2 is a micro program address register, 3 is an incrementer, 4 is a micro program memory, 5 is a micro program instruction register, 6 is a micro program instruction decoder, and 7 is a branch control circuit. .

FIG. 1 shows a micro program sequencer for controlling the execution of a general micro program, and the micro address selector 1 selects a micro address to be executed next. One input of the micro address selector 1 is added from the incrementer 3 via, for example, the signal line 301,
The other input is applied from the branch control circuit 7 via the signal line 701. The incrementer 3 is used to increment the microprogram address by 1 when no branch occurs. The output of the micro address selector 1 is output via the signal line 101 to the micro program address register 2
Entered in. The output of the micro program counter 2 is the incrementer 3 and the micro program memory 4
Entered in.

The output of the micro program memory 4 is input to the micro program instruction register 5, and the output data of the micro program memory 4 is waited for every one clock cycle. The branch control unit and the branch address unit held in the microprogram instruction register 5 are added to one input terminal of the branch control circuit 7 via the signal line 502. The output of an arithmetic circuit (not shown) is added to the other input terminal of the branch control circuit 7 and used for conditional branch control.

The output of the micro program instruction register 5 is the decoder 6
In addition, the micro program instruction decoder 6 decodes the micro instruction and generates a micro order.

The inhibit signal on signal line 1801 is applied to the incrementer 3 to inhibit the increment of the microprogram address and inhibit the output of the microprogram instruction register 5. At this time, the outputs of the microprogram instruction register 5 are all "0". This stops the execution of the microprogram.

FIG. 2 is a block diagram showing another embodiment for implementing the microprogram control system including the interface portion of the memory according to the present invention.

In FIG. 2, 10 is an address boundary register, 11 is an address comparator, 12 is an address register, 13 is a data register, 14 is a memory, 15 is a micro instruction register, 16 is a decoder, 17 is a memory access control circuit, and 18 is Each of the memory queuing control circuits 121 to 129 is a driver.

In FIG. 2, an address boundary register 10 holds a boundary address between a high speed part and a low speed part on the memory 14 and is set by a micro program at the time of system initialization.
The bus signal lines 101 to 103 are each connected to a calculation unit (not shown), and the result calculated by the address boundary register 10, the address register 12, the data register 13, and the micro instruction register 15 is the signal line 101. Through 103, and the bus signal lines 101 to 1 by micro order
03 is controlled.

The address register 12 holds an address at the time of memory access, and supplies the memory address to the memory 14 via the driver 121.

The output of the address register 12 is input to the comparator 11, the contents of the address boundary register 10 and the contents of the address register 12 are compared at the memory access timing, and the comparison output becomes "1" at the high speed memory access.

The micro instruction register 15 corresponds to the micro program instruction register 5 in FIG. 1. In the micro instruction register 15, 15-1 is a memory access permission field during high speed access, 15-2 is a memory queuing control field, and 15-3 is a memory access. It is an order field. The memory access permission field 15-1 at the time of high speed access instructs to send out a memory request in the high speed memory mode when accessed by the memory access order field 15-3. Memory access order field 1-3
Defines several types of memory request orders.

The memory access control circuit 17 decodes the value of the memory access order field 15-3 by the decoder 16 and, when it is determined that it is a memory request, receives the output and the high-speed memory control field 15-1 from the comparator 11. When the values of are equal, the memory 14 is accessed. Decoder 16
Corresponds to the microprogram instruction decoder 6 in FIG.

The memory waiting control circuit 18 has a memory waiting field 15
It is a flip-flop that is set when the value of -2 is "1", and its output controls the signal on the signal line 1801 in FIG. 1 to stop the execution of the microprogram. When a response is sent from the memory 14, the memory queuing control circuit
18 is reset and microprogram execution is restarted. Here, the execution of the microprogram is stopped during the memory access time.

FIG. 3 is an explanatory diagram showing an example of microprogram coding in FIGS. 1 and 2.

The microprogram of FIG. 3 consists of four steps and is a program for executing memory requests and operations.

In the first step, the address is set in the address register 12 and the memory request is executed. At this time, the contents of the address boundary register 10 and the contents of the address register 12 are compared by the comparator 11, and the comparison result is sent to the memory access control circuit 17. The comparator 11 compares the content of the address boundary register 10 with the content of the address register 12, and outputs "1" when the content of the address register 12 is smaller than the content of the address boundary register 10. This indicates that the address of the memory 14 to be accessed is the high speed memory area.

The access time from access to response in the high-speed memory is set to at least 1 clock, and the access time in the low-speed memory area is set to at least 3 clock. The number of these clocks may be extended at the time of refreshing or when an error occurs. Therefore, in the case of one clock access, the response from the memory is received in one clock. A memory queuing order must be issued by the instruction. In case of 3-clock access, it takes 3 before the response from the memory is received.
Since there is a clock, a memory queuing order is issued within three steps.

However, when the system is provided with a high-speed memory and a low-speed memory, it is necessary to match the one with the smaller memory access clock. Therefore, the memory waiting must be performed immediately after the memory access order is issued. Therefore, when the memory access is executed to the low speed area, the waiting time cannot be used effectively, and the processing shown in the example of FIG. 4 is executed according to the usual method. In Fig. 4, after making a memory request in the first step, regardless of whether it is a high-speed memory or a low-speed memory, a memory waiting order is issued in the next step, and after waiting for 3 clocks, the remaining 2 steps are executed. Since the above process is performed, 4 steps must be executed in 6 clocks. On the other hand, according to the microprogram shown in FIG. 3 according to the present invention, the problem can be solved in four clocks.

First, at the same time as setting the address boundary register 10 to perform the memory read access according to the first step,
Issuing a read request. At this time, RE for low-speed memory access is set by the memory access order field 15-3.
AD1 micro-order is sent and the memory access permission field 15-1 at high speed access is set to "0". When the address establishes the low-speed memory area, the output from the comparator 11 is "0", and the setting value of the memory access permission field 15-1 during high-speed access is also "0". The memory access control circuit 17 immediately sends a memory request to the memory 14 to access the memory. Then, the second to fourth steps are sequentially executed in three clocks until the memory response of the low-speed memory comes, and after the completion of the execution of the fourth step, the memory waiting order is issued.

Then, after that, if the refresh has not occurred in the memory 14, the memory 14 sends the return data, so that the control of the microprogram proceeds. In this way, in the low-speed memory area, the memory 14 is accessed while performing internal calculation in parallel during the memory waiting time.

Next, the case where the microprogram shown in FIG. 3 accesses a high speed memory will be described. It is assumed that the comparator 11 compares the pair of addresses in the first step and determines that the memory is a high speed memory. At this time
Memory access permission field 1 for high-speed access of READ1
Since 5-1 is set to "0", the memory access control circuit 17 does not access the memory 14 and the second and third
Step. When the third step is executed, the READ2 micro-order for accessing the high-speed memory (when the value of the memory waiting control field 15-2 in FIG. 2 is "1" and the memory access order field 15-3 is
The memory request is sent out (at the time of READ), and then a waiting order for waiting for a memory response is issued in the fourth step. In this way, by inserting a parallel processing step for the memory waiting clock next to the micro order sent at the time of low-speed memory access and combining the micro order sent at the time of high-speed memory access and the memory waiting order, Even if high-speed memories are mixed, parallel processing can be effectively performed during the waiting time of the low-speed memories.

(Effect of the Invention) As described above, according to the present invention, when a memory request is made, its address is compared with a fixed value, and the memory request is validated or invalidated according to the comparison result. Since it is possible to parallelize the arithmetic operation and the memory operation at the time of low-speed memory access, which is impossible in the system including the memory, it is possible to improve the processing efficiency.

[Brief description of drawings]

FIG. 1 is a block diagram partially showing one embodiment for realizing the microprogram control method according to the present invention. FIG. 2 is a block diagram showing another embodiment including the interface portion of the memory according to the present invention and realizing the micro program control system. 3 and 4 are flow charts showing the processing steps of the program related to the present invention. 1 ... Micro address selector 2 ... Micro program address register 3 ... Incrementer 4 ... Micro program memory 5 ... Micro program instruction register 6 ... Micro program instruction decoder 7 ... Branch control circuit 10 ... Address boundary register 11 …… Comparator, 12 …… Address register 13 …… Data register, 14 …… Memory 15 …… Micro instruction register 16 …… Decoder 17 …… Memory access control circuit 18 …… Memory waiting control circuit 121-129 …… Drivers 15-1 to 15-3 ... Field 101 to 103,201,301,401,501,502,602,701,702,1801 ......
Signal line

Claims (1)

[Claims] 1. A control system for executing a microprogram using a memory in which a high-speed memory area and a low-speed memory area are divided by a boundary address, and a high-speed memory in which an execution address of the microprogram is compared with a boundary address of the memory. Area for determining whether the area is a low speed memory area, a first memory access order having access memory type information for permitting access when the execution address is a high speed memory, and a first memory access order for the execution address being a low speed memory A second memory access order having access memory type information permitting access, and the access memory type information held by the first and second memory access orders respectively and a judgment output of the comparing means when a memory access request is made. If they match, a memory access is performed and the match Memory access control means that does not execute memory access when not performing, and at the time of memory access, temporarily suspends program execution to accept the second memory access order and access response based on the access time of the low-speed memory. And a waiting instruction to be set between the second memory access order and the waiting instruction, and the first memory access order and other instructions are set so as to match the waiting instruction with reference to the access time of the high-speed memory. A microprogram control method characterized by performing a program process.