JPS60159958A - Data transfer controlling circuit - Google Patents

Abstract

PURPOSE:To omit a conditional branch instruction for waiting for a data transfer, to reduce the number of steps of a program, and to hasten a processing speed by controlling a program counter by a control signal from a controlling circuit. CONSTITUTION:When waiting for an execution of a data transfer of a slave processor, in case of judging the end of the data transfer by a master processor, a control is executed as follows. That is to say, a program counter 1 is controlled by an instruction 5 for transferring a data through an interface register 9, and a program counter control signal 14 from a controlling circuit 13 by which an RQ flag 8 becomes an input signal. As a result, the RQ flag 8 is set, a data transfer is requested to the master processor, and thereafter, a program sequence to immediately before an instruction for transferring a data through the register 9 in the succeeding instruction group is executed automatically. Accordingly, a conditional branch instruction for waiting for a data transfer is omitted, the number of steps of a program is reduced, and the processing speed can be hastened.

Description

[Detailed Description of the Invention] (1) Description of the Technical Field of the Invention The present invention relates to a data transfer control circuit of a processor having a data transfer function, and in particular does not output control signals such as address signals and read/write signals. The present invention relates to a data transfer control circuit for a processor (hereinafter referred to as a slave processor, and a processor that outputs a control signal is referred to as a master processor).

(2) Description of Prior Art FIG. 5lE1 shows a conventional example of a data transfer control circuit of a slave processor necessary for data transfer with a master processor. In the figure, 1 is a program counter, 2 is a program memory, 3 is an instruction register, 4 is an instruction decoder that decodes the instruction latched in the instruction register 3, and 8 is a data transfer request flag (hereinafter referred to as RQ flag). , 9 is an interface register for data buffering with the master processor, 11 is a branch signal output circuit that outputs a branch signal to the program counter 1, and 5 to 7 are interface registers among the instructions output from the instruction decoder 4. 7 indicates an instruction via the eighth register 9, 5 is a data transfer instruction, 6 is an instruction to set the RQ flag, 7 is a conditional branch instruction, 12 is a branch signal output from the branch signal output circuit 11), 10 indicates a data transfer control signal by the master processor.

The RQ flag 8 is set to p by the instruction 6 that sets the RQ flag 8 when a data transfer is requested to the master processor, and when the data transfer by the master processor is completed (from the start of the write cycle to the end of the write cycle). ), data transfer control signal 1
It is reset by ゜. In other words, after the system sleep processor requests data transfer from the master processor based on the RQ flag 8, if the data transfer is to be read by the master processor, the data in the eighth register 9 of the interface 7 is read by the master processor. If data is written by the master processor, it is possible to determine whether data has been written to the eighth register 9 by using a mask.

The interface register 9 is used as a data buffer in a data transfer circuit with the master processor. In the case of reading by the master processor, the slave processor writes the data to be given to the master processor in the interface register, sets the RQ flag 8 and requests the master processor to read the data, and then the master processor reads the data. Until the process is completed, other processes can be executed as long as the contents of the inter 7/8 register 9 are not changed.

Similarly, when writing by the master processor, R
By setting the Q flag 8 and requesting the master processor to write data, other processing can be executed to the extent that the data is not required. The thumb interface register 9 is used as a buffer to improve processing efficiency of the processor.

However, according to the conventional circuit example shown in FIG. , an instruction to control the program counter depending on its state) and the conditional branch instruction 7 is inserted at an appropriate location in the program sequence because the judgment is made based on the state of RQ7 lag 8, and in the subsequent sequence, Next, it was necessary to place an instruction to transfer data via the interface register 9. Therefore, when creating a program, it is important to create a program that has the highest processing speed and that does not involve any pre- or post-procedures (such as errors such as accessing an interface register before data transfer due to a mask has been completed). In addition, it is necessary to pay attention to whether the program sequence is in the state tq at the time of data transfer or in the state where the data transfer has been completed. The disadvantage is that the number of instruction steps is heavy.

, 3) Detailed Description of the Invention An object of the present invention is to automatically wait for a slave processor to execute a data transfer in a machine cycle in which an instruction to access an interface register is executed. The object of the present invention is to provide a data transfer control circuit that eliminates the above drawbacks by omitting branch instructions.

4) Structure of the Invention According to the present invention, a program counter, an instruction decoder, an RQ flag, an inter 7 eighth register, and a data transfer instruction and RQ via an interface register are provided.
The data transfer control circuit includes the flag and a control circuit which takes the flag as an input signal and causes the program sequence to enter a data transfer wait state depending on the state of the data transfer request flag.

5) Detailed Description of the Invention Next, embodiments of the present invention will be described with reference to the drawings. Figure 1 shows a conventional example, and Figure 2 shows an embodiment of the present invention.
Comparing with the figure, the difference in the conventional example is conditional branch instruction 7.
Branch signal output circuit 1 which receives and RQ flag 8 as input signals
In the embodiment of the present invention, the part that used to control the siprogram counter 1 by the branch signal 12 that is output more than 1 (see FIG. 1) inputs the instruction 5 for data transfer via the interface register and the RQ flag 8. The program counter 1 is controlled by a program counter control signal 14 which is outputted to a control circuit 13 as a signal (FIG. 2). Second
In the circuit shown in the figure, the operation of the interface register as a data buffer is exactly the same as in the conventional example, but whether or not data transfer by masking is completed depends on the timing at which instruction 5 to transfer data via the interface register is executed. Depending on the state of the decoy flag 8, the program counter control circuit 13 outputs the program counter 1 using the program counter control signal 14.
control. Therefore, after setting RQ7 lag 8 and requesting the master processor to transfer data, the program sequence immediately before executing the instruction that transfers data via the interface register among the subsequent instructions is automatically executed. executed and no conditional branch instructions are required.

Here, the expression 6 automatically °' means that in the conventional example, the programmer had to insert a conditional branch instruction at an appropriate position in the program sequence, but according to the embodiment of the present invention, this is not possible. It means there is no need. In other words, by configuring a data transfer control circuit according to the present invention, a conditional branch instruction for waiting for data transfer, which was conventionally necessary, becomes unnecessary.

By that (1) The number of program steps is reduced.

(2) Program creation becomes easier.

(3) A program with high processing speed can be reliably obtained.

This effect can be obtained.

Regarding (1), the effect is clear in that the number of program steps is reduced because the conditional branch instruction is omitted, and the program memory area is used effectively.

(2) and (3) will be explained using examples.

Assume a slave processor with the following specifications.

・Internal readable/writable data memory (RA)
M).

-The read/write address of the RAM is specified by the address register (POINTER).

Considering a program that uses this slave processor to write data from the master processor to a certain address in RAM, the conventional slave processor
Two program examples (1) and (2) shown in the figure can be considered. Comparing program examples (1) and (2), it is found that several instruction cycles of the slave processor are required for the mask to confirm the slave processor's data transfer request and perform the data transfer, so the POIN
The program example (2), which is a procedure for setting TEJ, has a faster processing speed until the end of the operation.

As shown in this example, processing speeds of slave processors with conventional data transfer control circuits vary depending on the type of program created, so program creators must invest a lot of effort in creating programs with the highest processing speed. Requires. However, with the slave processor having the data transfer control circuit according to the present invention, it is possible to easily create a program that has a small number of program steps and is excellent in terms of processing speed, as shown in program example (3) in FIG. .

[Brief explanation of drawings]

FIG. 1 is a block diagram illustrating a conventional data transfer control circuit, and FIG. 2 is a block diagram illustrating an embodiment of the present invention. 1: Program counter, 2: Old program memory, 3: Instruction register, 4: Old...
Instruction coder, 5...Data transfer instruction via interface register, 6...RQ flag set instruction, 7...Contested branch instruction (Figure 1 only) , 8... RQ flag, 9... Interface register, 10... Data transfer control signal by master, 11... Branch signal output circuit, 12... ... Branch signal, 13 ... Control circuit, 14 ... Program counter control signal w
, 3 and 4 are flowcharts of an example of a program of a slave processor using a conventional data transfer control circuit, and FIG. 5 is a flowchart of an example of a program of a slave processor employing the configuration of the present invention. 1: @ 1-5h = Jc'
a data transfer j11 fu? (4 pieces missing).

Claims (1)

[Claims] a program counter that specifies a memory address where an instruction to be executed is stored; an instruction decoder that decodes an instruction read from the memory address; and a program counter that is set by a data transfer request instruction and reset by execution of the data transfer. an interface register as a data buffering means for transferring data to and from the outside; and an interface register as a data buffering means for transferring data with the outside; and when executing a data transfer request instruction, the data transfer request instruction 1. A data transfer control circuit comprising: a control circuit that causes the execution of the data transfer control circuit to enter a wait state.