JPS63279351A - Dma transfer controller - Google Patents

Abstract

PURPOSE:To start the transfer of data at a high speed when a data transfer processing request is received by writing previously a microaddress for data transfer processing into a microaddress register while an operation microaddress register is working. CONSTITUTION:An operation microaddress register 45 is used as a microaddress register which an operation-only program process. Then the microaddresses MAPA read out of a mapping PLA 2 for transfer processing are written into microaddress registers 40-43 which are used for transfer of data for each channel. Thus it is possible to start the data transfer program processing at a high speed with no dead cycle based on those microaddresses written previously in the registers 40-43 when a data transfer program processing request is received after the end of a starting process.

Description

Detailed Description of the Invention (Summary) It has a microaddress register for each channel that stores a data transfer program address and an operation microaddress register that stores an operation program address, and processes programs other than data transfer program processing. is performed, the operation program address stored in the operation micro-address register is read out to control reading of the microprogram stored in the micro ROM, and furthermore, during the operation of the operation micro-address register (e.g. During start processing), each micro address register for data transfer processing for each channel is a DMA transfer control device in which a micro address for data transfer processing is written in advance in response to a write command from the micro ROM. Therefore, when a data transfer program processing request is accepted after the start processing is completed, the data transfer program is executed at high speed without dead cycles based on the microaddress written in advance in the microaddress register for the data transfer processing. Processing can be started.

[Industrial application field]

The present invention relates to a DMA (direct memory access) transfer control device, and more particularly to a DMA transfer control device for controlling data transfer by a DMA controller that controls data transfer without involving a CPU.

[Conventional technology]

FIG. 9 is a diagram explaining the concept of DMA transfer,
PU, I10 device (e.g. 101), memory (e.g. Ml, M2), DMA controller (to DM8) etc. are connected to address bus, data bus, and bus for control signals (e.g. bus for read/write signals). ) to form a microcomputer system. When DMA transfer is performed, the DMA controller occupies each of the buses instead of the CPU, and
According to transfer information such as a command and a transfer address written in advance by the PU to the internal register of the DMA controller, the transfer information is transferred between the memories (for example, M1).

M2) or between the memory and the I10 device (e.g.
Controls data transfer from OI to Ml or from Ml to ■01). For this purpose, the DMA controller
A hold request signal (10LD) is sent to the DMA controller, whereby the operation of the CPU is temporarily interrupted, the CPU hands over the bus, and a hold permission signal HOLD ACK is sent back from the CPU to the DMA controller.
Execution of the microprogram begins. Note that before sending the hold request signal, a predetermined command and transfer address are registered in advance from the CPU in the internal register of the DMA controller, and then the hold request signal is sent based on the start instruction from the CPU. Sent out. That is, for example, in the case of data transfer between memories, the addresses of the transfer source and destination, the amount of transfer data (byte information), etc. are registered, and the transfer data is transferred via the DMA controller. The above data transfer continues until the amount becomes zero. Furthermore, in the case of data transfer between a 10 device and a memory, for example, a predetermined I10 device sends a transfer request signal REQ to the DMA controller, and the DMA controller returns a permission signal REQ ACK for the transfer request and transfers the data. The destination address is specified, and data is transferred from the JI10 device to a predetermined memory.

FIG. 10 is a schematic diagram showing the internal configuration of such a DMA controller (DMAC), which is composed of a request handler R, a data handler D1, a micro unit M, and the like. For example, when the request handler R receives a transfer program processing request signal REQ from an I10 device (or an autorequest signal that is automatically generated based on a start instruction from the CPU when data is transferred between memories), , sends a predetermined data transfer program processing request signal TREQ to the data handler D or micro unit M. The micro unit M sends a control signal for performing a predetermined data transfer to the data handler D based on the transfer program processing request signal TRE. This allows predetermined data transfer (for example, memory M
Data of a predetermined byte is sequentially read from a predetermined location in the memory M2 and sequentially written from a predetermined location in the memory M2.

The DMA transfer control device of the present invention is a partially improved version of the micro unit M that functions as a control unit for controlling data transfer via such a DMA controller, and FIG. 7 shows the features of the present invention. In order to clarify this, the configuration of the corresponding portion of the micro unit M that can be assumed within the scope of the prior art is illustrated.

That is, in FIG. 7, R indicates a request handler, and other components (namely, address register control section 1, mapping PLA 2, selection condition PL
A3, micro address registers 40 to 43 for channels 0 to 3, selector 5, increment element 6, micro ROM 7, and register 8) form part of the micro unit M. That is, what is shown in FIG. 7 above shows a DMA transfer control device for four channels, and transfer request signals R[iQO to REQ3 are inputted to the request handler R from, for example, four sets of I10 devices. In response to the input of these transfer request signals, the request handler R sends a predetermined channel designation signal CH to the microaddress register.
At the same time, a transfer program processing request signal TREQ is input to the address register control unit l, and the micro address register (for example, 40
) is supplied with a read or write signal R/W. Micro address register 4o for each channel above
Address information for controlling data transfer for the channel is held in 43 to 43, and when the held address information is read out, the successively read address information is transferred to the micro ROM 7 through the selector 5. At the same time as being input, the contents of the address information are incremented by the increment element 6 and written again to the micro address register (for example, 40) of the channel. As a result, the microinstruction stored in the corresponding address is read from the micro ROM 7, and then taken into the register 8, and a control signal for performing data transfer regarding the channel is transmitted from the register 8 to, for example, the data handler. It is output to D, etc.

In addition to the address information read out from the micro address registers 40 to 43, the selector 5 also contains:
For example, address information read from the mapping PLA2 is also input, and only predetermined address information is selectively input to the micro ROM 7 through the selector 5 in accordance with a select signal supplied from the select condition PLA3. Here, the mapping PLA is a so-called jump for the micro ROM to specify the address from which the micro ROM should operate according to the conditions input to the mapping PLA, such as a startup address and an address for jumping. It functions as a table.

FIG. 8 is a timing diagram showing a startup sequence when a microprogram startup process is performed by the device shown in FIG.
A data transfer program processing request signal TREQ is output from , and based on the request signal TREQ, a predetermined micro address is first read out from the mapping PLA 2, and then data in the micro ROM is read out based on the successively read micro addresses. (micro-instruction) is read out, and a predetermined data transfer process is started via the data handler D based on the output data of the micro-ROM that has been read out. Note that the micro ROM 7 is precharged with the clock φ1 at a high level, and the clock φ1 is precharged at a high level.
1 is discharged at low level.

In addition, the mapping PLA2 and the selection condition PLA
3 is precharged when the clock φ2 is at a high level, and discharged when the clock φ2 is at a low level.

In this way, in the device shown in FIG. 7, the address information read from the mapping PLA 2 is input directly to the micro ROM 7 via the selector 5, so that the timing chart shown in FIG. , the transfer program processing request signal TREQ is mapped to PLA2.
It takes approximately two cycles (two clocks) from when the signal is input to the start of the transfer process, and therefore approximately one dead cycle is inserted at the time of channel transition.

This means that the data transfer program processing request signal TR
Not only when EQ is input, but also when operation processing (program processing other than data transfer program processing, such as start processing executed before actual data transfer processing) request signal 0REQ is sent from request handler R to mapping PLA2. It also takes approximately two cycles to start a predetermined operation process (for example, start process) after the data is input, resulting in a reduction in the transfer processing speed.

[Problem that the invention seeks to solve]

The present invention was made to solve this problem, and before accepting a request for data transfer program processing, (
For example, during the start process), in advance, the above mapping PLA
By reading the micro-address for data transfer program processing and writing it into the micro-address register for the transfer processing, the transfer processing request can sometimes be accepted immediately based on the micro-address written in the micro-address register. The micro ROM is operated to start data transfer processing at high speed (without dead cycles).

[Means for solving problems]

In order to solve the above problems, the present invention has a microaddress register for each channel that stores a data transfer program address and an operation microaddress register that stores an operation program address. When program processing is being performed, the operation program address stored in the operation microaddress register is read out to control reading of the microprogram stored in the microROM, and furthermore, the operation of the operation microaddress register is controlled. A DM in which a micro address for data transfer processing is written to each micro address register for data transfer processing for each channel in response to a write command from the micro ROM during the middle (for example, during start processing).
A transfer control device is provided.

[For production]

According to the above configuration, while the micro address register for the operation is in operation (for example, during start processing), the micro address for the data transfer process is written in a predetermined micro address register, thereby processing the data transfer program. Sometimes, request reception does not require reading the microaddress from the mapping PLA, and the request is immediately read from the microROM based on the microaddress written in advance to the microaddress register.
, and start the data transfer process at high speed (without de-node cycles).

〔Example〕

FIG. 1 shows a DMA transfer control device as an embodiment of the present invention. The major difference from the device shown in FIG. Alternatively, an operation microaddress register 45 for performing program processing other than data transfer program processing such as bus error processing) is added, and during the operation of the operation microaddress register 45 (for example, during start processing), from the mapping PLA 2. The read micro address MAPA for transfer processing is stored in micro address registers 40 to 4 for transfer processing for each channel.
3 is written in. In addition, in Figure 1,
MAPW is a write command supplied from the micro ROM 7 via the register 8 to predetermined micro address registers 40 to 43, and thereby the mapping PL
Micro address MAP for transfer processing read from A
A is micro address register 4 for operation
During the operation of step 5, the micro address registers 40 to 43 for the transfer process are written. Further, a read command C0D of the micro address MAPA is sent from the micro ROM 7 to the mapping PLA via the register 8.
E is supplied.

In the device shown in FIG. 1, when normal data transfer program processing is being executed, the data transfer program processing is performed according to the channel designation signal CH and the transfer program processing request signal TREQ input from the request handler R to the address register control unit 1. Then, the read signal μ is sent from the address register control unit 1 to the micro address registers 40 to 43 corresponding to a predetermined channel.
^RRO to μ^RR3 and write signals μARWO to μARW3 are supplied. Further, when an exception event occurrence signal such as a bus error signal BERR is input to the address register control section 1, the signals OPR and OPW output from the address register control section 1 are used to control the operation micro address register 45. Reading or writing is controlled. That is, these signals OPR and OPW are not generated while data transfer program processing is being executed, but are output when operation program processing such as bus error processing is executed.

FIG. 2 is a circuit diagram illustrating the internal configuration of the microaddress register shown in FIG. , transistors 402 to 432 to which write signals from the address register control unit 1 are supplied from the AND gates 401 to 431, respectively, and a latch circuit 40.
3 to 433, transistors 404 to 43 to which a signal for reading address information held in the latch circuit is supplied;
4, and transistors 405 to 435 to which a write signal MAPI14 from the micro ROM is supplied from a common AND gate 461. On the other hand, the micro address register 45 for operation includes an AND gate 451, a transistor 452 to which a write signal from the address register control section 1 is supplied from the AND gate 451, a latch circuit 453,
A transistor 45 is supplied with a signal for reading address information held in the latch circuit via an inverter 456.
Consisting of 4.

Therefore, when the write signal μARWO to the micro address register 40 for data transfer corresponding to channel O becomes high level when the clock signal φ1 is high level, the transistor 402 is turned on via the AND gate 401, and the increment element 6 side Predetermined address information is held in the launch circuit 403. On the other hand, when the read signal μARRO to the micro address register 40 becomes high level, the transistor 404
is turned on, and the address information held in the latch circuit 403 is read out.

Similarly, when the write signal OPW to the operation microaddress register 45 becomes high level at the time when the clock signal φ1 is high level (as described above, an exception event such as the bus error signal BERR occurs to the address register control unit 1). (High level when a generation signal is input or during start processing, etc.)
, the transistor 452 is turned on via the AND gate 451, and predetermined address information from the increment element 6 side is held in the launch circuit 453. On the other hand, when the read signal to the micro address register 45 becomes high level, In the case of FIG. 2, the low level transfer enable signal TEN is inverted by the inverter 456 and set to high level), the transistor 454 is turned on, and the address information held in the latch circuit 453 is read out.

Furthermore, in the present invention, while the micro address register 45 for the operation is in operation (for example, during start processing), the micro address MAPA for the transfer process read from the mapping PLA is stored in the micro address registers 40 to 43 for the transfer process. When the micro RO signal φ2 is at high level to write the micro RO
Write signal MA supplied from M7 via register 8 to micro address registers 40 to 43 for each transfer process.
When P- becomes high level, the micro address registers 40 to 4 for each transfer process are transferred via the AND gate 461.
Each of the transistors 405 to 435 provided in the above-mentioned transistors 405 to 435 is turned on, and the micro address MAPA read from the mapping PLA2 is
The data is written to each latch circuit 403 to 433 via the latch circuit 403 to 433.

In this way, each micro address register 4 for transfer processing
0 to 43 are provided with a write route from the mapping PLA in addition to the write route from the increment element 6.

That is, while the micro address register 45 for operation is in operation (for example, during start processing), the micro address registers 4 to 43 for transfer processing are in an unused state and are in a state where data can be written. In advance, the micro address MAPA for transfer processing is read from the mapping PLA by the successive write command C0DH from the micro ROM, and the write command MAP is read out from the mapping PLA.
- micro address register 4 for the transfer process
By writing the micro address MAP^ to 0 to 43, there is no need to read the micro address from the above-mentioned mapping PLA when accepting a transfer process request, and the transfer process can be executed at high speed without dead cycles. can do.

FIG. 3 shows a read signal μA for the micro address registers 40 to 43 for each channel for data transfer in the address register control section shown in FIG.
I? RO to μAFIR3 and write signal μARWO
4 is a circuit diagram illustrating a specific configuration of a portion that outputs a read signal OPR to μARW3, a transfer enable signal TEN, and a micro address register 45 for operation, and FIG. 3 is a circuit diagram illustrating a specific configuration of a portion of the register control unit that outputs a write signal oPW to a micro address register 45 for operation. FIG.

In FIGS. 3 and 4, A1 to Al1 are AND gates, B1 to B5 are OR gates, and (1) to (9) are inverters. Of these, inverter (4) operates when the clock signal φ1 is at a high level, and when the clock signal φ1 is at a low level. When , the output side is dynamically latched. Also, inverter I
t, 15.18 operates when the clock signal φ2 is at high level, and when it is at low level, its output side is dynamically latched. FFI to FF4 are RS flip-flops, of which FFI to FF3 are reset-priority RSS flip-flops, that is, when both cent power S and reset power R are O, the previous data is retained, and set power S is 1. When the reset human power R is O, it is in the set state (that is, Q = 1), and when the set human power S is O and the reset human power R is 1, and the set human power S and the reset human power R
When both are 1, it is a reset state (i.e. Q=0)
It is.

Of the signals input to the circuit shown in FIG.
D is a transfer processing end request signal, and EXP is an exception event occurrence signal, which also includes the above-mentioned bus error signal. Further, IBR indicates an internal data bus use request signal, WAIT indicates a wait request signal, and CHO to CH3 indicate instruction signals for each channel 0 to 3, and the signals CHO to CH3 are at a low level when active. Among the signals input to the circuit shown in FIG. 4, 0REQ indicates the above-mentioned operation processing (for example, start processing) request signal, and μEND indicates the operation processing end request signal.

As a result, when the exception event generation signal EXP is at a low level, the clock signal φ1 and the transfer program processing request signal TREQ go to a high level, thereby setting the flip-flop FFI and enabling the transfer enable signal T.
When EN goes high, a predetermined channel is designated (for example, CIO goes low), and the read signal μARRO for the microaddress register 40 corresponding to channel 0 goes high, and the next clock When signal φ2 is at high level, flip-flop FF2 is set, and write signal μARWO for micro address register 40 becomes high level.

On the other hand, when the exceptional event occurrence signal EXP becomes high level (for example, when a bus error occurs), the flip-flop FF1. FF2 is reset and the micro address register read signals μARRO to μARR3 and write signals μARWO to μARW for each channel are generated.
3 becomes low level, while the read signal OPR for the operation micro address register 45 becomes high level (transfer enable signal TEN becomes low level). Furthermore, in the circuit shown in FIG. 4, flip-flops FF3. By sequentially setting FF4, the write signal OPW to the operation microaddress register 45 becomes high level.

FIG. 5 shows the selection conditions Pl and A shown in FIG. 1 above.
3 shows a schematic configuration diagram of the micro ROM,
The selection conditions are determined by various signals input from the internal register of the DMA controller, the error test circuit, the request handler R1, the data handler D, etc., and are taken into the latch circuit by the clock φ1. For example, the above operation processing request signal 0R
EQ is input from request handler R, and bus error signal BERR is input from data handler D.

Further, FIG. 6 shows the mapping PLA shown in FIG. 1 above.
2 shows a schematic configuration diagram of the micro ROM,
The microaddress at which the microROM should operate is determined by various signal conditions input from the internal register of the DMA controller, the error test circuit, the ALU, the request handler R1, the data handler D, etc., and is taken into the latch circuit by the clock φ1. For example, the read command C0DE for each channel is input from the micro ROM, the operation processing request signal 0REQ is input from the request handler R, and the bus error signal BERR is input from the data handler D.

〔Effect of the invention〕

According to the present invention, during the operation of the operation microaddress register, data transfer processing requests are sometimes accepted without dead cycles based on the microaddress written in advance from the mapping PLA to the microaddress register for data transfer processing. Data transfer processing can be started at high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a DMA transfer control device as an embodiment of the present invention, FIG. 2 is a circuit diagram illustrating the internal configuration of the address register shown in FIG. 1, and FIG. 1 is a circuit diagram showing the structure of a part of the address register control section shown in FIG. 1; FIG. 4 is a circuit diagram showing the structure of another part of the address register control section shown in FIG. 1; 5 is a schematic diagram of the selection condition PLA shown in FIG. 1, FIG. 6 is a schematic diagram of the mapping PLA shown in FIG. 1, and FIG. 7 is a diagram of a DMA transfer control device as a conventional technique. FIG. 8 is a timing diagram showing the operation of the device shown in FIG. 7; FIG. 9 is a diagram explaining the concept of DMA transfer; FIG.
The figure is a schematic diagram showing the internal configuration of the DMA controller. (Explanation of symbols) DMAC: DMA controller, R: request handler, M: micro unit, D: data handler, 1: address register control unit, 2: mapping PLA. 3...Select condition PLA, 40-43...Micro address register for transfer processing for each channel, 45...Micro address register for operation, 5...Selector, 6...Increment element, 7. ...Micro ROM. 8...Register. Schematic diagram of the selection condition PLA shown in Figure 1 Part 5 Schematic diagram of the mapping PLA shown in Figure 1 Part 6

Claims (1)

[Claims] 1. It has a microaddress register for each channel that stores a data transfer program address and an operation microaddress register that stores an operation program address, and program processing other than data transfer program processing is performed. At this time, the operation program address stored in the operation microaddress register is read out to control the reading of the microprogram stored in the microROM, and furthermore, while the operation microaddress register is in operation, A DMA transfer control device characterized in that a microaddress for data transfer processing is written into each microaddress register for data transfer processing in response to a write command from the micro ROM. 2. During the start process executed prior to the data transfer process, the micro address for the data transfer process read from the mapping PLA in response to the read command from the micro ROM is used to transfer data for each channel. written to each microaddress register for processing,
A DMA transfer control device according to claim 1.