JP2623501B2 - Direct memory access control circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a direct memory access control circuit, and relates to a technique effective for use in a system in which a series of data transfer controls are performed by a microprogram control system, for example. is there.

[Conventional technology]

Regarding the direct memory access control circuit built in the microprocessor, see, for example, “Hitachi Microcomputer Data Book 8” published by Hitachi, Ltd. in September 1985.
• 16-bit processor, page 464 to page 474.

In this direct memory access control circuit, data transfer is performed by a method that does not include a bus open cycle (each read / write uses three clocks).

[Problems to be solved by the invention]

In the above direct memory access control circuit, the time for issuing the bus control signal and the address of the data transfer source (source side) and the transfer destination (destination side) is short,
This is a bottleneck for increasing the frequency of the clock. Also, in order to eliminate the critical path, it is necessary to increase the number of clocks required for one data transfer, so that a bus open cycle is inserted during data transfer.

An object of the present invention is to provide a direct memory access control circuit that realizes high-speed operation.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
In a series of operation control steps for executing one-byte data transfer, an address output for one-byte data transfer to be transferred next is included.

[Action]

According to the above-described means, an address signal can be issued at the same time as entering the next data transfer cycle, so that high-speed operation can be achieved.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of a direct memory access control circuit according to the present invention. Each circuit block in FIG. 1 is not particularly limited by a known semiconductor integrated circuit manufacturing technique, but may be made of a single-crystal silicon.
It is formed on individual semiconductor substrates.

In the direct memory access control circuit of this embodiment, a series of operation control for data transfer is performed by a microprogram control method. Therefore, the control circuit CONT includes a microprogram for the above microprogram control.
It has a ROM (hereinafter simply referred to as mROM).

The direct memory access control circuit of this embodiment has the following registers.

The source address register SAR0 specifies the transfer source address of the channel 0. The register SAR0 is not particularly limited, but has 19 bits and can directly access up to 512K bytes in the case of a memory and up to 64K bytes in the case of an I / O without going through a memory management unit.

The destination address register DAR0 specifies the transfer destination address of the channel 0. This register
DAR0 has 19 bits and can directly access up to 512K bytes for memory and up to 64K bytes for I / O without going through the memory management unit as described above.

The byte count register BCR0 specifies the number of transfer bytes of channel 0. This register BCR0 has 16 bits and can specify up to 64K bytes. To transfer n bytes, the register BCR0 is designated via the internal bus BUS and "n" is written. When the transfer of one byte is completed, the signal from the control circuit CONT and the counting circuit INC / DEC are decremented by one, and become "0" at the end of the transfer.

The memory address register MAR1 is the transfer source for channel 1. Alternatively, a memory address to be a transfer destination is specified. The register MAR1 has 19 bits in the same manner as described above, and accesses a 512-Kbyte address space in the case of a memory without going through a memory management unit.

The I / O address register IAR1 is a transfer source on channel 1. Or, specify the address of the I / O (input / output device) to be the transfer destination. This register IAR1 is not particularly limited, but has 16 bits and can directly access up to 64K bytes of I / O without going through the memory management unit as described above.

The byte count register BCR1 specifies the number of transfer bytes of channel 1. This register BCR1 is, as described above,
It has 16 bits and can specify up to 64 bytes, and when it is desired to transfer n bytes, this register BCR0 is specified via the internal bus BUS and "n" is written as described above. When the transfer of one byte is completed, the control circuit CONT
And -1 by the counting circuit INC / DEC, and becomes "0" at the end of the transfer.

Although the status register DSTAT is not particularly limited,
It has 8 bits and has an enable bit for the channels 0 and 1, a write enable bit for it, a DMA interrupt enable bit for channels 0 and 1, a master enable bit common to channels 0 and 1, and the like.

For example, when "1" is written to the enable bits of the channels 0 and 1 above, the master enable bit is automatically set to "1" and the DMA operation is started. When ▲ ▼ is input, this master enable bit becomes “0”
And the DMA operation stops, control is transferred to the microprocessor, and then to resume DMA operation,
Even if “1” has already been set, it is necessary to set “1” in the enable bit of channel 0 or 1. Data cannot be directly written to this master enable bit by software, and is initialized to "0" at reset.

The mode register DMODE is, although not particularly limited, composed of 8 bits. Of these, 2 bits are used to specify whether the transfer destination of the channel 0 is a memory, an I / O, and an increase or decrease of an address. These bits are initialized to "0" at reset. Using the remaining two bits, whether the transfer source of channel 0 is memory or I / O,
And increase / decrease of address. These two bits are
Initialized to "0" at reset. By the combination of the above four bits, it is possible to specify 16 transfer modes. The remaining one bit specifies the transfer mode between the memory of channel 0 and the memory.

The control register DCNTL is not particularly limited, but is composed of 8 bits and is used for setting the number of wait states.
And one for specifying a change in the memory address register after one-byte transfer.

For example, in the operation in the case where the cycle steal mode is designated, as shown in FIG. 2, the DMA transfers control to the microprocessor CPU every transfer of one byte. The microprocessor CPU executes one machine cycle,
Transfer control to. Such repetition is continued until the transfer end condition is satisfied.

On the other hand, in the burst mode, the DMA cycle continues until the DMA transfer is completed (until the byte count register becomes 00H), after which the microprocessor CPU resumes its operation.

The circuit P & RC determines whether the transfer request signals DERQ0 and DREQ1 are edges or levels with respect to the bits specified in the control register DCNTL, and controls the relationship between the DMA operation and the CPU operation.

The circuit B & CC is responsible for controlling the bus and the microprocessor CPU.

The drive circuit DRV is a bus drive circuit for outputting source and destination address signals, and includes, but not limited to, a latch circuit FF that holds an advance address signal as described later.

In this embodiment, a data transfer operation by the mROM in which a microprogram for executing a series of data transfer operations included in the control circuit CONT is stored is as follows.

FIG. 3 is a flowchart for explaining a rough data transfer operation by the mROM.

Rough processing for data transfer is, for example, processing Mi0
In the process Mi0, a source or destination address is formed, and the process Mi1 outputs the source or destination address from the address bus. In the process Mi2, read data is output on the data bus at the time of source access, and write data is output on the data bus at the time of destination access. In the process Mi3, the end process of the cycle is performed. In the first one-byte transfer operation of the series of processes, processes Mi0 to Mi2 for source side access are performed. After this, the end of the data transfer is determined.
Output of the address for the next transfer operation in parallel with Mi3 (in this case, the destination address)
And returns to the process Mi1 in the next cycle. If the transfer operation is completed by repeating the above loop, process Mi3
Performs only the transfer end. Process Mi0 as above
Is an operation for forming a transfer source or transfer destination address signal. In this configuration, the address output operation for the first one-byte transfer forms an address signal according to the microinstruction read from the mROM, but the subsequent address formation is performed in the end process Mi3 in the transfer operation process. In other words, in other words, at the same time, a process Mi0 for forming a source or destination address for the next cycle is performed. This allows
The next transfer destination or transfer source address signal is
This is taken into the latch circuit FF included in the DRV. Therefore, an address signal can be output on the address bus at the start of the next cycle.

This will be described with reference to a timing chart in the case of the cycle steal mode shown in FIG.
In the source-side cycle in the first half of the DMA cycle, a process of outputting write data of the cycle at the time of clock T3 in the output operation of the second-half destination address in the immediately preceding DMA transfer cycle (not shown)
Along with Mi3, a process Mi0 for outputting a source address for this DMA cycle is performed in parallel. Therefore, at the same time as the start of the DMA cycle, in other words, by operating the drive circuit DRV based on the address signal of the latch circuit FF at the clock T1, the output of the source address signal becomes possible. Then, at the clock T2, a process Mi2 of outputting read data to the data bus is performed, and at the clock T3, a process Mi3 of ending the cycle and a subsequent process Mi0 of forming a destination address signal are performed in parallel. Done. Therefore, the output operation of the destination address, which is the latter half of this DMA cycle, is performed in the same manner as described above.
Immediately starts with T1, the write data is output onto the data bus by the clock T2, and the clock T3 forms the end processing Mi3 of the cycle and the source address signal for the next 1-byte transfer operation to be performed. The processing Mi0 is performed in parallel.

As a result, the above processing is shown in FIG. 3 in comparison with the flow chart of FIG. 4 in which the micro-instruction relating to the next data transfer is sequentially issued after one data transfer is completed as in the prior art. In this embodiment in which the micro instruction issuance is pipelined,
This can be achieved by substantially reducing the number of processes. That is, if one clock is assigned to one process, the time required for transferring one byte of data can be reduced from four clocks to three clocks. In the dual address transfer as shown in FIG. 2, the clock is reduced from 8 clocks to 6 clocks. As a result, the data transfer rate can be reduced by as much as 33%.

The operational effects obtained from the above embodiment are as follows. That is, (1) by including an address forming operation for transferring 1-byte data to be transferred next in a series of operation control steps for executing 1-byte data transfer,
An address signal can be issued on the bus at the same time as entering the next data transfer cycle, so that there is no substantial internal critical path and an effect that high-speed operation can be achieved.

(2) High-speed operation is achieved by a very simple configuration in which a single data transfer operation is performed in parallel with the issuance of a microinstruction for forming an address signal for the next data transfer operation to be executed subsequently. Is obtained.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention of the present application is not limited to the embodiment, and it is needless to say that various modifications can be made without departing from the gist of the invention. Nor. For example, the process of forming a source address or a destination address for the next operation cycle may be performed before or in addition to being included in the process of ending the cycle as described above. Further, the latch circuit that holds the address signal formed earlier may be configured as one internal register in addition to being included in the drive circuit as described above.

The function of each register type can take various embodiments. For example, it may have a buffer memory for holding data to be transferred.

The direct memory access control circuit according to the present invention may be built in a single semiconductor integrated circuit device in addition to being built in a microprocessor or a microcomputer unit.

〔The invention's effect〕

The effect obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. In other words, a series of operation control steps for executing one-byte data transfer include an address forming operation for one-byte data transfer to be transferred next, so that the next data transfer cycle starts. At the same time, since an address signal can be issued on the bus, there is no substantial internal critical path, and high-speed operation is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a timing chart for explaining an example of the operation, FIG. 3 is a flowchart for explaining an example of the operation, FIG. 4 is a flow chart in the case where the data transfer operation of the present invention is performed by a conventional technique. CONT: Control circuit, mROM: Microprogram ROM, D
RV: Drive circuit, SAR0: Source address register, DA
R0: Destination address register, BCR0, B
CR1 Byte count register, MAR1 Memory address register, IAR1 I / O address register, DSTAT
… Status register, DMODE …… Mode register, DCN
TL: Control register, P & RC: Priority & request control circuit, B & CC: Bus & CPU control circuit, INC / DEC: Count circuit, BUS: Internal bus

Claims (2)

(57) [Claims] 1. A first process for forming a source or destination address, a second process for outputting an address formed by the first process from an address bus, and a read data on a data bus at the time of source side access. A third process of outputting the data and outputting the write data to the data bus at the time of access on the destination side, determining the end of the data transfer, performing a cycle end process if the data transfer is completed, and performing a next operation if the data transfer is not completed. A micro-program ROM for storing a micro-instruction for performing a fourth processing for forming a source or destination address for the first unit data transfer operation. 3 processing is performed, and the data transfer is not completed in the fourth processing. When it is determined that the data transfer cycle returns to the second processing, the above series of processing is sequentially repeated, and an address for the next data transfer cycle to be performed in the previous data transfer cycle is prepared. And a direct memory access control circuit. 2. The process of forming a source or destination address includes an operation of holding an address signal in a latch circuit provided in an output circuit.
2. The direct memory access control circuit according to claim 1, wherein each of said first to fourth processes is performed during one clock to constitute said one data transfer cycle.