JPH09244713A - Programmable controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the cost without lowering the throughput of data transfer. SOLUTION: The clock signal generated by a timer part 4 is outputted to an interruption control part 7 and a dedicated CPU 2. If the clock signal is inputted while the dedicated CPU 2 is performing a specific arithmetic process, the dedicated CPU 2 interrupts the process and puts a main CPU 1 in a hold state back to an operation state. Namely, the control is returned to the main CPU 1 in every cycle (500μs) of the clock signal even while the dedicated CPU 2 is performing the arithmetic process. Further, the cycle of the clock signal is set shorter than time intervals of a data transfer request from a serial control part 3, so data can be transferred to a memory part without using a DMA controller like before, thereby lowering the cost.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a main CPU that executes programs and performs arithmetic processing, and a dedicated CPU that substitutes specific arithmetic processing among the arithmetic processing performed by the main CPU by a command from the main CPU. And a programmable controller having and.

[0002]

2. Description of the Related Art Conventionally, in order to reduce the load on the main CPU and reduce the processing time, there has been provided a programmable controller having a dedicated CPU that substitutes a specific arithmetic process among the arithmetic processes performed by the main CPU. FIG. 6 is a block diagram showing the configuration of such a conventional example. The dedicated CPU 11 is a high-speed arithmetic CPU, and executes specific arithmetic processing instead of the main CPU 10. Here, the main CPU 10 activates the special CPU 11 by setting various parameters required for specific arithmetic processing in a register (not shown) of the special CPU 11, and the special CPU 11 sends a hold (HOLD) signal to the main CPU 10. Is output. When the main CPU 10 receives the hold signal, the main CPU 10 outputs a response signal (ACK) to the dedicated CPU 11 to bring the operation into a stopped state (hold state). Then, during this period, the dedicated CPU 11 executes arithmetic processing, and when the processing is completed, the dedicated CPU 11 outputs a signal for releasing the hold state of the main CPU 10.
This releases the hold state of the main CPU 10,
The main CPU 10 executes other arithmetic processing. Further, when the dedicated CPU 11 reads out an instruction that cannot be executed by itself (instruction that can be executed only by the main CPU 10) during execution of the arithmetic processing, or when a stop request signal is input to the dedicated CPU 11 from the outside. Also, the dedicated CPU 11 suspends the processing and releases the hold state of the main CPU 10.

Further, in the above-mentioned conventional example, an internal timing clock signal (hereinafter abbreviated as "clock signal") from the timer section 12 is inputted to the interrupt port int of the main CPU 10 and the dedicated CPU 11. That is, the main CPU 1
When 0 is in the hold state, the interrupt request cannot be accepted. Therefore, in order to measure the elapsed time of the timer instruction executed by the main CPU 10, the clock signal is input to the dedicated CPU 11 as the stop request signal and the main CPU 10 once After the hold state is released, an interrupt request is issued to the main CPU 10 by a clock signal, and a process (timer interrupt process) for incrementing the count value of a counter (not shown) must be performed. For example, in the above-mentioned conventional example, the period of the clock signal is set to 2.5 ms in order to measure the elapsed time of the timer command of 10 ms with a precision of 1/4 (see FIG. 7).

By the way, in the above-mentioned conventional example, in order to perform data communication with a peripheral device (external device) such as a programming device, the serial controller 13 for communication uses the address data bus 14 for the main CPU 10 and the dedicated C.
It is connected to the PU 11 and the like. Further, the address data bus 14 has a memory unit 15 including a RAM (writable / erasable memory), and a DMA (which controls data transfer between the memory unit 15 and the serial control unit 13 in place of the main CPU 10). A direct memory access) controller unit (hereinafter abbreviated as “DMA unit 16”) is connected to the memory unit 15 for reading data to be transmitted to the outside from the memory unit 15 and for receiving data from the outside.
All writing to is controlled by the DMA unit 16. In this way, by controlling the data transfer between the serial control unit 13 and the memory unit 15 by the DMA unit 16, the serial control unit 13 causes the main C
Since a program or the like for interrupt processing to the PU 10 is not required, the load of software and the overall processing time and processing efficiency are improved.

[0005]

However, when the DMA unit 16 is used as in the above-mentioned conventional example, the DMA unit 16 is relatively expensive although there are various advantages, so that it is difficult to reduce the cost. There was a problem that it was expensive. The present invention is intended to solve the above problems, and an object of the present invention is to provide a programmable controller capable of cost reduction without lowering the processing efficiency of data transfer.

[0006]

In order to achieve the above-mentioned object, a main CPU for executing a program and performing arithmetic processing, and a specific arithmetic operation in the arithmetic processing performed by the main CPU are provided. A dedicated CPU that substitutes the processing in response to a command from the main CPU is provided, and the dedicated CPU suspends the operation of the main CPU while performing the specific arithmetic processing, and the specific arithmetic processing ends. In the programmable controller configured to release the operation stop state of the main CPU when or when it becomes necessary to perform an arithmetic process other than the specific arithmetic process or when a stop request signal is input from the outside, A serial control unit that performs data communication with the device and issues an interrupt request to the main CPU each time a predetermined segment of data is received; The transfer control is performed by a timer unit that generates a clock signal for operating the main CPU and outputs the clock signal to the dedicated CPU as the stop request signal, and the main CPU that receives an interrupt request from the serial control unit. And a memory unit for storing data received from an external device, wherein the serial control unit sets the cycle of the clock signal to a value equal to or less than a reception time required to receive the delimited data. In addition, the operation stop state of the main CPU is released in synchronization with the clock signal even during the execution of the specific arithmetic processing in the dedicated CPU, and the time interval at which the interrupt request from the serial control unit is generated, that is, the serial control is performed. Time shorter than the reception time required to receive the data in one section The main CPU is ready for operation at intervals, it is possible to control the data transfer between the serial controller and the memory unit by the main CPU. That is, data transfer can be performed between the serial control unit and the memory unit even during execution of arithmetic processing of the dedicated CPU without using an expensive DMA controller as in the conventional example, and the processing efficiency of data transfer is not deteriorated. Cost reduction is possible.

According to a second aspect of the present invention, in the first aspect of the present invention, the cycle of the clock signal is set to a divisor of the timer time in the timer instruction executed by the main CPU, and the main CPU is in an operable state. Therefore, the period of time becomes equal to the period of time measurement for the timer command, and the time measurement can be easily performed with a predetermined accuracy. According to a third aspect of the present invention, in the second aspect, the communication speed of data communication in the serial control unit is 1920.
The bit length is 0 bit per second, and the data length of the delimited data is 10 bits or more, and the cycle of the clock signal is about 500 μsec. Since the main CPU returns to the operable state about every 500 μsec. Even in the above communication format in which the serial control unit issues an interrupt request every approximately 520.8 μsec at the shortest, DM
The data transfer process can be efficiently performed without using the A controller.

[0008]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings. FIG. 1 is a block diagram showing the basic configuration of the programmable controller of the present embodiment, which includes a main CPU 1 that executes a program and performs arithmetic processing,
A dedicated CPU 2 which substitutes a specific arithmetic processing among the arithmetic processing performed by the main CPU 1 by a command from the main CPU 1;
A serial control unit 3 that performs data communication with an external device and issues an interrupt request to the main CPU 1 each time a predetermined segment of data is received, a timer unit 4 that generates a clock signal for the operation of the main CPU 1, and a serial control The memory unit 5 stores the data received from the external device under the transfer control by the main CPU that receives the interrupt request from the unit 3. It should be noted that these units are connected to the main CPU 1 and the dedicated C by the address data bus 6.
Each is connected to PU2. Further, the clock signal of the timer unit 4 and the interrupt request signal of the serial control unit 3 are input to the interrupt control unit 7, and the predetermined bits of the register included in the interrupt control unit 7 are the clock signal and the interrupt request signal. By changing
The main CPU 1 can individually recognize the interrupt requests of the timer unit 4 and the serial control unit 3.

As described in the conventional example, the dedicated CPU 2 executes a specific arithmetic processing in place of the main CPU 1. Therefore, while the dedicated CPU 2 is performing the arithmetic processing, the main CPU 1 is in a hold state (stops operation). State) and the arithmetic processing of the dedicated CPU 2 is completed, or the dedicated CP
Hold of the main CPU 1 when it becomes necessary to perform arithmetic processing other than specific arithmetic processing, such as when U2 reads an instruction to be executed by the main CPU 1, or when a stop request signal is input from the outside. The condition is canceled. When the main CPU 1 is in the hold state, the interrupt request from the interrupt control unit 7 cannot be accepted.

The memory section 5 connected to the address data bus 6 is composed of a writable / erasable semiconductor memory such as a RAM. Further, as will be described later, the present embodiment does not include a DMA controller, and data transfer between the serial control unit 3 and the memory unit 5 is controlled by the main CPU 1. The serial control unit 3 performs data communication with an external device such as a programming device and has, for example, a 1-byte buffer, and issues an interrupt request each time 1-byte data is received in the buffer. Then, the data is sent to the address data bus 6 bit by bit, or the data is fetched bit by bit.

The timer section 4 generates a clock signal composed of a pulse signal of a constant cycle and outputs it to the interrupt control section 7 and the dedicated CPU 2. Here, the clock signal input to the dedicated CPU 2 becomes a stop request signal, and for example, every time the clock signal rises to the H level, the dedicated CP
U2 interrupts the arithmetic processing being executed and the main CPU1
The hold state of is released. On the other hand, when the clock signal is input to the interrupt control unit 7, an interrupt request (hereinafter, referred to as “timer interrupt request”) from the timer unit 4 is issued to the main CPU 1 whose hold state has been released. However, the above operation is performed when the specific arithmetic processing is executed by the dedicated CPU 2, and when the main CPU 1 is executing the arithmetic processing without the dedicated CPU 2 operating, only the timer interrupt request is issued. Done.

Next, the operation of this embodiment will be described with reference to the flow charts of FIGS. First, FIG. 2 is a flow chart showing the entire operation. As with the general operation of a programmable controller, various hardware and parameters are initialized by turning on the power, and then a user program is executed to execute I / O. O refresh,
The calculation process and the communication command execution process are repeated.

FIG. 3 shows the main CPU 1 and the special CPU 2 when the special CPU 2 executes a particular calculation process that requires particularly high speed processing among the main CPU 1.
3 is a flowchart showing each operation of First,
When the main CPU 1 reads an instruction (command) to be processed by the dedicated CPU 2, it sets various parameters in the register of the dedicated CPU 2 and activates the dedicated CPU 2.

On the other hand, from the activated dedicated CPU 2 to the main CPU
The HOLD signal is output to 1 and the main CPU 1 enters the hold state. As a response to receiving the HOLD signal, an ACK signal (acknowledge signal) is output from the main CPU 1 to the dedicated CPU 2. Then, the dedicated CPU 2 performs arithmetic processing if the read instruction is an executable instruction, and interrupts the arithmetic processing when an unexecutable instruction (for example, an instruction to be executed by the main CPU 1) is read. The hold state of the CPU 1 is released and the control is returned to the main CPU 1. If a stop request signal or a clock signal from the timer unit 4 is input from the outside while the dedicated CPU 2 is executing the arithmetic processing, the hold state of the main CPU 1 is similarly released. On the other hand, if the stop request signal or the clock signal is not input, the specific arithmetic processing is continued until the end, and when it is ended, the hold state of the main CPU 1 is released and the control is returned to the main CPU 1.

On the other hand, when the hold state is released, the main CPU 1 investigates the cause of the release, and if it is an execution instruction of the main CPU 1, executes its arithmetic processing. At this time, the main CP
U1 checks whether there is a timer interrupt request from the interrupt control unit 7 or an interrupt request from the serial control unit 3 (hereinafter referred to as "data transfer interrupt request"), and responds to each interrupt request. 2), that is, the timer interrupt processing routine or the data transfer processing routine is executed. After the processing of each routine is completed, the dedicated C is again used.
By starting the PU2, the arithmetic processing interrupted by the dedicated CPU2 is continued.

FIG. 4 is a flow chart of the timer interrupt processing routine. Main CPU 1 is an auxiliary counter (not shown)
Is decremented, and if the count value is not zero, the timer interrupt processing routine is terminated and the original processing is returned to. On the other hand, if the count value of the auxiliary counter is zero, set the initial value (= 5) to the auxiliary counter and
After incrementing the counter (not shown), the timer interrupt processing routine is terminated and the original processing is returned to. That is,
In this embodiment, the cycle of the clock signal of the timer unit 5 is set to 50.
Since it is set to 0 μs, the main CPU 1 executes the timer interrupt processing routine in synchronization with the cycle of the clock signal (500 μs).
The count value of the auxiliary counter is reset to the initial value (=
Decrement from 5) to 0. As a result, the main CPU 1 measures the time of 500 μs × 5 = 2.5 ms, and it is possible to measure the elapsed time for the 10 ms timer command with a precision of 1/4 as in the conventional example.

FIG. 5 is a flowchart of the data transfer processing routine. If there is a data transfer interrupt request, the main CPU 1 branches to a data transfer processing routine, reads 1 byte of received data from the serial control unit 3, and reads a pointer of a reception buffer (not shown).
This pointer indicates the address of the memory unit 5, and the main CPU 1 stores the received data in the memory unit 5 by setting the received data at the read address of the pointer. Then, in preparation for the next set of received data,
The main CPU 1 increments the reception pointer, ends the data transfer processing routine, and returns to the original processing.

Here, the format of the data communication performed between the external device and the serial control unit 3 is, for example, asynchronous communication, with a start bit of 1 bit, a data length of 8 bits, a parity odd number, and a stop bit. Is 1 bit and the communication speed is 19200 bps. In this case, the time interval from the reception of one segment of data by the serial control unit 3 until the reception of the next segment of data is completed, that is, the time interval of the data transfer interrupt request from the serial control unit 3 is 1 ÷ 192
00 × (1 + 8 + 1 + 1) = 572.9 μs. Also, another format (1 stop bit, 7 data length, parity parameter, 1 stop bit)
Bit), the time interval is 1 ÷ 19200 ×
(1 + 7 + 1 + 1) = 520.8 μs.

Therefore, in the case of a communication format in which the communication speed is 19200 bps and the data of one segment is 10 bits or more, the data transfer interrupt request from the serial control unit 3 is made at a time interval shorter than 520.8 μs. Since it is not performed, if the main CPU 1 is returned to the operable state at a time interval shorter than this,
The main CPU 1 can control the data transfer between the serial control unit 3 and the memory unit 5 without using a DMA controller as in the conventional example, and the cost can be reduced by not using an expensive DMA controller. .
Therefore, in this embodiment, the cycle of the clock signal of the timer unit 4 is set to 500 μs and the clock signal is set to the dedicated CP.
It is used as a stop request signal for U2. Further, by setting the cycle of the clock signal to 500 μs, the cycle of the clock signal becomes a divisor of the count time (2.5 ms) of the 2.5 ms counter for measuring the elapsed time of the 10 ms timer command, which is the same as the conventional example. Moreover, the elapsed time of the timer command can be measured.

As described above, in the present embodiment, the timer in the timer command executed by the main CPU 1 is less than or equal to the reception time (520.8 μs) required for the serial control unit 3 to receive one segment of data. 500 μs, which is a divisor (maximum common divisor) of time (2.5 ms)
Since the period of the clock signal of the timer unit 4 is set to, the main CPU 1 returns from the hold state to the operable state in synchronization with the period of the clock signal even during execution of the arithmetic processing by the dedicated CPU 2, and during this period. If there is a data transfer interrupt request from the serial control unit 3, the data transfer processing routine can be executed to transfer the received data from the serial control unit 3 to the memory unit 5. That is, the cost can be reduced without using the DMA controller, and the load on the main CPU 1 can be reduced by minimizing the number of software interrupts.

[0021]

According to the first aspect of the present invention, a main CPU that executes a program and performs arithmetic processing, and a dedicated arithmetic processing among the arithmetic processing performed by the main CPU are executed by a command from the main CPU. CPU, and the dedicated CPU
Is the main CPU while performing the specific arithmetic processing.
The operation of the main CPU when the specific arithmetic processing is completed or when it is necessary to perform an arithmetic processing other than the specific arithmetic processing or when a stop request signal is input from the outside. In a programmable controller configured to release a stopped state, a serial control unit that performs data communication with an external device and issues an interrupt request to the main CPU each time a predetermined segment of data is received, and the operation of the main CPU And a timer unit that generates a clock signal for use as a stop request signal and outputs the clock signal to the dedicated CPU, and the main CPU that receives an interrupt request from the serial control unit performs external transfer control. A memory unit for storing the data received from
Since the cycle of the clock signal is set to a value that is less than or equal to the reception time required to receive the one segment of data in the serial control unit, it is synchronized with the clock signal even during execution of a specific arithmetic process in the dedicated CPU. Master C
The main CP is released at a time interval when the operation stop state of the PU is released and the interrupt request from the serial control unit is generated, that is, a time interval which is shorter than the reception time required for the serial control unit to receive the delimited data.
U becomes operable, the data transfer between the serial control unit and the memory unit can be controlled by the main CPU, and the arithmetic processing of the dedicated CPU is being executed without using an expensive DMA controller as in the conventional example. Moreover, there is an effect that data transfer can be performed between the serial control unit and the memory unit, and the cost can be reduced without lowering the processing efficiency of the data transfer.

According to the second aspect of the present invention, the cycle of the clock signal is set to a divisor of the timer time in the timer instruction executed by the main CPU, so that the cycle in which the main CPU becomes operable is for the timer instruction. This coincides with the period of time measurement, and there is an effect that such time measurement can be easily performed with predetermined accuracy. According to a third aspect of the present invention, the communication speed of the data communication in the serial control unit is 19200 bits per second, and the data length of the delimited data is 10 bits or more, and the cycle of the clock signal is about 500 μsec. , Lord C
Since the PU returns to the operable state about every 500 μsec,
Even in the above communication format in which the serial control unit issues an interrupt request every 520.8 μsec at the shortest, the data transfer process can be efficiently performed without using the DMA controller.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment.

FIG. 2 is a flowchart for explaining the operation of the above.

FIG. 3 is a flowchart for explaining the operation of the above.

FIG. 4 is a flowchart for explaining the operation of the above.

FIG. 5 is a flowchart for explaining the operation of the above.

FIG. 6 is a block diagram showing a conventional example.

FIG. 7 is a flowchart for explaining the operation of the above.

[Explanation of symbols] 1 main CPU 2 dedicated CPU 3 serial control unit 4 timer unit 5 memory unit 6 address data bus 7 interrupt control unit

Claims (3)

[Claims] 1. A main C for executing a program and performing arithmetic processing.
The CPU includes a PU and a dedicated CPU that substitutes specific arithmetic processing among the arithmetic processing performed by the main CPU in response to a command from the main CPU. The dedicated CPU is provided while performing the specific arithmetic processing. Putting the main CPU into an inoperative state,
When the specific arithmetic processing is completed, or when it becomes necessary to perform arithmetic processing other than the specific arithmetic processing, or when a stop request signal is input from the outside, the main C
In a programmable controller configured to release the operation stop state of a PU, a serial control unit that performs data communication with an external device and issues an interrupt request to the main CPU every time a predetermined segment of data is received; Transfer control is performed by a timer unit that generates a clock signal for operating the CPU and outputs the clock signal as the stop request signal to the dedicated CPU, and the main CPU that receives an interrupt request from the serial control unit. And a memory unit for storing data received from an external device, and the cycle of the clock signal is set to a value equal to or less than a reception time required to receive the delimited data in the serial control unit. And programmable controller. 2. The programmable controller according to claim 1, wherein a cycle of the clock signal is set to a divisor of a timer time in a timer instruction executed by the main CPU. 3. The serial control unit has a data communication speed of 19200 bits per second, and the data length of the delimiter data is 10 bits or more, and the cycle of the clock signal is about 500 μsec. The programmable controller according to claim 2.