JP2625573B2 - Direct memory access controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial application field) The present invention relates to a method for transferring data by direct memory access (DMA) in a serial printer without stopping the DMA operation. The present invention relates to a direct memory access control device which enables a CPU memory direct access operation at the timing of (1).

(Prior Art) Conventionally, in a serial printer, information sent from an external device is processed by a program of a CPU, converted into character information, and printed.

FIG. 2 is a block diagram of a conventional serial printer.

In the figure, reference numeral 1 denotes an interface circuit for receiving information sent from an external device and returning information from the serial printer to the external device as necessary. Stored processing procedure (for example, CPU2a program)
Is a control circuit that processes information according to
a, a DMA control circuit 2b and the like.

Reference numeral 3 denotes a storage circuit (A) for storing graphic information to be printed by a serial printer, which is generally called a character generation circuit. The storage circuit (A) 3 includes a ROM, a RAM, an external storage device, and the like.

Reference numeral 4 denotes a storage circuit (B) for temporarily storing information edited by the control circuit 2 based on information received via the interface circuit 1, and is configured by a RAM.

Reference numeral 5 denotes a mechanism control circuit for driving the serial printer mechanism 6.

FIG. 3 is a block diagram of the control circuit and the storage circuit of FIG.

In the figure, 2a is a CPU, 7 is a program ROM storing a program for driving the CPU 2a, 8 is an instruction decoding / information editing circuit section, and in addition to the instruction decoding / information editing circuit 8a, DM
A control circuit 2b is included. Since reading and writing of information from the storage circuit (A) 3 to the storage circuit (B) 4 or transfer of information between areas in the storage circuit (B) 4 involves many simple operations such as data transfer, the CPU 2a The processing is performed by DMA operation without intervening to speed up the processing.

That is, the storage location (address) and information amount (size) of information to be read from the storage circuit (A) 3 and the storage location (address) of information to be written to the storage circuit (B) 4
From the CPU 2a, and after that, the DMA control circuit 2b
Independently reads information from the storage circuit (A) 3 and writes the information to the storage circuit (B) 4 by DMA transfer. The transfer of information between areas in the storage circuit (B) 4 is performed in the same manner.

(Problems to be Solved by the Invention) However, in the above-described conventional direct memory access control device, once the DMA control circuit 2b starts operating, it is separated from the control of the CPU 2a. If the information to be processed by the CPU 2a occurs in 1, the DMA operation must be temporarily suspended by the DMA operation stopping means.

Then, after the processing is completed, the CPU 2a controls the DMA control circuit.
2b is restarted, but the processing required for this restart is complicated, and the speed is impaired.

The present invention solves the above-mentioned problems of the conventional direct memory access control device, and provides a direct memory access control device capable of stopping and restarting the DMA operation without requiring special processing by the CPU. The purpose is to provide.

(Means for Solving the Problems) For this purpose, in the direct memory access control device of the present invention, a CPU, an instruction decoding / information editing circuit, a first storage circuit for storing graphic information for printing, A second storage circuit for temporarily storing information edited by the instruction decoding / information editing circuit, transfer of information from the first storage circuit to the second storage circuit, and between areas in the second storage circuit; And a DMA control circuit for transferring the information.

The DMA control circuit detects a control signal generated along with the start and end of the memory access by the CPU, generates a switching signal, and selectively generates an address update signal. An address generation circuit that updates the DMA address in response to the address update signal, and an address control circuit that switches between the CPU address and the DMA address in response to the switching signal.

(Operation) According to the present invention, in the direct memory access control device as described above, the CPU, the instruction decoding / information editing circuit, the first storage circuit for storing graphic information for printing, and the instruction A second storage circuit for temporarily storing the information edited by the decoding / information editing circuit, transfer of the information from the first storage circuit to the second storage circuit, and transfer between areas in the second storage circuit; A DMA control circuit for transferring information.

The DMA control circuit detects a control signal generated along with the start and end of the memory access by the CPU, generates a switching signal, and selectively generates an address update signal. An address generation circuit that updates the DMA address in response to the address update signal, and an address control circuit that switches between the CPU address and the DMA address in response to the switching signal.

In this case, the first and second storage circuits are connected to a DMA control circuit, and the DMA control circuit transfers information from the first storage circuit to the second storage circuit and stores information in the second storage circuit. Information is transferred between the areas.

Further, the DMA control circuit, when the CPU outputs a control signal for performing memory access, detects the control signal,
Switches between DMA operation and CPU operation.

Then, at the time of DMA operation, the timing generation circuit generates an address update signal and sends it to the address generation circuit, and the address generation circuit receives the address update signal and updates the DMA address.

Further, the timing generation circuit generates a switching signal and sends it to an address control circuit. The address control circuit receives the switching signal, selects a DMA address, and transfers a DMA address from the first storage circuit to the second storage circuit. Transfer of information or transfer of information between areas in the second storage circuit is performed.

On the other hand, when the timing generation circuit stops the address update signal during the operation of the CPU, the address generation circuit stops updating the DMA address.

Further, the timing generation circuit generates a switching signal and sends it to the address control circuit. The address control circuit receives the switching signal and selects a CPU address. As a result, memory access by the CPU is performed.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a direct memory access control device showing an embodiment of the present invention.

In the figure, 2a is a CPU, 7 is a program ROM, 9 is an instruction decoding and information editing circuit, 9a is an instruction decoding and information editing circuit,
9b is a DMA control circuit. 3 is a memory circuit (A) (hereinafter referred to as “R
OM ". ), 4 is a storage circuit (B) (hereinafter referred to as "RAM"), 10 is an address / data bus between the CPU 2a and the instruction decoding / information editing circuit section 9, and 11 is the instruction decoding / information editing circuit section 9 and ROM3. Address / data bus between the RAM and the RAM4.

FIG. 4 is a block diagram of a DMA control circuit of the direct memory access control device of the present invention.

In the figure, 12 is a transfer destination address counter, 13 is a transfer destination address counter, 14 is a transfer byte number counter, 15 is a timing generation circuit, and 16 is an address control circuit. The source address counter 12 and the destination address counter 13 constitute an address generation circuit.

The switching signal between the DMA operation and the CPU operation is output from the timing generation circuit 15, and the address control of the ROM 3 and the RAM 4 is performed by the transfer source address counter 12, the transfer destination address counter 13, the transfer byte number counter 14, and the address control circuit 16. Will be

FIG. 5 is a block diagram of an address control circuit of the direct memory access control device of the present invention.

In the figure, reference numeral 20 denotes a ROM address selector, and reference numeral 21 denotes a RAM address selector. The address control circuit 16 has a CPU address 22 and the transfer source address counter 1 described above.
Transfer source address 2 as DMA address output from 2
3, and DMA output from the transfer destination address counter 13
A transfer destination address 24 is input as an address, and an output address to the ROM 3 and the RAM 4 is selected by a DMA control signal (DMASEL signal 19 and TRCH signal 18) output from the timing generation circuit 15.

FIG. 6 is a block diagram of a DMA control signal generation circuit in the timing generation circuit.

In the figure, the timing of the PSEN signal and the ALE signal output from the circuit of the CPU 2a is the input condition of the flip-flops FF1 to FF5, and the delay timing synchronized with the CLK signal is generated in each of the flip-flops FF1 to FF5. A DMA control signal is output.

Next, the operation of each circuit of the direct memory access control device will be described based on a time chart.

FIG. 7 is a time chart of the timing generation circuit.

CPU 2a follows the procedure written in program ROM 7
It processes information input from an external device via the interface circuit 1 (see FIG. 2). When the DMA operation is requested, the CPU 2a determines the transfer destination address 24 allocated in the RAM 4, the transfer source address 23 of the character to be transferred in the ROM 3 (for example, a character pattern generation ROM), and the transfer amount (the number of transfer bytes). ) Is calculated, and each set value is set to the fourth value in the DMA control circuit 9b.
These are set in the transfer source address counter 12, the transfer destination address counter 13, and the transfer byte number counter 14 shown in FIG.

Thereafter, when the CPU 2a generates a PSEN signal and an ALE signal as control signals, the DMA control circuit 9b transmits the PSEN signal and the ALE signal.
The signal is detected, the instruction decoding / information editing circuit unit 9 and the ROM 3 and
A DMA operation is started with the RAM 4 via the address / data bus 11. At this time, the CPU 2a independently accesses the program ROM 7 via the CPU address / data bus 10.

In the DMA operation, information is transferred from the ROM 3 to the RAM 4 (hereinafter referred to as “ROM → RAM transfer”), and information is transferred between areas in the RAM 4 (hereinafter referred to as “RAM → RAM transfer”). ). During DMA operation, ROM3 and RAM4
The control is performed without passing through the PU 2a, and the DMA control signal is output by the timing generation circuit 15 (FIG. 4) of the DMA control circuit 9b.

The timing generation circuit 15 receives a PSEN signal, an ALE signal, a WR signal, an RD signal output from a circuit (not shown) of the CPU 2a, and a CLK signal that is a basic clock of the CPU 2a.
The timing shown in FIG. 7 is generated.

Here, the FF signal to FF signal and the DMASEL signal shown in (5) to (10) of the time chart of FIG. 7 are output from the DMA control signal generation circuit (FIG. 6) in the timing generation circuit 15.

In the DMA control signal generation circuit of FIG. 6, the ALE signal and the PSEN signal, which are the output signals of the CPU 2a, are input to the AND gate AG1, and the output signal of the AND gate AG1 is synchronized with the output signal CLK signal (not shown) of the CPU 2a. Then, time delay is performed by five stages of flip-flops FF1 to FF5. Then, the FF signal that is the output signal of the flip-flop FF1, the output signal of the AND gate AG3 that receives the FF signal that is the output of the flip-flop FF3, and the PSEN signal output from a circuit (not shown) are supplied to the AND gate AG2. Is entered. The output signal of the AND gate AG2 is a flip-flop FF6
And its output signal is the DMAS shown in (10) of FIG.
This becomes the EL signal 19 (a signal for switching between DMA operation and CPU operation).
ROM3, RAM at "ROM → RAM transfer" or "RAM → RAM transfer"
The various control signals of 4 are shown in (11) of the time chart of FIG.
To (16).

Next, referring to FIG.
Is a circuit for selecting an address of the ROM 3 or the RAM 4 in the CPU mode or the DMA mode. That is, the CPU address 22, the source address 23 output from the source address counter 12 (FIG. 4), and the DMASEL signal 19 as its select signal are input to the ROM address selector 20.
The RAM address selector 21 has a CPU address 22, a transfer source address 23 output from the transfer source address counter 12 (FIG. 4), a transfer destination address 24 output from the transfer destination address counter 13, and its select signal. DM as
ASEL signal 19 and TRCH signal 18 output from a circuit not shown
(Output signal from the timing generation circuit 15 for switching the transfer source and transfer destination of the ROM 3 and the RAM 4 during the DMA transfer operation).

 Next, the DMA operation will be described.

When the start of the DMA operation is instructed by the CPU 2a, the M2 cycle (A) of FIG. 7 of the CPU 2a ((2), (3) of FIG. 7)
(When the ALE signal and the PSEN signal output from the CPU 2a are output synchronously), the DMASEL signal of (10) goes to the “0” level (ON state). Then, the output signal of the AND gate AG1 (FIG. 6) having the ALE signal and the PSEN signal as input signals is the basic timing, and “ROM → RAM transfer” or “RAM → RAM transfer” is performed. The control signals for the ROM3 and RAM4 are individually output according to the FF signals to FF signals shown in (5) to (9) of FIG. 7 and other conditions.

Here, the M1 cycle (A) of the CPU 2a continues, and the DMA operation is continued in the basic cycle of the output signal of the AND gate AG1 unless the CPU 2a accesses the external data memory. When setting the address of ROM3 and RAM4 during DMA operation,
A count-up clock 17 is output from the timing generation circuit 15 (FIG. 4) as an address update signal to the address value set before the DMA is started, and the transfer source address counter 12, the transfer destination address counter 13, and the transfer are performed. The byte number counter 14 counts up and outputs an address value to the address control circuit 16.

Here, when a DMA stop request is issued during DMA operation (when CPU 2a performs memory direct access)
Indicates that the CPU 2a has M2 cycles (B) (AL output from the CPU 2a)
E signal and PSEN signal are output asynchronously). That is, when the CPU 2a is in the M2 cycle (B), the PSEN signal and the ALE signal become asynchronous and the PSEN signal maintains the "1" level, so that the DMASEL signal becomes "1" as shown in FIG. Level (off state). By this DMASEL signal, ROM3, R
The output of various control signals indicated by (11) to (16) of AM4 is stopped, and the CPU address 22 is selected by the ROM address selector 20 and the RAM address selector 21, and the control of the ROM3 and RAM4 depends on the CPU 2a. Become. At this time, since the output of the count-up clock 17 (FIG. 4) also stops, the DMA
The address value at the time of operation stop is retained. Thus CPU2
When the external data memory is accessed by a, the DMA operation is stopped in the DMA control circuit 9b (FIG. 1) without the intervention of the CPU 2a.

When the external data memory access by the CPU 2a is completed (after the M2 cycle (B)), the CPU 2a enters the M1 cycle (A), so that the ALE signal and the PSEN signal are synchronously output again.
As a result, the DMASEL signal becomes “0” as shown in FIG.
Level (on state), the FF signal to the FF signal are output, and the RO indicated by (11) to (16) in FIG.
The output of the control signals of M3 and RAM4 also starts from the timing generation circuit 15, and the DMA operation starts from the address value when the DMA operation is stopped.

When ending the above DMA operation, the timing generation circuit 15
, A count-up clock 17 is output, and the transfer byte number counter 14 counts up. When the value becomes a preset value, the timing generation circuit
15, the transfer source address counter 12 and the transfer destination address counter 13 are reset, the DMA mode is released, and the DMA operation ends.

In FIG. 7, the RAS signal in (11) and the C signal in (12)
The AS signal, the RAMRD signal of (15), the RAMWR signal of (14) and (16), and the RAMAD signal of (18) to (20) are time charts when a dynamic RAM is used for RAM4. R and C are the row address and column address of the dynamic RAM.

It should be noted that the present invention is not limited to the above embodiments, and various modifications are possible based on the gist of the present invention, and they are not excluded from the scope of the present invention.

(Effects of the Invention) As described in detail above, according to the present invention, in a direct memory access control device, a CPU, an instruction decoding / information editing circuit, and a first memory for storing graphic information for printing. A storage circuit, a second storage circuit for temporarily storing information edited by the instruction decoding / information editing circuit, a transfer of information from the first storage circuit to the second storage circuit, and a second storage circuit DMA for transferring information between areas within
A control circuit.

The DMA control circuit detects a control signal generated along with the start and end of the memory access by the CPU, generates a switching signal, and selectively generates an address update signal. An address generation circuit that updates the DMA address in response to the address update signal, and an address control circuit that switches between the CPU address and the DMA address in response to the switching signal.

In this case, direct memory access by the CPU is required during the DMA operation, and when the CPU generates a control signal, the DMA control circuit detects the control signal and starts the CPU operation,
The timing generation circuit stops the address update signal, and the address generation circuit stops updating the DMA address and holds the DMA address.

Further, the timing generation circuit generates a switching signal and sends it to the address control circuit. The address control circuit receives the switching signal and selects a CPU address.

Subsequently, the direct memory access by the CPU ends and C
When the PU generates a control signal, the DMA control circuit detects the control signal and restarts the DMA operation, the timing generation circuit generates an address update signal, and the address generation circuit performs DMA from the held DMA address. Start updating the address.

Further, the timing generation circuit generates a switching signal and sends it to an address control circuit. The address control circuit receives the switching signal and selects a DMA address.

As described above, when the CPU generates a control signal at the start and end of the memory access, the DMA control circuit
The control signal is detected and the DMA operation is stopped or restarted without receiving special processing by the PU.

Therefore, when trying to start memory access, the CPU is not subject to restrictions due to the stop of the DMA operation, and can immediately start memory access and execute predetermined processing.

Further, the DMA operation is stopped and restarted by the DMA control circuit without receiving any special processing by the CPU.
Therefore, the processing efficiency of the CPU can be improved accordingly.

[Brief description of the drawings]

FIG. 1 is a block diagram of a direct memory access control device showing an embodiment of the present invention, FIG. 2 is a block diagram of a conventional serial printer, FIG. 3 is a block diagram of a control circuit and a storage circuit of FIG. FIG. 4 is a block diagram of a DMA control circuit of the direct memory access control device of the present invention, FIG. 5 is a block diagram of an address control circuit of the direct memory access control device of the present invention, and FIG. FIG. 7 is a block diagram of the circuit, and FIG. 7 is a time chart of the timing generation circuit. 2a CPU, 3 storage circuit (A), 4 storage circuit (B), 7 program ROM, 9 instruction decoding / information editing circuit section, 9a instruction decoding / information editing circuit, 9b …… DM
A control circuit, 10, 11 ... Address / data bus.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Toshiyuki Wada 1-1-1 Tatsuda, Shono, Fukushima-shi, Fukushima Prefecture Inside Oki Data Systems Co., Ltd. (72) Inventor Takao Uchida 1-7-112 Toranomon, Minato-ku, Tokyo Okiden (72) Inventor Jiro Tanuma 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Inside (72) Inventor Naoji Akutsu 1-7-12 Toranomon, Minato-ku, Tokyo Okiden (72) Inventor Tadashi Kasai 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (56) References JP-A-1-283659 (JP, A)

Claims (1)

(57) [Claims] (A) a CPU; (b) an instruction decoding / information editing circuit; (c) a first storage circuit for storing graphic information for printing; and (d) the instruction decoding / information editing. A second storage circuit for temporarily storing the information edited by the circuit; (e) transfer of information from the first storage circuit to the second storage circuit, and information between areas in the second storage circuit. And (f) the DMA control circuit detects a control signal generated at the start and end of the memory access by the CPU, generates a switching signal, and A timing generation circuit for selectively generating an address update signal, an address generation circuit for receiving the address update signal and updating a DMA address, and a CPU address and a DMA for receiving the switch signal.
A direct memory access control device comprising an address control circuit for switching between an address and an address.