JP2844624B2 - Data processing device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pulse output in machine control, and more particularly to a method of continuously outputting pulses.

[Conventional technology]

Recently, microcomputers are used in machine control. Basically, it is common to directly open / close a valve or drive a motor by a PWM output pulse output from a microcomputer.

FIG. 5 shows an example of a pulse output pattern in the case of performing a pulse output according to the prior art.

Hereinafter, a conventional pulse generator will be described with reference to FIGS. 6 and 7. FIG. FIG. 6 is a block diagram of a conventional pulse generator, and FIG. 7 is a block diagram of conventional peripheral hardware. 8 includes a CPU 800, a data bus 110, an address bus 111, an INTC (interrupt request circuit) 112, a program memory 113, a data memory 114, and peripheral hardware 115.
It is composed of

The CPU 800 is an arithmetic logic unit (hereinafter referred to as ALU) 1
01, temporary register 102, general-purpose register 103, address buffer 104 (represented by AB in the figure), micro address (hereinafter referred to as μ address) generation unit 105, μ ROM 10
6, a PC (program counter) 107, a PSW (program execution state holding register) 108, and a timing control unit 109.

The INTC 112 has an interrupt request flag 116 and outputs an interrupt request signal 117 to the timing control unit 109. Upon receiving the interrupt request, the timing control unit 109 outputs an interrupt request clear signal 118 to the INTC 112.

The INTC112 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects one interrupt source with the highest priority, and responds to that interrupt source The interrupt request flag 116 is set. Interrupt request flag 1
16 is set when there are n interrupt requests, but only one is shown in the figure. Further, an interrupt signal from external hardware, a priority determination unit, and the like are not particularly illustrated.

Conventional interrupt processing is usually called vector interrupt, and a vector table space is previously set in a memory space, and an entry address of an interrupt processing program corresponding to each interrupt source is stored in this space. When a vector interrupt occurs, the process branches to an entry address corresponding to the interrupt source.

Next, the configuration of the peripheral hardware 115 will be described with reference to FIG.

The peripheral hardware 115 compares the value of the timer 901 counting the clock φ with the value of the timer 901, and controls the output pulses by using three compare registers (hereinafter referred to as COMPT and COMP).
S, COMPR) 902, 903, 904, set / reset flip-flops that hold the output pulse level (hereinafter referred to as output F / F) 9
05 and a port P for outputting the value of the output F / F to the outside.

COMPT 902 is a compare register that defines the cycle of the output pulse, and a value corresponding to the cycle T0 of the output pulse is set in advance by the CPU 800. The COMPT 902 always performs a comparison operation with the timer 901 and outputs a match signal 912 when the value of the timer 901 held in the register matches. Similarly, COMPS903 and COMPR904 are compare registers that specify the pulse output start timing and the pulse output end timing of the output pulse, respectively, and always perform a comparison operation with the timer 901 to determine whether the value of the timer 901 and the value held in each register are equal. When they match, match signals 913 and 914 are output, respectively. All of these compare registers can be read and written from the CPU 800.

The coincidence signal 912 is input to the timer 901, and when this signal is input, the timer 901 is cleared to all "0". Thereby, the timer 901 functions as an interval timer that continuously counts from the count value 0 to T0.

Next, the control operation of the pulse output in this example will be described with reference to FIGS. 5 to 7. FIG. However, the output F / F 905 is reset, and the description will be made from the time when the output from the port P is at a low level.

In normal instruction processing, the program address stored in the PC 107 is transferred to the address buffer 104, drives the address bus 111, and the next instruction to be executed is fetched from the program memory 113.

The fetched instruction is transferred to the μ address generation unit 105 via the data bus 110. μ address generator 105
Generates the address of the μROM 106 from the instruction code. Thereafter, the instruction is processed by operating the ALU 101, the temporary register 102, the general-purpose register 103, and the like in accordance with the instruction of the μ program corresponding to the instruction stored in the μ ROM 106.

The INTC112 continuously samples whether or not an interrupt request has been generated from peripheral hardware, independently of the processing of the CPU 800. If a request has been generated, the INTC112 selects one request and the interrupt request corresponding to the source. The flag 116 is set.

By the way, when the value of COMPS903 matches the value of timer 901, C
The OMPS 903 outputs a match signal 913, and the output F /
The output from port P is set to high level by setting F905. (FIG. 5—timing t1, t4, t7) Further, the coincidence signal 913 is input to the INTC 112, which generates an interrupt request to the INTC 112, and the INTC 112 receives the request.
If the break request flag 116 is set, an interrupt request signal 117 is output to the timing control unit 109.

At the last timing of execution of each instruction, it is a timing for detecting whether or not the normal interrupt has occurred. At this timing, the timing control unit 109 samples the presence or absence of the interrupt request signal 117. If the interrupt request signal 117 is active, the interrupt request is accepted, an interrupt request clear signal 118 is output to the INTC 112, and the interrupt request flag 116 is cleared.

Next, the PC 107 and the PSW 108 are saved in a stack space indicated by a stack pointer (a register set in the CPU 800 but not shown), and stored in a vector table set at a specific address in the data memory 114. The entry address of the interrupt processing program corresponding to the stored interrupt source is read, and the data bus 110 is read.
Set to PC107 via The execution of the interrupt processing program is started from the program address newly set in the PC 107.

The interrupt processing program based on the interrupt processing request by the coincidence signal 913 is an interrupt processing for setting the pulse output start timing of the pulse output from the port P in the next cycle.
In the interrupt processing started at the timing t1 of S1, the pulse output start timing of the next cycle is sequentially set, such as setting the timing t4 of the next cycle S2. At this time, the CPU 901 sets the timer 901 to all “ The data corresponding to the period from when the signal is cleared to "0" until the pulse output is activated is set in the COMPS903.

In the naming process that terminates the interrupt processing program,
The PC value and PSW value saved in the stack space are stored in PC10, respectively.
7. By returning to PSW108, processing is restarted from the next instruction at the time when the interrupt occurred.

Next, when the value of COMPR904 matches the value of timer 901, C
The OMPR904 outputs the coincidence signal 914, and the output
By resetting the F / F 905, the pulse output from the port P is set to a low level. (Fig. 5-Timing t2, t5, t
8) Also, the match signal 914 is input to the INTC 112, generates an interrupt request to the INTC 112, the INTC 112 accepts the request, and if the interrupt request flag 116 is set, the interrupt request signal 117 is sent to the timing control unit 109. Is output.

At the last timing of instruction execution, the timing controller
109 samples the presence or absence of the interrupt request signal 117.

If the interrupt request signal 117 is active, an interrupt request clear signal 117 is output to the INTC 112 to clear the interrupt request flag 116, similarly to the interrupt processing started by the coincidence signal 913.

Next, the stack is saved in the stack space of the PC 107 and the PSW 108, and a branch is made to an entry address of an interrupt processing program corresponding to the interrupt source stored in the vector table set at a specific address in the data memory 114. Starts execution.

The interrupt processing program based on the interrupt processing request by the coincidence signal 914 is an interrupt processing for setting the pulse output end timing of the pulse output from the port P in the next cycle. For example, in FIG.
In the interrupt process started at the timing t2, the next cycle S2
As in the case of setting the timing t5, the pulse output end timing of the next cycle is sequentially set. At this time, CPU8
In the case of 00, the pulse width of the output pulse is set by setting the data corresponding to the period from when the timer 901 is all cleared to “0” in the COMPR 904 to when the pulse output is reset to the COMPR 904.

In the processing of the instruction to end the interrupt processing program,
The PC value and PSW value saved in the stack space are
By returning to 107 and PSW 108, the processing is restarted from the next instruction at the time when the interrupt occurred.

As described above, the pulse output from the port P is directly controlled by the coincidence signals 913 and 914 output from the COMPS903 and COMPR904, and the pulse output output in the next cycle is performed by the interrupt processing started by these signals. The pulse output start timing and the pulse output end timing are set. Therefore, by repeating this operation, the pulse output from the port P and the control of the pulse output can be continuously performed. Although the above description shows one example of various pulse output control methods, control is basically performed by a similar processing method.

[Problems to be solved by the invention]

As described above, the conventional pulse generator receives the signal for starting the pulse output and the signal for terminating the pulse output as an interrupt signal, and according to the interrupt processing program, the timing of starting the pulse output to be output in the next cycle. Since the end timing is set, when the PC and PSW are saved to the stack space at that time and when returning from the interrupt processing program to the main processing, the processing of returning the contents of the stack to the PC and PSW frequently occurs. Therefore, the higher the frequency of the output pulse, the more it is divided into evacuation and return
The ratio of CPU time becomes huge.

In addition, the CPU executes various programs such as other data processing in addition to controlling the pulse. If a long time is required for the interrupt processing for controlling the pulse output, the CPU time is divided into the main processing. Is reduced, and in some cases, processing that cannot be performed at all may occur.

Further, in FIG. 5, if the value set as the pulse output start timing (timing t7) of the next cycle S3 by the interrupt processing of the cycle of S2 is larger than the current timer count value, Even if the setting is performed with the intention of designating the pulse output timing, a coincidence signal for starting pulse output is generated again in the current cycle S2 (timing tX). Therefore, when the pulse output of the current cycle S2 has been completed, an event occurs that the pulse output is started without waiting for the next cycle S3. The pulse output at this time has a period of timing tX to t6 to t7 to t8,
The pulse output will be over two cycles.

Since the pulse output as described above is different from the originally intended start and end timings of the pulse output and a pulse having an unintended pulse width is output, for example, the output width of the pulse is the control amount itself. In such a case, there is a serious problem that erroneous control is performed on the control target. Moreover, in order to prevent or correct this, a dedicated program process is required.
When added to the interrupt processing for setting the start and end timings of the pulse output, the time required for the interrupt processing of the pulse output control is further increased as a whole.

[Means for solving the problem]

A data processing apparatus according to the present invention includes a program counter for holding an instruction execution address, a unit for holding a program execution state, a general-purpose register, and a microprogram ROM.
A data processing device having a central processing unit, an interrupt request generating circuit that asynchronously generates an interrupt processing request to the central processing device, a program memory, a data memory, and a peripheral circuit. And a plurality of comparison registers for comparing with the timer,
An output port for outputting a pulse, wherein the interrupt request generating circuit generates a request for a predetermined data processing in addition to the generation of the interrupt processing request, and outputs the interrupt processing request and the request for the predetermined data processing. Processing instruction information for specifying a processing mode of the predetermined data processing, and the interrupt request generating circuit receives a request for the predetermined data processing from the interrupt request generation circuit. When issued to the central processing unit, the central processing unit interrupts the instruction execution process when detecting that the configuration instruction means is instructing the predetermined data processing, and According to the information, predetermined data in the data memory is compared with the value of the timer or the value of the comparison register at the timing, and the comparison result is determined by a predetermined condition. Means for transferring data to the predetermined comparison register at the time of controlling the generation of a pulse from the output port, and when the comparison result is not a predetermined condition, an interrupt request from the interrupt generation circuit to the central processing unit. Is generated.

Further, in the data processing device of the present invention, a timer that performs an increment operation by a clock, a first register that stores first word data, and a second word data that is larger than the first word data are stored. A second register, a first comparison circuit for detecting that the count value of the timer matches the first word data stored in the first register and activating a first control signal, the timer A peripheral circuit including a second comparison circuit that detects that the count value of the second control signal matches the second word data stored in the second register and inactivates the first control signal; The first register is responsive to a first control signal being activated and when the third word data to be written is less than or equal to the first word data. When the third word data is written, and when the third word data is larger than the first word data, the writing of the third word data to the first register is stopped and the writing is not completed. And writing means for storing certain data and writing fourth word data to the second register in response to the first control signal becoming inactive.

As described above, according to the present invention, when the start and end timing signals of the pulse output are received as the interrupt request signal,
Continuous pulse output from ports by setting the start and end timing of pulse output in the next cycle based on data set in advance at a predetermined address without saving C and PSW to the stack space If the data set in the compare register that defines the start and end of pulse output may cause erroneous pulse output, this is detected and a vector interrupt is generated. Is notified to the CPU that special processing is required.

〔Example〕

 Hereinafter, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a pulse generator showing a first embodiment.

The pulse generator of the present invention includes a CPU 100, a data bus 110,
It comprises an address bus 111, an INTC 112, a program memory 113, a data memory 114, and peripheral hardware 115.

The CPU 100 includes an ALU 101, a temporary register 102, a general-purpose register 103, an address buffer 104 (represented by AB in the figure), a μ address generator 105, a μROM 106, a PC 107, a PSW 108,
It comprises a timing control unit 109.

The INTC 112 includes an interrupt request flag 116 and a form designation flag 119, and outputs an interrupt request signal 117 and a form designation signal 120 to the timing control unit 109. The timing control unit 109 outputs a form change signal 121 of the interrupt request clear signal 118 to the INTC 112.

The INTC112 accepts several interrupt signals from external hardware, determines the priority assigned to each interrupt source, selects one interrupt source with the highest priority, and responds to that interrupt source The interrupt request flag 116 is set. Interrupt request flag 1
When there are n interrupt requests, n and 16 are set for each of the type designation flags 119, but only one set is shown in the figure. Further, an interrupt signal from external hardware, a priority determination unit, and the like are not particularly illustrated because they are not directly related to the gist of the present invention.

The CPU 100 can process an interrupt request from the INTC 112 in two forms. One is the conventional vector interrupt processing, and the other is the processing mode which is the gist of the present invention. When an interrupt occurs, the vector table is not referred to but is set to a specific address in the data memory 114 in advance. This is a mode in which predetermined data processing is executed based on the processed processing mode information. Hereinafter, this predetermined data processing is referred to as a micro service.

Whether or not the vector interrupt is a micro service is specified by the configuration specifying flag 119, and the CPU 100 specifies the configuration specifying flag 119.
Is set to “0” as a vector interrupt,
When "1" is set, it is designated as a microservice.

The peripheral hardware configuration and the operation in the present embodiment are the same as the peripheral hardware configuration shown in FIG. 9 in the conventional example and the above-described operation description, and thus description thereof will be omitted.

Next, processing mode information for specifying the processing mode of the micro service of the present invention will be described. FIG. 2 shows the configuration of the processing mode information. The processing mode information is arranged at a specific address in the data memory 114, and the processing mode information of this example is constituted by a 1-byte header section having a channel pointer and a 2-word microservice channel pointed to by the channel pointer. You.

The micro service channel of this example has a configuration assuming one pulse output, and is composed of word data 1 specifying an output start timing of an output pulse and word data 2 specifying an output end timing of an output pulse. ing.

Word data 1 is word data corresponding to a period from the count value 0 of the timer 901 to the count value at which pulse output is started, of the pulse output output from the port P, and word data 2 is the count value 0 of the timer 901. From
The CPU 100 stores word data corresponding to a period up to the count value at which the pulse output ends, that is, word data for defining the pulse width of the output pulse.

The micro service of this example is activated by the coincidence signals 913 and 914 from the COMPS903 and COMPR904. Before the micro service is started, the CPU 100 initializes a micro service channel and hardware.

FIGS. 3A and 3B are flow charts showing the microservices of the present embodiment, and are actually controlled by the μ program. FIG. 4 shows an example of a pulse output pattern in this embodiment.

Hereinafter, the control operation of the micro service and the pulse output will be described with reference to FIG. 1 to FIG. However, the output F / F 905 is reset, and the description starts from the time when the pulse output from the port P is at a low level.

First, the timer 901 is cleared to all “0” by the coincidence signal 912 of the COMPT 902 and starts counting from the initial value 0. (FIG. 4—timings t0, t3, t6, t9) Next, when the value held in the COMPS 903 matches the count value of the timer 901, a match signal 913 is output. Also match signal 913
Is input to the output F / F 905, and by setting the output F / F 905, the pulse output from the port P is set to a high level.
Further, the coincidence signal 913 performs the above operation and generates an interrupt request to the INTC 112. (FIG. 4—Timings t1, t4, t7) When the INTC 112 receives the interrupt request of the coincidence signal 913, the interrupt request flag 116 corresponding to this source is set and the interrupt request signal 117 is activated.

The timing control unit 109 samples the interrupt request signal 117 at the end of the instruction processing, and samples the configuration instruction means 120 because it is active. When the form instruction unit 120 detects that the value is “1” indicating the micro service, the PC 10
7. The micro service processing entry address of the μROM 106 is generated while holding the information of the PSW 108, and the micro service is started.

Hereinafter, the description of the processing flow processed in accordance with the microprogram command of the microservice will proceed with the flowchart of FIG.

First, the header of the micro service using the coincidence signal 913 as an interrupt source is read from a specific address in the data memory 114, and the address of the micro service channel is detected.

Next, the content of the timer 901 is read, and the count value of the timer read at this time is compared with the word data 1 in the micro service channel corresponding to the micro service processing. (Hereinafter, this read data is referred to as TMO.) As a result of comparison, if word data 1 is smaller than TMO, word data 1 is set to COMPS903.

Next, the timing control unit 109
Outputs the interrupt request clear signal 118 to the INTC 112,
The micro service processing in which the interrupt request flag 116 has been reset ends.

When the micro service processing is completed, the timing control unit 109 restarts the normal instruction processing from the values of the PC 107 and PSW 108 held.

Alternatively, as a result of the comparison, if the word data 1 is larger than the TMO, the word control 1 is not set in the COMPS903, and the timing control unit is instructed by the μ program command.
109 outputs the form change signal 121 to the INTC 112, resets the form designation flag 119, and ends the micro service.

INTC112 has the interrupt request 116 flag set,
Since the mode designation flag 119 is in the reset state, a normal vector interrupt request is issued to the CPU 100, and the above-described vector interrupt process is started.

In the interrupt processing executed here, the processing of setting (updating) the word data 1 to the COMPS 903 is not performed, and the fact that the setting of the word data 1 to the COMPS 903 is not completed is stored. Perform special processing of

After this, the timer 901 continues counting and the COMPR904
When the value held by the timer 901 matches the count value of the timer 901, the matching signal 914 is output. The coincidence signal 914 is input to the output F / F 905, and resetting the output F / F 905 changes the pulse output from the port P to low level. Further, the match signal 91
No. 4 performs the above operation and is generated in response to the interrupt request INTC112. (FIG. 4—Timings t2, t5, t8) When the INTC 112 receives the interrupt request of the coincidence signal 914, the interrupt request flag 116 corresponding to this source is set and the interrupt request signal 117 is activated.

The timing control unit 109 samples the interrupt request signal 117 at the end of the instruction processing, and samples the configuration instruction means 120 because it is active. When the form instruction unit 120 detects that the value is “1” indicating the micro service, the PC 10
7. While maintaining the PSW 108, the micro service processing entry address of the μROM 106 is generated, and the micro service is started.

Thereafter, processing is performed in accordance with the microservice μ program command. The description of the processing flow proceeds according to the flowchart of FIG.

First, the header of the micro service having the coincidence signal 914 as an interrupt source is read from a specific address in the data memory 114, and the position of the micro service channel is detected. COMPR9 word data 2
Store in 04.

Next, the timing control unit 109
Outputs the interrupt request clear signal 118 to the INTC 112,
The interrupt request flag 116 is reset and the micro service processing ends.

When the micro service processing is completed, the timing control unit 109 restarts the normal instruction processing from the values of the PC 107 and PSW 108 held.

After this, the timer 901 continues counting and the COMPT
When the held value of 902 matches the count value of timer 901, CO
MPT 901 outputs match signal 912. This match signal 912 is
The count value is input to the timer 901 and the count value of the timer 901 is initialized to all “0”. Further, the match signal 912 is input to the INTC 112 and requests an interrupt process to the INTC 112 (FIG. 4—timing t3, t6, t9). When the INTC 112 receives the interrupt request of the match signal 912,
The interrupt request flag 116 corresponding to this source is set, and the interrupt request signal 117 is activated.

The timing control unit 109 samples the interrupt request signal 117 at the end of the instruction processing, and samples the configuration instruction unit 120 because it is active. Here, the form instructing means 1
Since 20 is "0", the above-described vector interrupt processing is started.

In the interrupt processing started here, first, if the data update to the COMPS 903 is not completed based on the information on the interrupt processing by the micro service based on the coincidence signal 913, this processing is executed.

Next, at the time of executing the micro service activated by the coincidence signals 913 and 914, the data set in the COMPS 903 and COMPR 904 are set in the word data 1 and the word data 2, and the interrupt processing is terminated.

By executing the interrupt process and the interrupt process using the coincidence signals 913 and 914, the control of the pulse output for one cycle is completed. Therefore, if this operation is repeated, continuous pulse output control can be performed.

In addition, if the value set in the COMPS903 is larger than the count value of the timer at that time, the problem that the pulse output of the next cycle starts to be output within the current cycle will be This can be determined, a vector interrupt can be generated, and the pulse output start timing can always be corrected by software processing.

For this reason, in FIG. 7 of the conventional pulse output pattern example, the erroneous portion of the pattern as shown by the cycle S2 + S3, that is, the period of the timings tX to t6 to t7 to t8 does not appear, and the originally intended pulse waveform Thus, a pulse output waveform as shown in a cycle S2 of FIG. 4 is obtained.

As described above, the pulse generator of the present invention sets the output start timing and output end timing of the output pulse to be output in the next cycle by the interrupt processing started by the coincidence of the current cycle CPMPS 903 and COMPR904. By doing so, it is possible to continuously output pulses.

In this embodiment, the control related to the cycle of the output pulse,
In other words, although the setting data of the COMPT 902 is not updated, if the process of updating the COMPT 902 to predetermined word data is executed successively at the time of the interrupt processing by the coincidence signal 912 output from the COMPT 902, the setting is different for each cycle. Since pulse output with a period can be generated, pulse output control with higher precision can be realized according to the application.

 Next, a second embodiment of the present invention will be described.

In this embodiment, the configuration and the basic operation of the pulse generator are the same as those of the previous embodiment, and therefore, detailed description is omitted here.

Hereinafter, the control operation of the micro service and the pulse output in this embodiment will be described with reference to FIGS. 3 (a), (c) and FIG. However, timer 901
It is assumed that the counting operation is performed, the output F / F 905 is reset, and the pulse output from the port P is at a low level.

The configuration of the micro service channel of this example is the same as that of the first embodiment, and a description thereof will not be repeated.

FIGS. 3 (a) and 3 (c) show a flowchart of the micro service of the present embodiment, and are actually μ program control. FIG. 4 shows an example of a pulse output pattern in this embodiment.

When the held value matches the count value of the timer 901, the COMPS 903 outputs a match signal 913. The match signal 913 sets the output F / F 905 to change the pulse output from the port P to a high level. And INTC112
Generates an interrupt request. This request causes the INTC
The 112 outputs an interrupt request signal 117 to the timing control unit 109. When the timing control unit 109 receives this request, an interrupt process is started and a process for updating the setting data of the COMPS 903 is performed. (FIG. 4—timing t1, t4, t7) However, since this interrupt processing is the same as the interrupt processing started by the coincidence signal 913 in the first embodiment, the description is omitted here. (See FIG. 3 (a) for the processing flow.) On the other hand, the timer 904 continues counting even during the interrupt processing started by the coincidence signal 913, and when the value held in the COMPR904 matches the count value of the timer 904, the COMPR904 Outputs a coincidence signal 914 and resets the output F / F 905, thereby making the pulse output from the port P low level and generating an interrupt request to the INTC 112. In response to this request, the INTC 112 outputs an interrupt request signal 117 to the timing control unit 109. When the timing control unit 109 receives this request, the interrupt processing is started and the COMP
Processing for updating the setting data of R904 is performed. (FIG. 4—timing t2, t5, t8) In the interrupt processing started here, first, the micro service is started. Hereinafter, the description of the processing flow of the micro service proceeds according to the flowchart of FIG.

First, a header to the micro service using the coincidence signal 914 as an interrupt source is read from a specific address in the data memory 114, the position of the micro service channel is detected, and the word data 2 corresponds to the micro service processing. Recognize that

Next, the content of the COMPS 903 is read, and the read value is compared with the word data 2.

If the result of the comparison indicates that the value of word data 2 is smaller than the read value from COMPS903, word data 2 is COMP
After storing in R904, the micro service processing ends. (Corresponding to the relationship between the timings t1 and t2 of the cycle S1 in FIG. 4) When the microservice processing ends, the timing control unit 109 restarts the normal instruction processing from the values of the PCs 107 and PSW 108 held.

Alternatively, as a result of comparison, the value of word data 2 is COMPS9
If the value is larger than the read value from 03, the micro service is terminated without updating the data to the COMPR904, and the normal vector interrupt processing is started this time.

In the vector interrupt processing started here, the pulse output end timing of the next cycle to be set is set to be shorter than the pulse output start timing of the next cycle (already set in the interrupt processing started by the previous match signal 913). In the special processing at the previous timing, processing such as correction of the contents of the word data 2 and setting of the corrected data in the COMPR 904 or, in some cases, resetting of the data in the COMPS 903 is executed.

After the execution of the above processing, the vector interrupt processing ends, and all the interrupt processing started by the coincidence signal 914 ends.

Thereafter, when the value held by the COMPT 902 matches the count value of the timer 901, the COMPT 902 outputs a match signal 912 and requests an interrupt process. Since the interrupt process performed here is the same as in the first embodiment, The description here is omitted.

The pulse output in one cycle can be controlled by the interrupt processing started by the coincidence signals 912, 913, 914 described above. Therefore, by repeatedly performing this operation, control of continuous pulse output can be performed.

Also, the data normally set as the word data 1 and the word data 2 is generated by a program process based on basic data prepared in advance in the data memory 114 and taking into account information from other peripheral hardware and the like. However, if there is an error in the program of the basic data or word data generation process, the timing of starting pulse output, that is, the word data 1 is changed to the timing of terminating pulse output, It is conceivable that 2 sets the combination of word data having a smaller value. In such a case, if the pulse output end timing comes before the pulse output start timing, the pulse output start timing at the pulse output start timing becomes the pulse output end timing within the same cycle. Does not come, the pulse output continues until the pulse output end timing of the next cycle. Such a pulse output may cause a serious problem for the control target as described in the first embodiment.

In such a case, in the present embodiment, in the interrupt processing started by the coincidence signal 414 output from the COMPR904, when the occurrence of the above-described pulse is expected,
The countermeasure is made by correcting the value of the word data 2 to be set as the pulse output end timing of the next cycle, thereby preventing the occurrence of a defective pulse.

〔The invention's effect〕

As described above, the pulse generator of the present invention processes the interrupt for setting (updating) the start and end timings of the pulse output by the microservice and does not generate a vector interrupt request, so that the frequency of the pulse output increases. PC, PSW when switching to the interrupt processing program
When saving to the stack or returning to the main process from the interrupt processing program, the process of restoring the contents of the stack to the PC and PSW does not take up CPU time.

Also, if there is a possibility that the data to be set in the compare register that controls the start and end of pulse output by the microservice with respect to the count value of the timer may cause an erroneous pulse, Is detected, a vector interrupt is activated according to the result, and special processing is performed, so that a normal pulse can always be generated.

Furthermore, in the pulse generator, the number of ports is increased,
That is, even when the number of pulse outputs to be controlled increases, the interrupt processing for all the ports can be dealt with by the micro service in one cycle. For this reason, regarding the increase in the interrupt processing time accompanying the increase in the number of ports, the interrupt processing can be executed in a shorter time than in the case where all the processing is executed by the vector interrupt processing.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of a first embodiment of the present invention, FIG. 2 is a configuration diagram of processing form information of a micro service in the embodiment, FIG. 5, a pulse output pattern diagram from a port P in a conventional example, FIG. 6 is a system configuration diagram in a conventional example, and FIG. 7 is a peripheral hardware configuration diagram in a conventional example. is there. 100, 800 CPU, 101 ALU, 102 temporary register, 103 general-purpose register, 104 address buffer, 105 μ address generator, 106 μROM, 107
PC, 108 ... PSW, 109 ... Timing control unit, 110 ... Data bus, 111 ... Address bus, 112 ... INTC, 113 ...
... program memory, 114 ... data memory, 115 ... peripheral hardware, 116 ... interrupt request flag, 117 ... interrupt request signal, 118 ... interrupt request clear signal, 119 ...
Form designation flag, 120 Form designation signal, 121 Form change signal, 901 Timer, 902,903,904 Compare register, 912,913,914 Match signal, 905 Output F / F.

Claims (2)

(57) [Claims] A central processing unit including a program counter for holding an execution address of an instruction, a means for holding an execution state of a program, a general-purpose register and a microprogram ROM, and an interrupt processing request generated asynchronously to the central processing unit. In a data processing device having an interrupt request generation circuit, a program memory, a data memory, and a peripheral circuit, the peripheral circuit includes a timer, a plurality of comparison registers for comparing the timer, and an output for pulse output. A port for generating a request for predetermined data processing in addition to generation of a crack processing request, and for identifying the interrupt processing request and the predetermined data processing request. And a processing form for designating a processing form of the predetermined data processing in the data memory. When information is stored and the request for the predetermined data processing is generated from the interrupt request generation circuit to the central processing unit, the central processing unit causes the configuration instruction unit to instruct the predetermined data processing. Instruction execution processing is interrupted,
According to the processing mode information, predetermined data in the data memory is compared with the value of the timer or the value of the comparison register at the timing, and when the comparison result is a predetermined condition, the data to the predetermined comparison register is Means for performing transfer, controlling generation of pulses from the output port and generating an interrupt request from the interrupt generation circuit to the central processing unit when the comparison result is not a predetermined condition. Processing equipment. A timer for performing an increment operation by a clock; a first register for storing first word data; a second register for storing second word data larger than the first word data; A first comparison circuit that activates a first control signal by detecting that the count value of the timer matches the first word data stored in the first register, wherein the count value of the timer is A peripheral circuit including a second comparison circuit that detects a match with the second word data stored in a second register and inactivates the first control signal; and the first control signal Is activated, and when the third word data to be written is equal to or less than the first word data, the third word data is stored in the first register. When the third word data is larger than the first word data, the writing of the third word data to the first register is stopped, and the data whose writing is not completed is stored. And a writing means for writing fourth word data into the second register in response to the first control signal becoming inactive.